1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T7001 "A8X" SoC 4 * 5 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 6 * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts. 7 */ 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/apple-aic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/pinctrl/apple.h> 13 14/ { 15 interrupt-parent = <&aic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 serial0 = &serial0; 21 }; 22 23 clkref: clock-ref { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <24000000>; 27 clock-output-names = "clkref"; 28 }; 29 30 cpus { 31 #address-cells = <2>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 compatible = "apple,typhoon"; 36 reg = <0x0 0x0>; 37 cpu-release-addr = <0 0>; /* To be filled in by loader */ 38 enable-method = "spin-table"; 39 device_type = "cpu"; 40 }; 41 42 cpu1: cpu@1 { 43 compatible = "apple,typhoon"; 44 reg = <0x0 0x1>; 45 cpu-release-addr = <0 0>; /* To be filled in by loader */ 46 enable-method = "spin-table"; 47 device_type = "cpu"; 48 }; 49 50 cpu2: cpu@2 { 51 compatible = "apple,typhoon"; 52 reg = <0x0 0x2>; 53 cpu-release-addr = <0 0>; /* To be filled by loader */ 54 enable-method = "spin-table"; 55 device_type = "cpu"; 56 }; 57 }; 58 59 soc { 60 compatible = "simple-bus"; 61 #address-cells = <2>; 62 #size-cells = <2>; 63 nonposted-mmio; 64 ranges; 65 66 serial0: serial@20a0c0000 { 67 compatible = "apple,s5l-uart"; 68 reg = <0x2 0x0a0c0000 0x0 0x4000>; 69 reg-io-width = <4>; 70 interrupt-parent = <&aic>; 71 interrupts = <AIC_IRQ 158 IRQ_TYPE_LEVEL_HIGH>; 72 /* Use the bootloader-enabled clocks for now. */ 73 clocks = <&clkref>, <&clkref>; 74 clock-names = "uart", "clk_uart_baud0"; 75 status = "disabled"; 76 }; 77 78 wdt: watchdog@20e027000 { 79 compatible = "apple,t7000-wdt", "apple,wdt"; 80 reg = <0x2 0x0e027000 0x0 0x1000>; 81 clocks = <&clkref>; 82 interrupt-parent = <&aic>; 83 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 84 }; 85 86 aic: interrupt-controller@20e100000 { 87 compatible = "apple,t7000-aic", "apple,aic"; 88 reg = <0x2 0x0e100000 0x0 0x100000>; 89 #interrupt-cells = <3>; 90 interrupt-controller; 91 }; 92 93 pinctrl: pinctrl@20e300000 { 94 compatible = "apple,t7000-pinctrl", "apple,pinctrl"; 95 reg = <0x2 0x0e300000 0x0 0x100000>; 96 97 gpio-controller; 98 #gpio-cells = <2>; 99 gpio-ranges = <&pinctrl 0 0 184>; 100 apple,npins = <184>; 101 102 interrupt-controller; 103 #interrupt-cells = <2>; 104 interrupt-parent = <&aic>; 105 interrupts = <AIC_IRQ 62 IRQ_TYPE_LEVEL_HIGH>, 106 <AIC_IRQ 63 IRQ_TYPE_LEVEL_HIGH>, 107 <AIC_IRQ 64 IRQ_TYPE_LEVEL_HIGH>, 108 <AIC_IRQ 65 IRQ_TYPE_LEVEL_HIGH>, 109 <AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH>, 110 <AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH>, 111 <AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH>; 112 }; 113 }; 114 115 timer { 116 compatible = "arm,armv8-timer"; 117 interrupt-parent = <&aic>; 118 interrupt-names = "phys", "virt"; 119 /* Note that A8X doesn't actually have a hypervisor (EL2 is not implemented). */ 120 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 121 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 122 }; 123}; 124