1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T7000 "A8" SoC 4 * 5 * Other names: H7P, "Fiji" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts. 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/apple-aic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/pinctrl/apple.h> 15 16/ { 17 interrupt-parent = <&aic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 clkref: clock-ref { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <24000000>; 25 clock-output-names = "clkref"; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 compatible = "apple,typhoon"; 34 reg = <0x0 0x0>; 35 cpu-release-addr = <0 0>; /* To be filled in by loader */ 36 enable-method = "spin-table"; 37 device_type = "cpu"; 38 }; 39 40 cpu1: cpu@1 { 41 compatible = "apple,typhoon"; 42 reg = <0x0 0x1>; 43 cpu-release-addr = <0 0>; /* To be filled in by loader */ 44 enable-method = "spin-table"; 45 device_type = "cpu"; 46 }; 47 }; 48 49 soc { 50 compatible = "simple-bus"; 51 #address-cells = <2>; 52 #size-cells = <2>; 53 nonposted-mmio; 54 ranges; 55 56 serial0: serial@20a0c0000 { 57 compatible = "apple,s5l-uart"; 58 reg = <0x2 0x0a0c0000 0x0 0x4000>; 59 reg-io-width = <4>; 60 interrupt-parent = <&aic>; 61 interrupts = <AIC_IRQ 158 IRQ_TYPE_LEVEL_HIGH>; 62 /* Use the bootloader-enabled clocks for now. */ 63 clocks = <&clkref>, <&clkref>; 64 clock-names = "uart", "clk_uart_baud0"; 65 status = "disabled"; 66 }; 67 68 serial6: serial@20a0d8000 { 69 compatible = "apple,s5l-uart"; 70 reg = <0x2 0x0a0d8000 0x0 0x4000>; 71 reg-io-width = <4>; 72 interrupt-parent = <&aic>; 73 interrupts = <AIC_IRQ 164 IRQ_TYPE_LEVEL_HIGH>; 74 /* Use the bootloader-enabled clocks for now. */ 75 clocks = <&clkref>, <&clkref>; 76 clock-names = "uart", "clk_uart_baud0"; 77 status = "disabled"; 78 }; 79 80 wdt: watchdog@20e027000 { 81 compatible = "apple,t7000-wdt", "apple,wdt"; 82 reg = <0x2 0x0e027000 0x0 0x1000>; 83 clocks = <&clkref>; 84 interrupt-parent = <&aic>; 85 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 86 }; 87 88 aic: interrupt-controller@20e100000 { 89 compatible = "apple,t7000-aic", "apple,aic"; 90 reg = <0x2 0x0e100000 0x0 0x100000>; 91 #interrupt-cells = <3>; 92 interrupt-controller; 93 }; 94 95 pinctrl: pinctrl@20e300000 { 96 compatible = "apple,t7000-pinctrl", "apple,pinctrl"; 97 reg = <0x2 0x0e300000 0x0 0x100000>; 98 99 gpio-controller; 100 #gpio-cells = <2>; 101 gpio-ranges = <&pinctrl 0 0 208>; 102 apple,npins = <208>; 103 104 interrupt-controller; 105 #interrupt-cells = <2>; 106 interrupt-parent = <&aic>; 107 interrupts = <AIC_IRQ 62 IRQ_TYPE_LEVEL_HIGH>, 108 <AIC_IRQ 63 IRQ_TYPE_LEVEL_HIGH>, 109 <AIC_IRQ 64 IRQ_TYPE_LEVEL_HIGH>, 110 <AIC_IRQ 65 IRQ_TYPE_LEVEL_HIGH>, 111 <AIC_IRQ 66 IRQ_TYPE_LEVEL_HIGH>, 112 <AIC_IRQ 67 IRQ_TYPE_LEVEL_HIGH>, 113 <AIC_IRQ 68 IRQ_TYPE_LEVEL_HIGH>; 114 }; 115 }; 116 117 timer { 118 compatible = "arm,armv8-timer"; 119 interrupt-parent = <&aic>; 120 interrupt-names = "phys", "virt"; 121 /* Note that A8 doesn't actually have a hypervisor (EL2 is not implemented). */ 122 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 123 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 124 }; 125}; 126