1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Devices used on die 0 on the Apple T6002 "M1 Ultra" SoC and present on 4 * Apple T6000 / T6001 "M1 Pro" / "M1 Max". 5 * 6 * Copyright The Asahi Linux Contributors 7 */ 8 9 10 nco: clock-controller@28e03c000 { 11 compatible = "apple,t6000-nco", "apple,nco"; 12 reg = <0x2 0x8e03c000 0x0 0x14000>; 13 clocks = <&nco_clkref>; 14 #clock-cells = <1>; 15 }; 16 17 aic: interrupt-controller@28e100000 { 18 compatible = "apple,t6000-aic", "apple,aic2"; 19 #interrupt-cells = <4>; 20 interrupt-controller; 21 reg = <0x2 0x8e100000 0x0 0xc000>, 22 <0x2 0x8e10c000 0x0 0x4>; 23 reg-names = "core", "event"; 24 power-domains = <&ps_aic>; 25 }; 26 27 pinctrl_smc: pinctrl@290820000 { 28 compatible = "apple,t6000-pinctrl", "apple,pinctrl"; 29 reg = <0x2 0x90820000 0x0 0x4000>; 30 31 gpio-controller; 32 #gpio-cells = <2>; 33 gpio-ranges = <&pinctrl_smc 0 0 30>; 34 apple,npins = <30>; 35 36 interrupt-controller; 37 #interrupt-cells = <2>; 38 interrupt-parent = <&aic>; 39 interrupts = <AIC_IRQ 0 743 IRQ_TYPE_LEVEL_HIGH>, 40 <AIC_IRQ 0 744 IRQ_TYPE_LEVEL_HIGH>, 41 <AIC_IRQ 0 745 IRQ_TYPE_LEVEL_HIGH>, 42 <AIC_IRQ 0 746 IRQ_TYPE_LEVEL_HIGH>, 43 <AIC_IRQ 0 747 IRQ_TYPE_LEVEL_HIGH>, 44 <AIC_IRQ 0 748 IRQ_TYPE_LEVEL_HIGH>, 45 <AIC_IRQ 0 749 IRQ_TYPE_LEVEL_HIGH>; 46 }; 47 48 wdt: watchdog@2922b0000 { 49 compatible = "apple,t6000-wdt", "apple,wdt"; 50 reg = <0x2 0x922b0000 0x0 0x4000>; 51 clocks = <&clkref>; 52 interrupt-parent = <&aic>; 53 interrupts = <AIC_IRQ 0 631 IRQ_TYPE_LEVEL_HIGH>; 54 }; 55 56 sio_dart_0: iommu@39b004000 { 57 compatible = "apple,t6000-dart"; 58 reg = <0x3 0x9b004000 0x0 0x4000>; 59 interrupt-parent = <&aic>; 60 interrupts = <AIC_IRQ 0 1130 IRQ_TYPE_LEVEL_HIGH>; 61 #iommu-cells = <1>; 62 power-domains = <&ps_sio_cpu>; 63 }; 64 65 sio_dart_1: iommu@39b008000 { 66 compatible = "apple,t6000-dart"; 67 reg = <0x3 0x9b008000 0x0 0x8000>; 68 interrupt-parent = <&aic>; 69 interrupts = <AIC_IRQ 0 1130 IRQ_TYPE_LEVEL_HIGH>; 70 #iommu-cells = <1>; 71 power-domains = <&ps_sio_cpu>; 72 }; 73 74 i2c0: i2c@39b040000 { 75 compatible = "apple,t6000-i2c", "apple,i2c"; 76 reg = <0x3 0x9b040000 0x0 0x4000>; 77 clocks = <&clkref>; 78 interrupt-parent = <&aic>; 79 interrupts = <AIC_IRQ 0 1119 IRQ_TYPE_LEVEL_HIGH>; 80 pinctrl-0 = <&i2c0_pins>; 81 pinctrl-names = "default"; 82 power-domains = <&ps_i2c0>; 83 #address-cells = <0x1>; 84 #size-cells = <0x0>; 85 }; 86 87 i2c1: i2c@39b044000 { 88 compatible = "apple,t6000-i2c", "apple,i2c"; 89 reg = <0x3 0x9b044000 0x0 0x4000>; 90 clocks = <&clkref>; 91 interrupt-parent = <&aic>; 92 interrupts = <AIC_IRQ 0 1120 IRQ_TYPE_LEVEL_HIGH>; 93 pinctrl-0 = <&i2c1_pins>; 94 pinctrl-names = "default"; 95 power-domains = <&ps_i2c1>; 96 #address-cells = <0x1>; 97 #size-cells = <0x0>; 98 status = "disabled"; 99 }; 100 101 i2c2: i2c@39b048000 { 102 compatible = "apple,t6000-i2c", "apple,i2c"; 103 reg = <0x3 0x9b048000 0x0 0x4000>; 104 clocks = <&clkref>; 105 interrupt-parent = <&aic>; 106 interrupts = <AIC_IRQ 0 1121 IRQ_TYPE_LEVEL_HIGH>; 107 pinctrl-0 = <&i2c2_pins>; 108 pinctrl-names = "default"; 109 power-domains = <&ps_i2c2>; 110 #address-cells = <0x1>; 111 #size-cells = <0x0>; 112 status = "disabled"; 113 }; 114 115 i2c3: i2c@39b04c000 { 116 compatible = "apple,t6000-i2c", "apple,i2c"; 117 reg = <0x3 0x9b04c000 0x0 0x4000>; 118 clocks = <&clkref>; 119 interrupt-parent = <&aic>; 120 interrupts = <AIC_IRQ 0 1122 IRQ_TYPE_LEVEL_HIGH>; 121 pinctrl-0 = <&i2c3_pins>; 122 pinctrl-names = "default"; 123 power-domains = <&ps_i2c3>; 124 #address-cells = <0x1>; 125 #size-cells = <0x0>; 126 status = "disabled"; 127 }; 128 129 i2c4: i2c@39b050000 { 130 compatible = "apple,t6000-i2c", "apple,i2c"; 131 reg = <0x3 0x9b050000 0x0 0x4000>; 132 clocks = <&clkref>; 133 interrupt-parent = <&aic>; 134 interrupts = <AIC_IRQ 0 1123 IRQ_TYPE_LEVEL_HIGH>; 135 pinctrl-0 = <&i2c4_pins>; 136 pinctrl-names = "default"; 137 power-domains = <&ps_i2c4>; 138 #address-cells = <0x1>; 139 #size-cells = <0x0>; 140 status = "disabled"; 141 }; 142 143 i2c5: i2c@39b054000 { 144 compatible = "apple,t6000-i2c", "apple,i2c"; 145 reg = <0x3 0x9b054000 0x0 0x4000>; 146 clocks = <&clkref>; 147 interrupt-parent = <&aic>; 148 interrupts = <AIC_IRQ 0 1124 IRQ_TYPE_LEVEL_HIGH>; 149 pinctrl-0 = <&i2c5_pins>; 150 pinctrl-names = "default"; 151 power-domains = <&ps_i2c5>; 152 #address-cells = <0x1>; 153 #size-cells = <0x0>; 154 status = "disabled"; 155 }; 156 157 serial0: serial@39b200000 { 158 compatible = "apple,s5l-uart"; 159 reg = <0x3 0x9b200000 0x0 0x1000>; 160 reg-io-width = <4>; 161 interrupt-parent = <&aic>; 162 interrupts = <AIC_IRQ 0 1097 IRQ_TYPE_LEVEL_HIGH>; 163 /* 164 * TODO: figure out the clocking properly, there may 165 * be a third selectable clock. 166 */ 167 clocks = <&clkref>, <&clkref>; 168 clock-names = "uart", "clk_uart_baud0"; 169 power-domains = <&ps_uart0>; 170 status = "disabled"; 171 }; 172 173 admac: dma-controller@39b400000 { 174 compatible = "apple,t6000-admac", "apple,admac"; 175 reg = <0x3 0x9b400000 0x0 0x34000>; 176 #dma-cells = <1>; 177 dma-channels = <16>; 178 interrupts-extended = <0>, 179 <&aic AIC_IRQ 0 1118 IRQ_TYPE_LEVEL_HIGH>, 180 <0>, 181 <0>; 182 iommus = <&sio_dart_0 2>, <&sio_dart_1 2>; 183 power-domains = <&ps_sio_adma>; 184 resets = <&ps_audio_p>; 185 }; 186 187 mca: mca@39b600000 { 188 compatible = "apple,t6000-mca", "apple,mca"; 189 reg = <0x3 0x9b600000 0x0 0x10000>, 190 <0x3 0x9b500000 0x0 0x20000>; 191 clocks = <&nco 0>, <&nco 1>, <&nco 2>, <&nco 3>; 192 dmas = <&admac 0>, <&admac 1>, <&admac 2>, <&admac 3>, 193 <&admac 4>, <&admac 5>, <&admac 6>, <&admac 7>, 194 <&admac 8>, <&admac 9>, <&admac 10>, <&admac 11>, 195 <&admac 12>, <&admac 13>, <&admac 14>, <&admac 15>; 196 dma-names = "tx0a", "rx0a", "tx0b", "rx0b", 197 "tx1a", "rx1a", "tx1b", "rx1b", 198 "tx2a", "rx2a", "tx2b", "rx2b", 199 "tx3a", "rx3a", "tx3b", "rx3b"; 200 interrupt-parent = <&aic>; 201 interrupts = <AIC_IRQ 0 1112 IRQ_TYPE_LEVEL_HIGH>, 202 <AIC_IRQ 0 1113 IRQ_TYPE_LEVEL_HIGH>, 203 <AIC_IRQ 0 1114 IRQ_TYPE_LEVEL_HIGH>, 204 <AIC_IRQ 0 1115 IRQ_TYPE_LEVEL_HIGH>; 205 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>, 206 <&ps_mca2>, <&ps_mca3>; 207 resets = <&ps_audio_p>; 208 #sound-dai-cells = <1>; 209 }; 210 211 pcie0_dart_0: iommu@581008000 { 212 compatible = "apple,t6000-dart"; 213 reg = <0x5 0x81008000 0x0 0x4000>; 214 #iommu-cells = <1>; 215 interrupt-parent = <&aic>; 216 interrupts = <AIC_IRQ 0 1271 IRQ_TYPE_LEVEL_HIGH>; 217 power-domains = <&ps_apcie_gp_sys>; 218 }; 219 220 pcie0_dart_1: iommu@582008000 { 221 compatible = "apple,t6000-dart"; 222 reg = <0x5 0x82008000 0x0 0x4000>; 223 #iommu-cells = <1>; 224 interrupt-parent = <&aic>; 225 interrupts = <AIC_IRQ 0 1274 IRQ_TYPE_LEVEL_HIGH>; 226 power-domains = <&ps_apcie_gp_sys>; 227 }; 228 229 pcie0_dart_2: iommu@583008000 { 230 compatible = "apple,t6000-dart"; 231 reg = <0x5 0x83008000 0x0 0x4000>; 232 #iommu-cells = <1>; 233 interrupt-parent = <&aic>; 234 interrupts = <AIC_IRQ 0 1277 IRQ_TYPE_LEVEL_HIGH>; 235 power-domains = <&ps_apcie_gp_sys>; 236 }; 237 238 pcie0_dart_3: iommu@584008000 { 239 compatible = "apple,t6000-dart"; 240 reg = <0x5 0x84008000 0x0 0x4000>; 241 #iommu-cells = <1>; 242 interrupt-parent = <&aic>; 243 interrupts = <AIC_IRQ 0 1280 IRQ_TYPE_LEVEL_HIGH>; 244 power-domains = <&ps_apcie_gp_sys>; 245 }; 246 247 pcie0: pcie@590000000 { 248 compatible = "apple,t6000-pcie", "apple,pcie"; 249 device_type = "pci"; 250 251 reg = <0x5 0x90000000 0x0 0x1000000>, 252 <0x5 0x80000000 0x0 0x100000>, 253 <0x5 0x81000000 0x0 0x4000>, 254 <0x5 0x82000000 0x0 0x4000>, 255 <0x5 0x83000000 0x0 0x4000>, 256 <0x5 0x84000000 0x0 0x4000>; 257 reg-names = "config", "rc", "port0", "port1", "port2", "port3"; 258 259 interrupt-parent = <&aic>; 260 interrupts = <AIC_IRQ 0 1270 IRQ_TYPE_LEVEL_HIGH>, 261 <AIC_IRQ 0 1273 IRQ_TYPE_LEVEL_HIGH>, 262 <AIC_IRQ 0 1276 IRQ_TYPE_LEVEL_HIGH>, 263 <AIC_IRQ 0 1279 IRQ_TYPE_LEVEL_HIGH>; 264 265 msi-controller; 266 msi-parent = <&pcie0>; 267 msi-ranges = <&aic AIC_IRQ 0 1581 IRQ_TYPE_EDGE_RISING 32>; 268 269 270 iommu-map = <0x100 &pcie0_dart_0 1 1>, 271 <0x200 &pcie0_dart_1 1 1>, 272 <0x300 &pcie0_dart_2 1 1>, 273 <0x400 &pcie0_dart_3 1 1>; 274 iommu-map-mask = <0xff00>; 275 276 bus-range = <0 4>; 277 #address-cells = <3>; 278 #size-cells = <2>; 279 ranges = <0x43000000 0x5 0xa0000000 0x5 0xa0000000 0x0 0x20000000>, 280 <0x02000000 0x0 0xc0000000 0x5 0xc0000000 0x0 0x40000000>; 281 282 power-domains = <&ps_apcie_gp_sys>; 283 pinctrl-0 = <&pcie_pins>; 284 pinctrl-names = "default"; 285 286 port00: pci@0,0 { 287 device_type = "pci"; 288 reg = <0x0 0x0 0x0 0x0 0x0>; 289 reset-gpios = <&pinctrl_ap 4 GPIO_ACTIVE_LOW>; 290 291 #address-cells = <3>; 292 #size-cells = <2>; 293 ranges; 294 295 interrupt-controller; 296 #interrupt-cells = <1>; 297 298 interrupt-map-mask = <0 0 0 7>; 299 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 300 <0 0 0 2 &port00 0 0 0 1>, 301 <0 0 0 3 &port00 0 0 0 2>, 302 <0 0 0 4 &port00 0 0 0 3>; 303 }; 304 305 port01: pci@1,0 { 306 device_type = "pci"; 307 reg = <0x800 0x0 0x0 0x0 0x0>; 308 reset-gpios = <&pinctrl_ap 5 GPIO_ACTIVE_LOW>; 309 310 #address-cells = <3>; 311 #size-cells = <2>; 312 ranges; 313 314 interrupt-controller; 315 #interrupt-cells = <1>; 316 317 interrupt-map-mask = <0 0 0 7>; 318 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 319 <0 0 0 2 &port01 0 0 0 1>, 320 <0 0 0 3 &port01 0 0 0 2>, 321 <0 0 0 4 &port01 0 0 0 3>; 322 }; 323 324 port02: pci@2,0 { 325 device_type = "pci"; 326 reg = <0x1000 0x0 0x0 0x0 0x0>; 327 reset-gpios = <&pinctrl_ap 6 GPIO_ACTIVE_LOW>; 328 329 #address-cells = <3>; 330 #size-cells = <2>; 331 ranges; 332 333 interrupt-controller; 334 #interrupt-cells = <1>; 335 336 interrupt-map-mask = <0 0 0 7>; 337 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 338 <0 0 0 2 &port02 0 0 0 1>, 339 <0 0 0 3 &port02 0 0 0 2>, 340 <0 0 0 4 &port02 0 0 0 3>; 341 }; 342 343 port03: pci@3,0 { 344 device_type = "pci"; 345 reg = <0x1800 0x0 0x0 0x0 0x0>; 346 reset-gpios = <&pinctrl_ap 7 GPIO_ACTIVE_LOW>; 347 348 #address-cells = <3>; 349 #size-cells = <2>; 350 ranges; 351 352 interrupt-controller; 353 #interrupt-cells = <1>; 354 355 interrupt-map-mask = <0 0 0 7>; 356 interrupt-map = <0 0 0 1 &port03 0 0 0 0>, 357 <0 0 0 2 &port03 0 0 0 1>, 358 <0 0 0 3 &port03 0 0 0 2>, 359 <0 0 0 4 &port03 0 0 0 3>; 360 }; 361 }; 362