1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T6002 "M1 Ultra" SoC 4 * 5 * Other names: H13J, "Jade 2C" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/spmi/spmi.h> 16 17#include "multi-die-cpp.h" 18 19#include "t600x-common.dtsi" 20 21/ { 22 compatible = "apple,t6002", "apple,arm-platform"; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 cpus { 28 cpu-map { 29 cluster3 { 30 core0 { 31 cpu = <&cpu_e10>; 32 }; 33 core1 { 34 cpu = <&cpu_e11>; 35 }; 36 }; 37 38 cluster4 { 39 core0 { 40 cpu = <&cpu_p20>; 41 }; 42 core1 { 43 cpu = <&cpu_p21>; 44 }; 45 core2 { 46 cpu = <&cpu_p22>; 47 }; 48 core3 { 49 cpu = <&cpu_p23>; 50 }; 51 }; 52 53 cluster5 { 54 core0 { 55 cpu = <&cpu_p30>; 56 }; 57 core1 { 58 cpu = <&cpu_p31>; 59 }; 60 core2 { 61 cpu = <&cpu_p32>; 62 }; 63 core3 { 64 cpu = <&cpu_p33>; 65 }; 66 }; 67 }; 68 69 cpu_e10: cpu@800 { 70 compatible = "apple,icestorm"; 71 device_type = "cpu"; 72 reg = <0x0 0x800>; 73 enable-method = "spin-table"; 74 cpu-release-addr = <0 0>; /* To be filled by loader */ 75 next-level-cache = <&l2_cache_3>; 76 i-cache-size = <0x20000>; 77 d-cache-size = <0x10000>; 78 operating-points-v2 = <&icestorm_opp>; 79 capacity-dmips-mhz = <714>; 80 performance-domains = <&cpufreq_e_die1>; 81 }; 82 83 cpu_e11: cpu@801 { 84 compatible = "apple,icestorm"; 85 device_type = "cpu"; 86 reg = <0x0 0x801>; 87 enable-method = "spin-table"; 88 cpu-release-addr = <0 0>; /* To be filled by loader */ 89 next-level-cache = <&l2_cache_3>; 90 i-cache-size = <0x20000>; 91 d-cache-size = <0x10000>; 92 operating-points-v2 = <&icestorm_opp>; 93 capacity-dmips-mhz = <714>; 94 performance-domains = <&cpufreq_e_die1>; 95 }; 96 97 cpu_p20: cpu@10900 { 98 compatible = "apple,firestorm"; 99 device_type = "cpu"; 100 reg = <0x0 0x10900>; 101 enable-method = "spin-table"; 102 cpu-release-addr = <0 0>; /* To be filled by loader */ 103 next-level-cache = <&l2_cache_4>; 104 i-cache-size = <0x30000>; 105 d-cache-size = <0x20000>; 106 operating-points-v2 = <&firestorm_opp>; 107 capacity-dmips-mhz = <1024>; 108 performance-domains = <&cpufreq_p0_die1>; 109 }; 110 111 cpu_p21: cpu@10901 { 112 compatible = "apple,firestorm"; 113 device_type = "cpu"; 114 reg = <0x0 0x10901>; 115 enable-method = "spin-table"; 116 cpu-release-addr = <0 0>; /* To be filled by loader */ 117 next-level-cache = <&l2_cache_4>; 118 i-cache-size = <0x30000>; 119 d-cache-size = <0x20000>; 120 operating-points-v2 = <&firestorm_opp>; 121 capacity-dmips-mhz = <1024>; 122 performance-domains = <&cpufreq_p0_die1>; 123 }; 124 125 cpu_p22: cpu@10902 { 126 compatible = "apple,firestorm"; 127 device_type = "cpu"; 128 reg = <0x0 0x10902>; 129 enable-method = "spin-table"; 130 cpu-release-addr = <0 0>; /* To be filled by loader */ 131 next-level-cache = <&l2_cache_4>; 132 i-cache-size = <0x30000>; 133 d-cache-size = <0x20000>; 134 operating-points-v2 = <&firestorm_opp>; 135 capacity-dmips-mhz = <1024>; 136 performance-domains = <&cpufreq_p0_die1>; 137 }; 138 139 cpu_p23: cpu@10903 { 140 compatible = "apple,firestorm"; 141 device_type = "cpu"; 142 reg = <0x0 0x10903>; 143 enable-method = "spin-table"; 144 cpu-release-addr = <0 0>; /* To be filled by loader */ 145 next-level-cache = <&l2_cache_4>; 146 i-cache-size = <0x30000>; 147 d-cache-size = <0x20000>; 148 operating-points-v2 = <&firestorm_opp>; 149 capacity-dmips-mhz = <1024>; 150 performance-domains = <&cpufreq_p0_die1>; 151 }; 152 153 cpu_p30: cpu@10a00 { 154 compatible = "apple,firestorm"; 155 device_type = "cpu"; 156 reg = <0x0 0x10a00>; 157 enable-method = "spin-table"; 158 cpu-release-addr = <0 0>; /* To be filled by loader */ 159 next-level-cache = <&l2_cache_5>; 160 i-cache-size = <0x30000>; 161 d-cache-size = <0x20000>; 162 operating-points-v2 = <&firestorm_opp>; 163 capacity-dmips-mhz = <1024>; 164 performance-domains = <&cpufreq_p1_die1>; 165 }; 166 167 cpu_p31: cpu@10a01 { 168 compatible = "apple,firestorm"; 169 device_type = "cpu"; 170 reg = <0x0 0x10a01>; 171 enable-method = "spin-table"; 172 cpu-release-addr = <0 0>; /* To be filled by loader */ 173 next-level-cache = <&l2_cache_5>; 174 i-cache-size = <0x30000>; 175 d-cache-size = <0x20000>; 176 operating-points-v2 = <&firestorm_opp>; 177 capacity-dmips-mhz = <1024>; 178 performance-domains = <&cpufreq_p1_die1>; 179 }; 180 181 cpu_p32: cpu@10a02 { 182 compatible = "apple,firestorm"; 183 device_type = "cpu"; 184 reg = <0x0 0x10a02>; 185 enable-method = "spin-table"; 186 cpu-release-addr = <0 0>; /* To be filled by loader */ 187 next-level-cache = <&l2_cache_5>; 188 i-cache-size = <0x30000>; 189 d-cache-size = <0x20000>; 190 operating-points-v2 = <&firestorm_opp>; 191 capacity-dmips-mhz = <1024>; 192 performance-domains = <&cpufreq_p1_die1>; 193 }; 194 195 cpu_p33: cpu@10a03 { 196 compatible = "apple,firestorm"; 197 device_type = "cpu"; 198 reg = <0x0 0x10a03>; 199 enable-method = "spin-table"; 200 cpu-release-addr = <0 0>; /* To be filled by loader */ 201 next-level-cache = <&l2_cache_5>; 202 i-cache-size = <0x30000>; 203 d-cache-size = <0x20000>; 204 operating-points-v2 = <&firestorm_opp>; 205 capacity-dmips-mhz = <1024>; 206 performance-domains = <&cpufreq_p1_die1>; 207 }; 208 209 l2_cache_3: l2-cache-3 { 210 compatible = "cache"; 211 cache-level = <2>; 212 cache-unified; 213 cache-size = <0x400000>; 214 }; 215 216 l2_cache_4: l2-cache-4 { 217 compatible = "cache"; 218 cache-level = <2>; 219 cache-unified; 220 cache-size = <0xc00000>; 221 }; 222 223 l2_cache_5: l2-cache-5 { 224 compatible = "cache"; 225 cache-level = <2>; 226 cache-unified; 227 cache-size = <0xc00000>; 228 }; 229 }; 230 231 die0: soc@200000000 { 232 compatible = "simple-bus"; 233 #address-cells = <2>; 234 #size-cells = <2>; 235 ranges = <0x2 0x0 0x2 0x0 0x4 0x0>, 236 <0x5 0x80000000 0x5 0x80000000 0x1 0x80000000>, 237 <0x7 0x0 0x7 0x0 0xf 0x80000000>; 238 nonposted-mmio; 239 240 // filled via templated includes at the end of the file 241 }; 242 243 die1: soc@2200000000 { 244 compatible = "simple-bus"; 245 #address-cells = <2>; 246 #size-cells = <2>; 247 ranges = <0x2 0x0 0x22 0x0 0x4 0x0>, 248 <0x7 0x0 0x27 0x0 0xf 0x80000000>; 249 nonposted-mmio; 250 251 // filled via templated includes at the end of the file 252 }; 253}; 254 255#define DIE 256#define DIE_NO 0 257 258&die0 { 259 #include "t600x-die0.dtsi" 260 #include "t600x-dieX.dtsi" 261}; 262 263#include "t600x-pmgr.dtsi" 264#include "t600x-gpio-pins.dtsi" 265 266#undef DIE 267#undef DIE_NO 268 269#define DIE _die1 270#define DIE_NO 1 271 272&die1 { 273 #include "t600x-dieX.dtsi" 274 #include "t600x-nvme.dtsi" 275}; 276 277#include "t600x-pmgr.dtsi" 278 279#undef DIE 280#undef DIE_NO 281 282&aic { 283 affinities { 284 e-core-pmu-affinity { 285 apple,fiq-index = <AIC_CPU_PMU_E>; 286 cpus = <&cpu_e00 &cpu_e01 287 &cpu_e10 &cpu_e11>; 288 }; 289 290 p-core-pmu-affinity { 291 apple,fiq-index = <AIC_CPU_PMU_P>; 292 cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03 293 &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13 294 &cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23 295 &cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>; 296 }; 297 }; 298}; 299 300&ps_gfx { 301 // On t6002, the die0 GPU power domain needs both AFR power domains 302 power-domains = <&ps_afr>, <&ps_afr_die1>; 303}; 304 305&gpu { 306 compatible = "apple,agx-g13d", "apple,agx-g13s"; 307}; 308