1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T6002 "M1 Ultra" SoC 4 * 5 * Other names: H13J, "Jade 2C" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15#include "multi-die-cpp.h" 16 17#include "t600x-common.dtsi" 18 19/ { 20 compatible = "apple,t6002", "apple,arm-platform"; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 cpus { 26 cpu-map { 27 cluster3 { 28 core0 { 29 cpu = <&cpu_e10>; 30 }; 31 core1 { 32 cpu = <&cpu_e11>; 33 }; 34 }; 35 36 cluster4 { 37 core0 { 38 cpu = <&cpu_p20>; 39 }; 40 core1 { 41 cpu = <&cpu_p21>; 42 }; 43 core2 { 44 cpu = <&cpu_p22>; 45 }; 46 core3 { 47 cpu = <&cpu_p23>; 48 }; 49 }; 50 51 cluster5 { 52 core0 { 53 cpu = <&cpu_p30>; 54 }; 55 core1 { 56 cpu = <&cpu_p31>; 57 }; 58 core2 { 59 cpu = <&cpu_p32>; 60 }; 61 core3 { 62 cpu = <&cpu_p33>; 63 }; 64 }; 65 }; 66 67 cpu_e10: cpu@800 { 68 compatible = "apple,icestorm"; 69 device_type = "cpu"; 70 reg = <0x0 0x800>; 71 enable-method = "spin-table"; 72 cpu-release-addr = <0 0>; /* To be filled by loader */ 73 next-level-cache = <&l2_cache_3>; 74 i-cache-size = <0x20000>; 75 d-cache-size = <0x10000>; 76 operating-points-v2 = <&icestorm_opp>; 77 capacity-dmips-mhz = <714>; 78 performance-domains = <&cpufreq_e_die1>; 79 }; 80 81 cpu_e11: cpu@801 { 82 compatible = "apple,icestorm"; 83 device_type = "cpu"; 84 reg = <0x0 0x801>; 85 enable-method = "spin-table"; 86 cpu-release-addr = <0 0>; /* To be filled by loader */ 87 next-level-cache = <&l2_cache_3>; 88 i-cache-size = <0x20000>; 89 d-cache-size = <0x10000>; 90 operating-points-v2 = <&icestorm_opp>; 91 capacity-dmips-mhz = <714>; 92 performance-domains = <&cpufreq_e_die1>; 93 }; 94 95 cpu_p20: cpu@10900 { 96 compatible = "apple,firestorm"; 97 device_type = "cpu"; 98 reg = <0x0 0x10900>; 99 enable-method = "spin-table"; 100 cpu-release-addr = <0 0>; /* To be filled by loader */ 101 next-level-cache = <&l2_cache_4>; 102 i-cache-size = <0x30000>; 103 d-cache-size = <0x20000>; 104 operating-points-v2 = <&firestorm_opp>; 105 capacity-dmips-mhz = <1024>; 106 performance-domains = <&cpufreq_p0_die1>; 107 }; 108 109 cpu_p21: cpu@10901 { 110 compatible = "apple,firestorm"; 111 device_type = "cpu"; 112 reg = <0x0 0x10901>; 113 enable-method = "spin-table"; 114 cpu-release-addr = <0 0>; /* To be filled by loader */ 115 next-level-cache = <&l2_cache_4>; 116 i-cache-size = <0x30000>; 117 d-cache-size = <0x20000>; 118 operating-points-v2 = <&firestorm_opp>; 119 capacity-dmips-mhz = <1024>; 120 performance-domains = <&cpufreq_p0_die1>; 121 }; 122 123 cpu_p22: cpu@10902 { 124 compatible = "apple,firestorm"; 125 device_type = "cpu"; 126 reg = <0x0 0x10902>; 127 enable-method = "spin-table"; 128 cpu-release-addr = <0 0>; /* To be filled by loader */ 129 next-level-cache = <&l2_cache_4>; 130 i-cache-size = <0x30000>; 131 d-cache-size = <0x20000>; 132 operating-points-v2 = <&firestorm_opp>; 133 capacity-dmips-mhz = <1024>; 134 performance-domains = <&cpufreq_p0_die1>; 135 }; 136 137 cpu_p23: cpu@10903 { 138 compatible = "apple,firestorm"; 139 device_type = "cpu"; 140 reg = <0x0 0x10903>; 141 enable-method = "spin-table"; 142 cpu-release-addr = <0 0>; /* To be filled by loader */ 143 next-level-cache = <&l2_cache_4>; 144 i-cache-size = <0x30000>; 145 d-cache-size = <0x20000>; 146 operating-points-v2 = <&firestorm_opp>; 147 capacity-dmips-mhz = <1024>; 148 performance-domains = <&cpufreq_p0_die1>; 149 }; 150 151 cpu_p30: cpu@10a00 { 152 compatible = "apple,firestorm"; 153 device_type = "cpu"; 154 reg = <0x0 0x10a00>; 155 enable-method = "spin-table"; 156 cpu-release-addr = <0 0>; /* To be filled by loader */ 157 next-level-cache = <&l2_cache_5>; 158 i-cache-size = <0x30000>; 159 d-cache-size = <0x20000>; 160 operating-points-v2 = <&firestorm_opp>; 161 capacity-dmips-mhz = <1024>; 162 performance-domains = <&cpufreq_p1_die1>; 163 }; 164 165 cpu_p31: cpu@10a01 { 166 compatible = "apple,firestorm"; 167 device_type = "cpu"; 168 reg = <0x0 0x10a01>; 169 enable-method = "spin-table"; 170 cpu-release-addr = <0 0>; /* To be filled by loader */ 171 next-level-cache = <&l2_cache_5>; 172 i-cache-size = <0x30000>; 173 d-cache-size = <0x20000>; 174 operating-points-v2 = <&firestorm_opp>; 175 capacity-dmips-mhz = <1024>; 176 performance-domains = <&cpufreq_p1_die1>; 177 }; 178 179 cpu_p32: cpu@10a02 { 180 compatible = "apple,firestorm"; 181 device_type = "cpu"; 182 reg = <0x0 0x10a02>; 183 enable-method = "spin-table"; 184 cpu-release-addr = <0 0>; /* To be filled by loader */ 185 next-level-cache = <&l2_cache_5>; 186 i-cache-size = <0x30000>; 187 d-cache-size = <0x20000>; 188 operating-points-v2 = <&firestorm_opp>; 189 capacity-dmips-mhz = <1024>; 190 performance-domains = <&cpufreq_p1_die1>; 191 }; 192 193 cpu_p33: cpu@10a03 { 194 compatible = "apple,firestorm"; 195 device_type = "cpu"; 196 reg = <0x0 0x10a03>; 197 enable-method = "spin-table"; 198 cpu-release-addr = <0 0>; /* To be filled by loader */ 199 next-level-cache = <&l2_cache_5>; 200 i-cache-size = <0x30000>; 201 d-cache-size = <0x20000>; 202 operating-points-v2 = <&firestorm_opp>; 203 capacity-dmips-mhz = <1024>; 204 performance-domains = <&cpufreq_p1_die1>; 205 }; 206 207 l2_cache_3: l2-cache-3 { 208 compatible = "cache"; 209 cache-level = <2>; 210 cache-unified; 211 cache-size = <0x400000>; 212 }; 213 214 l2_cache_4: l2-cache-4 { 215 compatible = "cache"; 216 cache-level = <2>; 217 cache-unified; 218 cache-size = <0xc00000>; 219 }; 220 221 l2_cache_5: l2-cache-5 { 222 compatible = "cache"; 223 cache-level = <2>; 224 cache-unified; 225 cache-size = <0xc00000>; 226 }; 227 }; 228 229 die0: soc@200000000 { 230 compatible = "simple-bus"; 231 #address-cells = <2>; 232 #size-cells = <2>; 233 ranges = <0x2 0x0 0x2 0x0 0x4 0x0>, 234 <0x5 0x80000000 0x5 0x80000000 0x1 0x80000000>, 235 <0x7 0x0 0x7 0x0 0xf 0x80000000>; 236 nonposted-mmio; 237 238 // filled via templated includes at the end of the file 239 }; 240 241 die1: soc@2200000000 { 242 compatible = "simple-bus"; 243 #address-cells = <2>; 244 #size-cells = <2>; 245 ranges = <0x2 0x0 0x22 0x0 0x4 0x0>, 246 <0x7 0x0 0x27 0x0 0xf 0x80000000>; 247 nonposted-mmio; 248 249 // filled via templated includes at the end of the file 250 }; 251}; 252 253#define DIE 254#define DIE_NO 0 255 256&die0 { 257 #include "t600x-die0.dtsi" 258 #include "t600x-dieX.dtsi" 259}; 260 261#include "t600x-pmgr.dtsi" 262#include "t600x-gpio-pins.dtsi" 263 264#undef DIE 265#undef DIE_NO 266 267#define DIE _die1 268#define DIE_NO 1 269 270&die1 { 271 #include "t600x-dieX.dtsi" 272 #include "t600x-nvme.dtsi" 273}; 274 275#include "t600x-pmgr.dtsi" 276 277#undef DIE 278#undef DIE_NO 279 280&aic { 281 affinities { 282 e-core-pmu-affinity { 283 apple,fiq-index = <AIC_CPU_PMU_E>; 284 cpus = <&cpu_e00 &cpu_e01 285 &cpu_e10 &cpu_e11>; 286 }; 287 288 p-core-pmu-affinity { 289 apple,fiq-index = <AIC_CPU_PMU_P>; 290 cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03 291 &cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13 292 &cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23 293 &cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>; 294 }; 295 }; 296}; 297 298&ps_gfx { 299 // On t6002, the die0 GPU power domain needs both AFR power domains 300 power-domains = <&ps_afr>, <&ps_afr_die1>; 301}; 302