1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple S8001 "A9X" SoC 4 * 5 * Other names: H8G, "Elba" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "apple,twister"; 33 reg = <0x0 0x0>; 34 cpu-release-addr = <0 0>; /* To be filled in by loader */ 35 operating-points-v2 = <&twister_opp>; 36 performance-domains = <&cpufreq>; 37 enable-method = "spin-table"; 38 device_type = "cpu"; 39 next-level-cache = <&l2_cache>; 40 i-cache-size = <0x10000>; 41 d-cache-size = <0x10000>; 42 }; 43 44 cpu1: cpu@1 { 45 compatible = "apple,twister"; 46 reg = <0x0 0x1>; 47 cpu-release-addr = <0 0>; /* To be filled in by loader */ 48 operating-points-v2 = <&twister_opp>; 49 performance-domains = <&cpufreq>; 50 enable-method = "spin-table"; 51 device_type = "cpu"; 52 next-level-cache = <&l2_cache>; 53 i-cache-size = <0x10000>; 54 d-cache-size = <0x10000>; 55 }; 56 57 l2_cache: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 cache-unified; 61 cache-size = <0x300000>; 62 }; 63 }; 64 65 twister_opp: opp-table { 66 compatible = "operating-points-v2"; 67 68 opp01 { 69 opp-hz = /bits/ 64 <300000000>; 70 opp-level = <1>; 71 clock-latency-ns = <800>; 72 }; 73 opp02 { 74 opp-hz = /bits/ 64 <396000000>; 75 opp-level = <2>; 76 clock-latency-ns = <53000>; 77 }; 78 opp03 { 79 opp-hz = /bits/ 64 <792000000>; 80 opp-level = <3>; 81 clock-latency-ns = <18000>; 82 }; 83 opp04 { 84 opp-hz = /bits/ 64 <1080000000>; 85 opp-level = <4>; 86 clock-latency-ns = <21000>; 87 }; 88 opp05 { 89 opp-hz = /bits/ 64 <1440000000>; 90 opp-level = <5>; 91 clock-latency-ns = <25000>; 92 }; 93 opp06 { 94 opp-hz = /bits/ 64 <1800000000>; 95 opp-level = <6>; 96 clock-latency-ns = <33000>; 97 }; 98 opp07 { 99 opp-hz = /bits/ 64 <2160000000>; 100 opp-level = <7>; 101 clock-latency-ns = <45000>; 102 }; 103#if 0 104 /* Not available until CPU deep sleep is implemented */ 105 opp08 { 106 opp-hz = /bits/ 64 <2160000000>; 107 opp-level = <8>; 108 clock-latency-ns = <45000>; 109 turbo-mode; 110 }; 111#endif 112 }; 113 114 soc { 115 compatible = "simple-bus"; 116 #address-cells = <2>; 117 #size-cells = <2>; 118 nonposted-mmio; 119 ranges; 120 121 cpufreq: performance-controller@202220000 { 122 compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 123 reg = <0x2 0x02220000 0 0x1000>; 124 #performance-domain-cells = <0>; 125 }; 126 127 serial0: serial@20a0c0000 { 128 compatible = "apple,s5l-uart"; 129 reg = <0x2 0x0a0c0000 0x0 0x4000>; 130 reg-io-width = <4>; 131 interrupt-parent = <&aic>; 132 interrupts = <AIC_IRQ 218 IRQ_TYPE_LEVEL_HIGH>; 133 /* Use the bootloader-enabled clocks for now. */ 134 clocks = <&clkref>, <&clkref>; 135 clock-names = "uart", "clk_uart_baud0"; 136 power-domains = <&ps_uart0>; 137 status = "disabled"; 138 }; 139 140 i2c0: i2c@20a110000 { 141 compatible = "apple,s8000-i2c", "apple,i2c"; 142 reg = <0x2 0x0a110000 0x0 0x1000>; 143 clocks = <&clkref>; 144 interrupt-parent = <&aic>; 145 interrupts = <AIC_IRQ 232 IRQ_TYPE_LEVEL_HIGH>; 146 pinctrl-0 = <&i2c0_pins>; 147 pinctrl-names = "default"; 148 power-domains = <&ps_i2c0>; 149 #address-cells = <1>; 150 #size-cells = <0>; 151 status = "disabled"; 152 }; 153 154 i2c1: i2c@20a111000 { 155 compatible = "apple,s8000-i2c", "apple,i2c"; 156 reg = <0x2 0x0a111000 0x0 0x1000>; 157 clocks = <&clkref>; 158 interrupt-parent = <&aic>; 159 interrupts = <AIC_IRQ 233 IRQ_TYPE_LEVEL_HIGH>; 160 pinctrl-0 = <&i2c1_pins>; 161 pinctrl-names = "default"; 162 power-domains = <&ps_i2c1>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 status = "disabled"; 166 }; 167 168 i2c2: i2c@20a112000 { 169 compatible = "apple,s8000-i2c", "apple,i2c"; 170 reg = <0x2 0x0a112000 0x0 0x1000>; 171 clocks = <&clkref>; 172 interrupt-parent = <&aic>; 173 interrupts = <AIC_IRQ 234 IRQ_TYPE_LEVEL_HIGH>; 174 pinctrl-0 = <&i2c2_pins>; 175 pinctrl-names = "default"; 176 power-domains = <&ps_i2c2>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 status = "disabled"; 180 }; 181 182 i2c3: i2c@20a113000 { 183 compatible = "apple,s8000-i2c", "apple,i2c"; 184 reg = <0x2 0x0a113000 0x0 0x1000>; 185 clocks = <&clkref>; 186 interrupt-parent = <&aic>; 187 interrupts = <AIC_IRQ 235 IRQ_TYPE_LEVEL_HIGH>; 188 pinctrl-0 = <&i2c3_pins>; 189 pinctrl-names = "default"; 190 power-domains = <&ps_i2c3>; 191 #address-cells = <1>; 192 #size-cells = <0>; 193 status = "disabled"; 194 }; 195 196 pmgr: power-management@20e000000 { 197 compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 198 #address-cells = <1>; 199 #size-cells = <1>; 200 201 reg = <0x2 0xe000000 0 0x8c000>; 202 }; 203 204 aic: interrupt-controller@20e100000 { 205 compatible = "apple,s8000-aic", "apple,aic"; 206 reg = <0x2 0x0e100000 0x0 0x100000>; 207 #interrupt-cells = <3>; 208 interrupt-controller; 209 power-domains = <&ps_aic>; 210 }; 211 212 pinctrl_ap: pinctrl@20f100000 { 213 compatible = "apple,s8000-pinctrl", "apple,pinctrl"; 214 reg = <0x2 0x0f100000 0x0 0x100000>; 215 power-domains = <&ps_gpio>; 216 217 gpio-controller; 218 #gpio-cells = <2>; 219 gpio-ranges = <&pinctrl_ap 0 0 219>; 220 apple,npins = <219>; 221 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 interrupt-parent = <&aic>; 225 interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, 226 <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, 227 <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, 228 <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 229 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 230 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 231 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; 232 233 i2c0_pins: i2c0-pins { 234 pinmux = <APPLE_PINMUX(165, 1)>, 235 <APPLE_PINMUX(164, 1)>; 236 }; 237 238 i2c1_pins: i2c1-pins { 239 pinmux = <APPLE_PINMUX(178, 1)>, 240 <APPLE_PINMUX(177, 1)>; 241 }; 242 243 i2c2_pins: i2c2-pins { 244 pinmux = <APPLE_PINMUX(132, 1)>, 245 <APPLE_PINMUX(131, 1)>; 246 }; 247 248 i2c3_pins: i2c3-pins { 249 pinmux = <APPLE_PINMUX(115, 1)>, 250 <APPLE_PINMUX(114, 1)>; 251 }; 252 }; 253 254 pinctrl_aop: pinctrl@2100f0000 { 255 compatible = "apple,s8000-pinctrl", "apple,pinctrl"; 256 reg = <0x2 0x100f0000 0x0 0x100000>; 257 power-domains = <&ps_aop_gpio>; 258 259 gpio-controller; 260 #gpio-cells = <2>; 261 gpio-ranges = <&pinctrl_aop 0 0 28>; 262 apple,npins = <28>; 263 264 interrupt-controller; 265 #interrupt-cells = <2>; 266 interrupt-parent = <&aic>; 267 interrupts = <AIC_IRQ 128 IRQ_TYPE_LEVEL_HIGH>, 268 <AIC_IRQ 129 IRQ_TYPE_LEVEL_HIGH>, 269 <AIC_IRQ 130 IRQ_TYPE_LEVEL_HIGH>, 270 <AIC_IRQ 131 IRQ_TYPE_LEVEL_HIGH>, 271 <AIC_IRQ 132 IRQ_TYPE_LEVEL_HIGH>, 272 <AIC_IRQ 133 IRQ_TYPE_LEVEL_HIGH>, 273 <AIC_IRQ 134 IRQ_TYPE_LEVEL_HIGH>; 274 }; 275 276 pmgr_mini: power-management@210200000 { 277 compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 278 #address-cells = <1>; 279 #size-cells = <1>; 280 281 reg = <0x2 0x10200000 0 0x84000>; 282 }; 283 284 wdt: watchdog@2102b0000 { 285 compatible = "apple,s8000-wdt", "apple,wdt"; 286 reg = <0x2 0x102b0000 0x0 0x4000>; 287 clocks = <&clkref>; 288 interrupt-parent = <&aic>; 289 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 290 }; 291 }; 292 293 timer { 294 compatible = "arm,armv8-timer"; 295 interrupt-parent = <&aic>; 296 interrupt-names = "phys", "virt"; 297 /* Note that A9X doesn't actually have a hypervisor (EL2 is not implemented). */ 298 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 299 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 300 }; 301}; 302 303#include "s8001-pmgr.dtsi" 304