1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple S8000 "A9" (Samsung) SoC 4 * 5 * Other names: H8P, "Maui" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "apple,twister"; 33 reg = <0x0 0x0>; 34 cpu-release-addr = <0 0>; /* To be filled in by loader */ 35 enable-method = "spin-table"; 36 device_type = "cpu"; 37 }; 38 39 cpu1: cpu@1 { 40 compatible = "apple,twister"; 41 reg = <0x0 0x1>; 42 cpu-release-addr = <0 0>; /* To be filled in by loader */ 43 enable-method = "spin-table"; 44 device_type = "cpu"; 45 }; 46 }; 47 48 soc { 49 compatible = "simple-bus"; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 nonposted-mmio; 53 ranges; 54 55 serial0: serial@20a0c0000 { 56 compatible = "apple,s5l-uart"; 57 reg = <0x2 0x0a0c0000 0x0 0x4000>; 58 reg-io-width = <4>; 59 interrupt-parent = <&aic>; 60 interrupts = <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>; 61 /* Use the bootloader-enabled clocks for now. */ 62 clocks = <&clkref>, <&clkref>; 63 clock-names = "uart", "clk_uart_baud0"; 64 status = "disabled"; 65 }; 66 67 aic: interrupt-controller@20e100000 { 68 compatible = "apple,s8000-aic", "apple,aic"; 69 reg = <0x2 0x0e100000 0x0 0x100000>; 70 #interrupt-cells = <3>; 71 interrupt-controller; 72 }; 73 74 pinctrl_ap: pinctrl@20f100000 { 75 compatible = "apple,s8000-pinctrl", "apple,pinctrl"; 76 reg = <0x2 0x0f100000 0x0 0x100000>; 77 78 gpio-controller; 79 #gpio-cells = <2>; 80 gpio-ranges = <&pinctrl_ap 0 0 208>; 81 apple,npins = <208>; 82 83 interrupt-controller; 84 #interrupt-cells = <2>; 85 interrupt-parent = <&aic>; 86 interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, 87 <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, 88 <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, 89 <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 90 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 91 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 92 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; 93 }; 94 95 pinctrl_aop: pinctrl@2100f0000 { 96 compatible = "apple,s8000-pinctrl", "apple,pinctrl"; 97 reg = <0x2 0x100f0000 0x0 0x100000>; 98 99 gpio-controller; 100 #gpio-cells = <2>; 101 gpio-ranges = <&pinctrl_aop 0 0 42>; 102 apple,npins = <42>; 103 104 interrupt-controller; 105 #interrupt-cells = <2>; 106 interrupt-parent = <&aic>; 107 interrupts = <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>, 108 <AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>, 109 <AIC_IRQ 115 IRQ_TYPE_LEVEL_HIGH>, 110 <AIC_IRQ 116 IRQ_TYPE_LEVEL_HIGH>, 111 <AIC_IRQ 117 IRQ_TYPE_LEVEL_HIGH>, 112 <AIC_IRQ 118 IRQ_TYPE_LEVEL_HIGH>, 113 <AIC_IRQ 119 IRQ_TYPE_LEVEL_HIGH>; 114 }; 115 116 wdt: watchdog@2102b0000 { 117 compatible = "apple,s8000-wdt", "apple,wdt"; 118 reg = <0x2 0x102b0000 0x0 0x4000>; 119 clocks = <&clkref>; 120 interrupt-parent = <&aic>; 121 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 122 }; 123 }; 124 125 timer { 126 compatible = "arm,armv8-timer"; 127 interrupt-parent = <&aic>; 128 interrupt-names = "phys", "virt"; 129 /* Note that A9 doesn't actually have a hypervisor (EL2 is not implemented). */ 130 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 131 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 132 }; 133}; 134 135/* 136 * The A9 was made by two separate fabs on two different process 137 * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made 138 * the S8003 (APL1022) on 16nm. While they are seemingly the same, 139 * they do have distinct part numbers and devices using them have 140 * distinct model names. There are currently no known differences 141 * between these as far as Linux is concerned, but let's keep things 142 * structured properly to make it easier to alter the behaviour of 143 * one of the chips if need be. 144 */ 145