1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple S8000/S8003 "A9" SoC 4 * 5 * This file contains parts common to both variants of A9 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 interrupt-parent = <&aic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 clkref: clock-ref { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "clkref"; 25 }; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "apple,twister"; 33 reg = <0x0 0x0>; 34 cpu-release-addr = <0 0>; /* To be filled in by loader */ 35 operating-points-v2 = <&twister_opp>; 36 performance-domains = <&cpufreq>; 37 enable-method = "spin-table"; 38 device_type = "cpu"; 39 }; 40 41 cpu1: cpu@1 { 42 compatible = "apple,twister"; 43 reg = <0x0 0x1>; 44 cpu-release-addr = <0 0>; /* To be filled in by loader */ 45 operating-points-v2 = <&twister_opp>; 46 performance-domains = <&cpufreq>; 47 enable-method = "spin-table"; 48 device_type = "cpu"; 49 }; 50 }; 51 52 soc { 53 compatible = "simple-bus"; 54 #address-cells = <2>; 55 #size-cells = <2>; 56 nonposted-mmio; 57 ranges; 58 59 cpufreq: performance-controller@202220000 { 60 compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; 61 reg = <0x2 0x02220000 0 0x1000>; 62 #performance-domain-cells = <0>; 63 }; 64 65 serial0: serial@20a0c0000 { 66 compatible = "apple,s5l-uart"; 67 reg = <0x2 0x0a0c0000 0x0 0x4000>; 68 reg-io-width = <4>; 69 interrupt-parent = <&aic>; 70 interrupts = <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>; 71 /* Use the bootloader-enabled clocks for now. */ 72 clocks = <&clkref>, <&clkref>; 73 clock-names = "uart", "clk_uart_baud0"; 74 power-domains = <&ps_uart0>; 75 status = "disabled"; 76 }; 77 78 pmgr: power-management@20e000000 { 79 compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 80 #address-cells = <1>; 81 #size-cells = <1>; 82 83 reg = <0x2 0xe000000 0 0x8c000>; 84 }; 85 86 aic: interrupt-controller@20e100000 { 87 compatible = "apple,s8000-aic", "apple,aic"; 88 reg = <0x2 0x0e100000 0x0 0x100000>; 89 #interrupt-cells = <3>; 90 interrupt-controller; 91 power-domains = <&ps_aic>; 92 }; 93 94 dwi_bl: backlight@20e200080 { 95 compatible = "apple,s8000-dwi-bl", "apple,dwi-bl"; 96 reg = <0x2 0x0e200080 0x0 0x8>; 97 power-domains = <&ps_dwi>; 98 status = "disabled"; 99 }; 100 101 pinctrl_ap: pinctrl@20f100000 { 102 compatible = "apple,s8000-pinctrl", "apple,pinctrl"; 103 reg = <0x2 0x0f100000 0x0 0x100000>; 104 power-domains = <&ps_gpio>; 105 106 gpio-controller; 107 #gpio-cells = <2>; 108 gpio-ranges = <&pinctrl_ap 0 0 208>; 109 apple,npins = <208>; 110 111 interrupt-controller; 112 #interrupt-cells = <2>; 113 interrupt-parent = <&aic>; 114 interrupts = <AIC_IRQ 42 IRQ_TYPE_LEVEL_HIGH>, 115 <AIC_IRQ 43 IRQ_TYPE_LEVEL_HIGH>, 116 <AIC_IRQ 44 IRQ_TYPE_LEVEL_HIGH>, 117 <AIC_IRQ 45 IRQ_TYPE_LEVEL_HIGH>, 118 <AIC_IRQ 46 IRQ_TYPE_LEVEL_HIGH>, 119 <AIC_IRQ 47 IRQ_TYPE_LEVEL_HIGH>, 120 <AIC_IRQ 48 IRQ_TYPE_LEVEL_HIGH>; 121 }; 122 123 pinctrl_aop: pinctrl@2100f0000 { 124 compatible = "apple,s8000-pinctrl", "apple,pinctrl"; 125 reg = <0x2 0x100f0000 0x0 0x100000>; 126 power-domains = <&ps_aop_gpio>; 127 128 gpio-controller; 129 #gpio-cells = <2>; 130 gpio-ranges = <&pinctrl_aop 0 0 42>; 131 apple,npins = <42>; 132 133 interrupt-controller; 134 #interrupt-cells = <2>; 135 interrupt-parent = <&aic>; 136 interrupts = <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>, 137 <AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>, 138 <AIC_IRQ 115 IRQ_TYPE_LEVEL_HIGH>, 139 <AIC_IRQ 116 IRQ_TYPE_LEVEL_HIGH>, 140 <AIC_IRQ 117 IRQ_TYPE_LEVEL_HIGH>, 141 <AIC_IRQ 118 IRQ_TYPE_LEVEL_HIGH>, 142 <AIC_IRQ 119 IRQ_TYPE_LEVEL_HIGH>; 143 }; 144 145 pmgr_mini: power-management@210200000 { 146 compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 147 #address-cells = <1>; 148 #size-cells = <1>; 149 150 reg = <0x2 0x10200000 0 0x84000>; 151 }; 152 153 wdt: watchdog@2102b0000 { 154 compatible = "apple,s8000-wdt", "apple,wdt"; 155 reg = <0x2 0x102b0000 0x0 0x4000>; 156 clocks = <&clkref>; 157 interrupt-parent = <&aic>; 158 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 159 }; 160 }; 161 162 timer { 163 compatible = "arm,armv8-timer"; 164 interrupt-parent = <&aic>; 165 interrupt-names = "phys", "virt"; 166 /* Note that A9 doesn't actually have a hypervisor (EL2 is not implemented). */ 167 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 168 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 169 }; 170}; 171 172#include "s800-0-3-pmgr.dtsi" 173 174/* 175 * The A9 was made by two separate fabs on two different process 176 * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made 177 * the S8003 (APL1022) on 16nm. There are some minor differences 178 * such as timing in cpufreq state transistions. 179 */ 180