1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple S5L8960X "A7" SoC 4 * 5 * Other Names: H6, "Alcatraz" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts. 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/apple-aic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/pinctrl/apple.h> 15 16/ { 17 interrupt-parent = <&aic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 clkref: clock-ref { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <24000000>; 25 clock-output-names = "clkref"; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 compatible = "apple,cyclone"; 34 reg = <0x0 0x0>; 35 cpu-release-addr = <0 0>; /* To be filled by loader */ 36 operating-points-v2 = <&cyclone_opp>; 37 performance-domains = <&cpufreq>; 38 enable-method = "spin-table"; 39 device_type = "cpu"; 40 next-level-cache = <&l2_cache>; 41 i-cache-size = <0x10000>; 42 d-cache-size = <0x10000>; 43 }; 44 45 cpu1: cpu@1 { 46 compatible = "apple,cyclone"; 47 reg = <0x0 0x1>; 48 cpu-release-addr = <0 0>; /* To be filled by loader */ 49 operating-points-v2 = <&cyclone_opp>; 50 performance-domains = <&cpufreq>; 51 enable-method = "spin-table"; 52 device_type = "cpu"; 53 next-level-cache = <&l2_cache>; 54 i-cache-size = <0x10000>; 55 d-cache-size = <0x10000>; 56 }; 57 58 l2_cache: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 cache-size = <0x100000>; 63 }; 64 }; 65 66 soc { 67 compatible = "simple-bus"; 68 #address-cells = <2>; 69 #size-cells = <2>; 70 nonposted-mmio; 71 ranges; 72 73 cpufreq: performance-controller@202220000 { 74 compatible = "apple,s5l8960x-cluster-cpufreq"; 75 reg = <0x2 0x02220000 0 0x1000>; 76 #performance-domain-cells = <0>; 77 }; 78 79 serial0: serial@20a0a0000 { 80 compatible = "apple,s5l-uart"; 81 reg = <0x2 0x0a0a0000 0x0 0x4000>; 82 reg-io-width = <4>; 83 interrupt-parent = <&aic>; 84 interrupts = <AIC_IRQ 140 IRQ_TYPE_LEVEL_HIGH>; 85 /* Use the bootloader-enabled clocks for now. */ 86 clocks = <&clkref>, <&clkref>; 87 clock-names = "uart", "clk_uart_baud0"; 88 power-domains = <&ps_uart0>; 89 status = "disabled"; 90 }; 91 92 i2c0: i2c@20a110000 { 93 compatible = "apple,s5l8960x-i2c", "apple,i2c"; 94 reg = <0x2 0x0a110000 0x0 0x1000>; 95 clocks = <&clkref>; 96 interrupt-parent = <&aic>; 97 interrupts = <AIC_IRQ 154 IRQ_TYPE_LEVEL_HIGH>; 98 pinctrl-0 = <&i2c0_pins>; 99 pinctrl-names = "default"; 100 power-domains = <&ps_i2c0>; 101 #address-cells = <1>; 102 #size-cells = <0>; 103 status = "disabled"; 104 }; 105 106 i2c1: i2c@20a111000 { 107 compatible = "apple,s5l8960x-i2c", "apple,i2c"; 108 reg = <0x2 0x0a111000 0x0 0x1000>; 109 clocks = <&clkref>; 110 interrupt-parent = <&aic>; 111 interrupts = <AIC_IRQ 155 IRQ_TYPE_LEVEL_HIGH>; 112 pinctrl-0 = <&i2c1_pins>; 113 pinctrl-names = "default"; 114 power-domains = <&ps_i2c1>; 115 #address-cells = <1>; 116 #size-cells = <0>; 117 status = "disabled"; 118 }; 119 120 i2c2: i2c@20a112000 { 121 compatible = "apple,s5l8960x-i2c", "apple,i2c"; 122 reg = <0x2 0x0a112000 0x0 0x1000>; 123 clocks = <&clkref>; 124 interrupt-parent = <&aic>; 125 interrupts = <AIC_IRQ 156 IRQ_TYPE_LEVEL_HIGH>; 126 pinctrl-0 = <&i2c2_pins>; 127 pinctrl-names = "default"; 128 power-domains = <&ps_i2c2>; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 status = "disabled"; 132 }; 133 134 i2c3: i2c@20a113000 { 135 compatible = "apple,s5l8960x-i2c", "apple,i2c"; 136 reg = <0x2 0x0a113000 0x0 0x1000>; 137 clocks = <&clkref>; 138 interrupt-parent = <&aic>; 139 interrupts = <AIC_IRQ 157 IRQ_TYPE_LEVEL_HIGH>; 140 pinctrl-0 = <&i2c3_pins>; 141 pinctrl-names = "default"; 142 power-domains = <&ps_i2c3>; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 status = "disabled"; 146 }; 147 148 pmgr: power-management@20e000000 { 149 compatible = "apple,s5l8960x-pmgr", "apple,pmgr", "syscon", "simple-mfd"; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 reg = <0x2 0xe000000 0 0x24000>; 154 }; 155 156 wdt: watchdog@20e027000 { 157 compatible = "apple,s5l8960x-wdt", "apple,wdt"; 158 reg = <0x2 0x0e027000 0x0 0x1000>; 159 clocks = <&clkref>; 160 interrupt-parent = <&aic>; 161 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 162 }; 163 164 aic: interrupt-controller@20e100000 { 165 compatible = "apple,s5l8960x-aic", "apple,aic"; 166 reg = <0x2 0x0e100000 0x0 0x100000>; 167 #interrupt-cells = <3>; 168 interrupt-controller; 169 power-domains = <&ps_aic>; 170 }; 171 172 dwi_bl: backlight@20e200010 { 173 compatible = "apple,s5l8960x-dwi-bl", "apple,dwi-bl"; 174 reg = <0x2 0x0e200010 0x0 0x8>; 175 power-domains = <&ps_dwi>; 176 status = "disabled"; 177 }; 178 179 pinctrl: pinctrl@20e300000 { 180 compatible = "apple,s5l8960x-pinctrl", "apple,pinctrl"; 181 reg = <0x2 0x0e300000 0x0 0x100000>; 182 power-domains = <&ps_gpio>; 183 184 gpio-controller; 185 #gpio-cells = <2>; 186 gpio-ranges = <&pinctrl 0 0 200>; 187 apple,npins = <200>; 188 189 interrupt-controller; 190 #interrupt-cells = <2>; 191 interrupt-parent = <&aic>; 192 interrupts = <AIC_IRQ 108 IRQ_TYPE_LEVEL_HIGH>, 193 <AIC_IRQ 109 IRQ_TYPE_LEVEL_HIGH>, 194 <AIC_IRQ 110 IRQ_TYPE_LEVEL_HIGH>, 195 <AIC_IRQ 111 IRQ_TYPE_LEVEL_HIGH>, 196 <AIC_IRQ 112 IRQ_TYPE_LEVEL_HIGH>, 197 <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>, 198 <AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>; 199 200 i2c0_pins: i2c0-pins { 201 pinmux = <APPLE_PINMUX(81, 1)>, 202 <APPLE_PINMUX(80, 1)>; 203 }; 204 205 i2c1_pins: i2c1-pins { 206 pinmux = <APPLE_PINMUX(83, 1)>, 207 <APPLE_PINMUX(82, 1)>; 208 }; 209 210 i2c2_pins: i2c2-pins { 211 pinmux = <APPLE_PINMUX(101, 1)>, 212 <APPLE_PINMUX(100, 1)>; 213 }; 214 215 i2c3_pins: i2c3-pins { 216 pinmux = <APPLE_PINMUX(172, 1)>, 217 <APPLE_PINMUX(171, 1)>; 218 }; 219 }; 220 }; 221 222 timer { 223 compatible = "arm,armv8-timer"; 224 interrupt-parent = <&aic>; 225 interrupt-names = "phys", "virt"; 226 /* Note that A7 doesn't actually have a hypervisor (EL2 is not implemented). */ 227 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 228 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 229 }; 230}; 231 232#include "s5l8960x-pmgr.dtsi" 233