1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple S5L8960X "A7" SoC 4 * 5 * Other Names: H6, "Alcatraz" 6 * 7 * Copyright (c) 2022, Konrad Dybcio <konradybcio@kernel.org> 8 * Based on Asahi Linux's M1 (t8103.dtsi) and Corellium's A10 efforts. 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/apple-aic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/pinctrl/apple.h> 15 16/ { 17 interrupt-parent = <&aic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 clkref: clock-ref { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <24000000>; 25 clock-output-names = "clkref"; 26 }; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 compatible = "apple,cyclone"; 34 reg = <0x0 0x0>; 35 cpu-release-addr = <0 0>; /* To be filled by loader */ 36 enable-method = "spin-table"; 37 device_type = "cpu"; 38 }; 39 40 cpu1: cpu@1 { 41 compatible = "apple,cyclone"; 42 reg = <0x0 0x1>; 43 cpu-release-addr = <0 0>; /* To be filled by loader */ 44 enable-method = "spin-table"; 45 device_type = "cpu"; 46 }; 47 }; 48 49 soc { 50 compatible = "simple-bus"; 51 #address-cells = <2>; 52 #size-cells = <2>; 53 nonposted-mmio; 54 ranges; 55 56 serial0: serial@20a0a0000 { 57 compatible = "apple,s5l-uart"; 58 reg = <0x2 0x0a0a0000 0x0 0x4000>; 59 reg-io-width = <4>; 60 interrupt-parent = <&aic>; 61 interrupts = <AIC_IRQ 140 IRQ_TYPE_LEVEL_HIGH>; 62 /* Use the bootloader-enabled clocks for now. */ 63 clocks = <&clkref>, <&clkref>; 64 clock-names = "uart", "clk_uart_baud0"; 65 status = "disabled"; 66 }; 67 68 wdt: watchdog@20e027000 { 69 compatible = "apple,s5l8960x-wdt", "apple,wdt"; 70 reg = <0x2 0x0e027000 0x0 0x1000>; 71 clocks = <&clkref>; 72 interrupt-parent = <&aic>; 73 interrupts = <AIC_IRQ 4 IRQ_TYPE_LEVEL_HIGH>; 74 }; 75 76 aic: interrupt-controller@20e100000 { 77 compatible = "apple,s5l8960x-aic", "apple,aic"; 78 reg = <0x2 0x0e100000 0x0 0x100000>; 79 #interrupt-cells = <3>; 80 interrupt-controller; 81 }; 82 83 pinctrl: pinctrl@20e300000 { 84 compatible = "apple,s5l8960x-pinctrl", "apple,pinctrl"; 85 reg = <0x2 0x0e300000 0x0 0x100000>; 86 87 gpio-controller; 88 #gpio-cells = <2>; 89 gpio-ranges = <&pinctrl 0 0 200>; 90 apple,npins = <200>; 91 92 interrupt-controller; 93 #interrupt-cells = <2>; 94 interrupt-parent = <&aic>; 95 interrupts = <AIC_IRQ 108 IRQ_TYPE_LEVEL_HIGH>, 96 <AIC_IRQ 109 IRQ_TYPE_LEVEL_HIGH>, 97 <AIC_IRQ 110 IRQ_TYPE_LEVEL_HIGH>, 98 <AIC_IRQ 111 IRQ_TYPE_LEVEL_HIGH>, 99 <AIC_IRQ 112 IRQ_TYPE_LEVEL_HIGH>, 100 <AIC_IRQ 113 IRQ_TYPE_LEVEL_HIGH>, 101 <AIC_IRQ 114 IRQ_TYPE_LEVEL_HIGH>; 102 }; 103 }; 104 105 timer { 106 compatible = "arm,armv8-timer"; 107 interrupt-parent = <&aic>; 108 interrupt-names = "phys", "virt"; 109 /* Note that A7 doesn't actually have a hypervisor (EL2 is not implemented). */ 110 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 111 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>; 112 }; 113}; 114