xref: /linux/arch/arm64/boot/dts/apm/apm-storm.dtsi (revision d8d2b1f81530988abe2e2bfaceec1c5d30b9a0b4) 
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
4 *
5 * Copyright (C) 2013, Applied Micro Circuits Corporation
6 */
7
8/ {
9	compatible = "apm,xgene-storm";
10	interrupt-parent = <&gic>;
11	#address-cells = <2>;
12	#size-cells = <2>;
13
14	cpus {
15		#address-cells = <2>;
16		#size-cells = <0>;
17
18		cpu@0 {
19			device_type = "cpu";
20			compatible = "apm,potenza";
21			reg = <0x0 0x000>;
22			enable-method = "spin-table";
23			cpu-release-addr = <0x1 0x0000fff8>;
24			next-level-cache = <&xgene_L2_0>;
25		};
26		cpu@1 {
27			device_type = "cpu";
28			compatible = "apm,potenza";
29			reg = <0x0 0x001>;
30			enable-method = "spin-table";
31			cpu-release-addr = <0x1 0x0000fff8>;
32			next-level-cache = <&xgene_L2_0>;
33		};
34		cpu@100 {
35			device_type = "cpu";
36			compatible = "apm,potenza";
37			reg = <0x0 0x100>;
38			enable-method = "spin-table";
39			cpu-release-addr = <0x1 0x0000fff8>;
40			next-level-cache = <&xgene_L2_1>;
41		};
42		cpu@101 {
43			device_type = "cpu";
44			compatible = "apm,potenza";
45			reg = <0x0 0x101>;
46			enable-method = "spin-table";
47			cpu-release-addr = <0x1 0x0000fff8>;
48			next-level-cache = <&xgene_L2_1>;
49		};
50		cpu@200 {
51			device_type = "cpu";
52			compatible = "apm,potenza";
53			reg = <0x0 0x200>;
54			enable-method = "spin-table";
55			cpu-release-addr = <0x1 0x0000fff8>;
56			next-level-cache = <&xgene_L2_2>;
57		};
58		cpu@201 {
59			device_type = "cpu";
60			compatible = "apm,potenza";
61			reg = <0x0 0x201>;
62			enable-method = "spin-table";
63			cpu-release-addr = <0x1 0x0000fff8>;
64			next-level-cache = <&xgene_L2_2>;
65		};
66		cpu@300 {
67			device_type = "cpu";
68			compatible = "apm,potenza";
69			reg = <0x0 0x300>;
70			enable-method = "spin-table";
71			cpu-release-addr = <0x1 0x0000fff8>;
72			next-level-cache = <&xgene_L2_3>;
73		};
74		cpu@301 {
75			device_type = "cpu";
76			compatible = "apm,potenza";
77			reg = <0x0 0x301>;
78			enable-method = "spin-table";
79			cpu-release-addr = <0x1 0x0000fff8>;
80			next-level-cache = <&xgene_L2_3>;
81		};
82		xgene_L2_0: l2-cache-0 {
83			compatible = "cache";
84			cache-level = <2>;
85			cache-unified;
86		};
87		xgene_L2_1: l2-cache-1 {
88			compatible = "cache";
89			cache-level = <2>;
90			cache-unified;
91		};
92		xgene_L2_2: l2-cache-2 {
93			compatible = "cache";
94			cache-level = <2>;
95			cache-unified;
96		};
97		xgene_L2_3: l2-cache-3 {
98			compatible = "cache";
99			cache-level = <2>;
100			cache-unified;
101		};
102	};
103
104	gic: interrupt-controller@78010000 {
105		compatible = "arm,cortex-a15-gic";
106		#address-cells = <0>;
107		#interrupt-cells = <3>;
108		interrupt-controller;
109		reg = <0x0 0x78010000 0x0 0x1000>,	/* GIC Dist */
110		      <0x0 0x78020000 0x0 0x1000>,	/* GIC CPU */
111		      <0x0 0x78040000 0x0 0x2000>,	/* GIC VCPU Control */
112		      <0x0 0x78060000 0x0 0x2000>;	/* GIC VCPU */
113		interrupts = <1 9 0xf04>;	/* GIC Maintenence IRQ */
114	};
115
116	refclk: clock-100000000 {
117		compatible = "fixed-clock";
118		#clock-cells = <0>;
119		clock-frequency = <100000000>;
120		clock-output-names = "refclk";
121	};
122
123	timer {
124		compatible = "arm,armv8-timer";
125		interrupts = <1 0 0xff08>,	/* Secure Phys IRQ */
126			     <1 13 0xff08>,	/* Non-secure Phys IRQ */
127			     <1 14 0xff08>,	/* Virt IRQ */
128			     <1 15 0xff08>;	/* Hyp IRQ */
129		clock-frequency = <50000000>;
130	};
131
132	pmu {
133		compatible = "apm,potenza-pmu";
134		interrupts = <1 12 0xff04>;
135	};
136
137	i2cslimpro {
138		compatible = "apm,xgene-slimpro-i2c";
139		mboxes = <&mailbox 0>;
140	};
141
142	hwmonslimpro {
143		compatible = "apm,xgene-slimpro-hwmon";
144		mboxes = <&mailbox 7>;
145	};
146
147	soc {
148		compatible = "simple-bus";
149		#address-cells = <2>;
150		#size-cells = <2>;
151		ranges;
152		dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
153
154		clocks {
155			#address-cells = <2>;
156			#size-cells = <2>;
157			ranges;
158
159			pcppll: pcppll@17000100 {
160				compatible = "apm,xgene-pcppll-clock";
161				#clock-cells = <1>;
162				clocks = <&refclk>;
163				clock-names = "pcppll";
164				reg = <0x0 0x17000100 0x0 0x1000>;
165				clock-output-names = "pcppll";
166			};
167
168			socpll: socpll@17000120 {
169				compatible = "apm,xgene-socpll-clock";
170				#clock-cells = <1>;
171				clocks = <&refclk>;
172				clock-names = "socpll";
173				reg = <0x0 0x17000120 0x0 0x1000>;
174				clock-output-names = "socpll";
175			};
176
177			socplldiv2: socplldiv2  {
178				compatible = "fixed-factor-clock";
179				#clock-cells = <0>;
180				clocks = <&socpll 0>;
181				clock-mult = <1>;
182				clock-div = <2>;
183				clock-output-names = "socplldiv2";
184			};
185
186			ahbclk: ahbclk@17000000 {
187				compatible = "apm,xgene-device-clock";
188				#clock-cells = <1>;
189				clocks = <&socplldiv2>;
190				reg = <0x0 0x17000000 0x0 0x2000>;
191				reg-names = "div-reg";
192				divider-offset = <0x164>;
193				divider-width = <0x5>;
194				divider-shift = <0x0>;
195				clock-output-names = "ahbclk";
196			};
197
198			sdioclk: sdioclk@1f2ac000 {
199				compatible = "apm,xgene-device-clock";
200				#clock-cells = <1>;
201				clocks = <&socplldiv2>;
202				reg = <0x0 0x1f2ac000 0x0 0x1000
203					0x0 0x17000000 0x0 0x2000>;
204				reg-names = "csr-reg", "div-reg";
205				csr-offset = <0x0>;
206				csr-mask = <0x2>;
207				enable-offset = <0x8>;
208				enable-mask = <0x2>;
209				divider-offset = <0x178>;
210				divider-width = <0x8>;
211				divider-shift = <0x0>;
212				clock-output-names = "sdioclk";
213			};
214
215			ethclk: ethclk {
216				compatible = "apm,xgene-device-clock";
217				#clock-cells = <1>;
218				clocks = <&socplldiv2>;
219				clock-names = "ethclk";
220				reg = <0x0 0x17000000 0x0 0x1000>;
221				reg-names = "div-reg";
222				divider-offset = <0x238>;
223				divider-width = <0x9>;
224				divider-shift = <0x0>;
225				clock-output-names = "ethclk";
226			};
227
228			menetclk: menetclk {
229				compatible = "apm,xgene-device-clock";
230				#clock-cells = <1>;
231				clocks = <&ethclk 0>;
232				reg = <0x0 0x1702c000 0x0 0x1000>;
233				reg-names = "csr-reg";
234				clock-output-names = "menetclk";
235			};
236
237			sge0clk: sge0clk@1f21c000 {
238				compatible = "apm,xgene-device-clock";
239				#clock-cells = <1>;
240				clocks = <&socplldiv2>;
241				reg = <0x0 0x1f21c000 0x0 0x1000>;
242				reg-names = "csr-reg";
243				csr-mask = <0xa>;
244				enable-mask = <0xf>;
245				clock-output-names = "sge0clk";
246			};
247
248			xge0clk: xge0clk@1f61c000 {
249				compatible = "apm,xgene-device-clock";
250				#clock-cells = <1>;
251				clocks = <&socplldiv2>;
252				reg = <0x0 0x1f61c000 0x0 0x1000>;
253				reg-names = "csr-reg";
254				csr-mask = <0x3>;
255				clock-output-names = "xge0clk";
256			};
257
258			xge1clk: xge1clk@1f62c000 {
259				compatible = "apm,xgene-device-clock";
260				status = "disabled";
261				#clock-cells = <1>;
262				clocks = <&socplldiv2>;
263				reg = <0x0 0x1f62c000 0x0 0x1000>;
264				reg-names = "csr-reg";
265				csr-mask = <0x3>;
266				clock-output-names = "xge1clk";
267			};
268
269			sataphy1clk: sataphy1clk@1f21c000 {
270				compatible = "apm,xgene-device-clock";
271				#clock-cells = <1>;
272				clocks = <&socplldiv2>;
273				reg = <0x0 0x1f21c000 0x0 0x1000>;
274				reg-names = "csr-reg";
275				clock-output-names = "sataphy1clk";
276				status = "disabled";
277				csr-offset = <0x4>;
278				csr-mask = <0x00>;
279				enable-offset = <0x0>;
280				enable-mask = <0x06>;
281			};
282
283			sataphy2clk: sataphy1clk@1f22c000 {
284				compatible = "apm,xgene-device-clock";
285				#clock-cells = <1>;
286				clocks = <&socplldiv2>;
287				reg = <0x0 0x1f22c000 0x0 0x1000>;
288				reg-names = "csr-reg";
289				clock-output-names = "sataphy2clk";
290				status = "okay";
291				csr-offset = <0x4>;
292				csr-mask = <0x3a>;
293				enable-offset = <0x0>;
294				enable-mask = <0x06>;
295			};
296
297			sataphy3clk: sataphy1clk@1f23c000 {
298				compatible = "apm,xgene-device-clock";
299				#clock-cells = <1>;
300				clocks = <&socplldiv2>;
301				reg = <0x0 0x1f23c000 0x0 0x1000>;
302				reg-names = "csr-reg";
303				clock-output-names = "sataphy3clk";
304				status = "okay";
305				csr-offset = <0x4>;
306				csr-mask = <0x3a>;
307				enable-offset = <0x0>;
308				enable-mask = <0x06>;
309			};
310
311			sata01clk: sata01clk@1f21c000 {
312				compatible = "apm,xgene-device-clock";
313				#clock-cells = <1>;
314				clocks = <&socplldiv2>;
315				reg = <0x0 0x1f21c000 0x0 0x1000>;
316				reg-names = "csr-reg";
317				clock-output-names = "sata01clk";
318				csr-offset = <0x4>;
319				csr-mask = <0x05>;
320				enable-offset = <0x0>;
321				enable-mask = <0x39>;
322			};
323
324			sata23clk: sata23clk@1f22c000 {
325				compatible = "apm,xgene-device-clock";
326				#clock-cells = <1>;
327				clocks = <&socplldiv2>;
328				reg = <0x0 0x1f22c000 0x0 0x1000>;
329				reg-names = "csr-reg";
330				clock-output-names = "sata23clk";
331				csr-offset = <0x4>;
332				csr-mask = <0x05>;
333				enable-offset = <0x0>;
334				enable-mask = <0x39>;
335			};
336
337			sata45clk: sata45clk@1f23c000 {
338				compatible = "apm,xgene-device-clock";
339				#clock-cells = <1>;
340				clocks = <&socplldiv2>;
341				reg = <0x0 0x1f23c000 0x0 0x1000>;
342				reg-names = "csr-reg";
343				clock-output-names = "sata45clk";
344				csr-offset = <0x4>;
345				csr-mask = <0x05>;
346				enable-offset = <0x0>;
347				enable-mask = <0x39>;
348			};
349
350			rtcclk: rtcclk@17000000 {
351				compatible = "apm,xgene-device-clock";
352				#clock-cells = <1>;
353				clocks = <&socplldiv2>;
354				reg = <0x0 0x17000000 0x0 0x2000>;
355				reg-names = "csr-reg";
356				csr-offset = <0xc>;
357				csr-mask = <0x2>;
358				enable-offset = <0x10>;
359				enable-mask = <0x2>;
360				clock-output-names = "rtcclk";
361			};
362
363			rngpkaclk: rngpkaclk@17000000 {
364				compatible = "apm,xgene-device-clock";
365				#clock-cells = <1>;
366				clocks = <&socplldiv2>;
367				reg = <0x0 0x17000000 0x0 0x2000>;
368				reg-names = "csr-reg";
369				csr-offset = <0xc>;
370				csr-mask = <0x10>;
371				enable-offset = <0x10>;
372				enable-mask = <0x10>;
373				clock-output-names = "rngpkaclk";
374			};
375
376			pcie0clk: pcie0clk@1f2bc000 {
377				status = "disabled";
378				compatible = "apm,xgene-device-clock";
379				#clock-cells = <1>;
380				clocks = <&socplldiv2>;
381				reg = <0x0 0x1f2bc000 0x0 0x1000>;
382				reg-names = "csr-reg";
383				clock-output-names = "pcie0clk";
384			};
385
386			pcie1clk: pcie1clk@1f2cc000 {
387				status = "disabled";
388				compatible = "apm,xgene-device-clock";
389				#clock-cells = <1>;
390				clocks = <&socplldiv2>;
391				reg = <0x0 0x1f2cc000 0x0 0x1000>;
392				reg-names = "csr-reg";
393				clock-output-names = "pcie1clk";
394			};
395
396			pcie2clk: pcie2clk@1f2dc000 {
397				status = "disabled";
398				compatible = "apm,xgene-device-clock";
399				#clock-cells = <1>;
400				clocks = <&socplldiv2>;
401				reg = <0x0 0x1f2dc000 0x0 0x1000>;
402				reg-names = "csr-reg";
403				clock-output-names = "pcie2clk";
404			};
405
406			pcie3clk: pcie3clk@1f50c000 {
407				status = "disabled";
408				compatible = "apm,xgene-device-clock";
409				#clock-cells = <1>;
410				clocks = <&socplldiv2>;
411				reg = <0x0 0x1f50c000 0x0 0x1000>;
412				reg-names = "csr-reg";
413				clock-output-names = "pcie3clk";
414			};
415
416			pcie4clk: pcie4clk@1f51c000 {
417				status = "disabled";
418				compatible = "apm,xgene-device-clock";
419				#clock-cells = <1>;
420				clocks = <&socplldiv2>;
421				reg = <0x0 0x1f51c000 0x0 0x1000>;
422				reg-names = "csr-reg";
423				clock-output-names = "pcie4clk";
424			};
425
426			dmaclk: dmaclk@1f27c000 {
427				compatible = "apm,xgene-device-clock";
428				#clock-cells = <1>;
429				clocks = <&socplldiv2>;
430				reg = <0x0 0x1f27c000 0x0 0x1000>;
431				reg-names = "csr-reg";
432				clock-output-names = "dmaclk";
433			};
434		};
435
436		msi: msi@79000000 {
437			compatible = "apm,xgene1-msi";
438			msi-controller;
439			reg = <0x00 0x79000000 0x0 0x900000>;
440			interrupts = <  0x0 0x10 0x4
441					0x0 0x11 0x4
442					0x0 0x12 0x4
443					0x0 0x13 0x4
444					0x0 0x14 0x4
445					0x0 0x15 0x4
446					0x0 0x16 0x4
447					0x0 0x17 0x4
448					0x0 0x18 0x4
449					0x0 0x19 0x4
450					0x0 0x1a 0x4
451					0x0 0x1b 0x4
452					0x0 0x1c 0x4
453					0x0 0x1d 0x4
454					0x0 0x1e 0x4
455					0x0 0x1f 0x4>;
456		};
457
458		scu: system-clk-controller@17000000 {
459			compatible = "apm,xgene-scu","syscon";
460			reg = <0x0 0x17000000 0x0 0x400>;
461		};
462
463		reboot: reboot@17000014 {
464			compatible = "syscon-reboot";
465			regmap = <&scu>;
466			offset = <0x14>;
467			mask = <0x1>;
468		};
469
470		csw: csw@7e200000 {
471			compatible = "apm,xgene-csw", "syscon";
472			reg = <0x0 0x7e200000 0x0 0x1000>;
473		};
474
475		mcba: mcba@7e700000 {
476			compatible = "apm,xgene-mcb", "syscon";
477			reg = <0x0 0x7e700000 0x0 0x1000>;
478		};
479
480		mcbb: mcbb@7e720000 {
481			compatible = "apm,xgene-mcb", "syscon";
482			reg = <0x0 0x7e720000 0x0 0x1000>;
483		};
484
485		efuse: efuse@1054a000 {
486			compatible = "apm,xgene-efuse", "syscon";
487			reg = <0x0 0x1054a000 0x0 0x20>;
488		};
489
490		rb: rb@7e000000 {
491			compatible = "apm,xgene-rb", "syscon";
492			reg = <0x0 0x7e000000 0x0 0x10>;
493		};
494
495		edac@78800000 {
496			compatible = "apm,xgene-edac";
497			#address-cells = <2>;
498			#size-cells = <2>;
499			ranges;
500			regmap-csw = <&csw>;
501			regmap-mcba = <&mcba>;
502			regmap-mcbb = <&mcbb>;
503			regmap-efuse = <&efuse>;
504			regmap-rb = <&rb>;
505			reg = <0x0 0x78800000 0x0 0x100>;
506			interrupts = <0x0 0x20 0x4>,
507				     <0x0 0x21 0x4>,
508				     <0x0 0x27 0x4>;
509
510			edacmc@7e800000 {
511				compatible = "apm,xgene-edac-mc";
512				reg = <0x0 0x7e800000 0x0 0x1000>;
513				memory-controller = <0>;
514			};
515
516			edacmc@7e840000 {
517				compatible = "apm,xgene-edac-mc";
518				reg = <0x0 0x7e840000 0x0 0x1000>;
519				memory-controller = <1>;
520			};
521
522			edacmc@7e880000 {
523				compatible = "apm,xgene-edac-mc";
524				reg = <0x0 0x7e880000 0x0 0x1000>;
525				memory-controller = <2>;
526			};
527
528			edacmc@7e8c0000 {
529				compatible = "apm,xgene-edac-mc";
530				reg = <0x0 0x7e8c0000 0x0 0x1000>;
531				memory-controller = <3>;
532			};
533
534			edacpmd@7c000000 {
535				compatible = "apm,xgene-edac-pmd";
536				reg = <0x0 0x7c000000 0x0 0x200000>;
537				pmd-controller = <0>;
538			};
539
540			edacpmd@7c200000 {
541				compatible = "apm,xgene-edac-pmd";
542				reg = <0x0 0x7c200000 0x0 0x200000>;
543				pmd-controller = <1>;
544			};
545
546			edacpmd@7c400000 {
547				compatible = "apm,xgene-edac-pmd";
548				reg = <0x0 0x7c400000 0x0 0x200000>;
549				pmd-controller = <2>;
550			};
551
552			edacpmd@7c600000 {
553				compatible = "apm,xgene-edac-pmd";
554				reg = <0x0 0x7c600000 0x0 0x200000>;
555				pmd-controller = <3>;
556			};
557
558			edacl3@7e600000 {
559				compatible = "apm,xgene-edac-l3";
560				reg = <0x0 0x7e600000 0x0 0x1000>;
561			};
562
563			edacsoc@7e930000 {
564				compatible = "apm,xgene-edac-soc-v1";
565				reg = <0x0 0x7e930000 0x0 0x1000>;
566			};
567		};
568
569		pmu: pmu@78810000 {
570			compatible = "apm,xgene-pmu-v2";
571			#address-cells = <2>;
572			#size-cells = <2>;
573			ranges;
574			regmap-csw = <&csw>;
575			regmap-mcba = <&mcba>;
576			regmap-mcbb = <&mcbb>;
577			reg = <0x0 0x78810000 0x0 0x1000>;
578			interrupts = <0x0 0x22 0x4>;
579
580			pmul3c@7e610000 {
581				compatible = "apm,xgene-pmu-l3c";
582				reg = <0x0 0x7e610000 0x0 0x1000>;
583			};
584
585			pmuiob@7e940000 {
586				compatible = "apm,xgene-pmu-iob";
587				reg = <0x0 0x7e940000 0x0 0x1000>;
588			};
589
590			pmucmcb@7e710000 {
591				compatible = "apm,xgene-pmu-mcb";
592				reg = <0x0 0x7e710000 0x0 0x1000>;
593				enable-bit-index = <0>;
594			};
595
596			pmucmcb@7e730000 {
597				compatible = "apm,xgene-pmu-mcb";
598				reg = <0x0 0x7e730000 0x0 0x1000>;
599				enable-bit-index = <1>;
600			};
601
602			pmucmc@7e810000 {
603				compatible = "apm,xgene-pmu-mc";
604				reg = <0x0 0x7e810000 0x0 0x1000>;
605				enable-bit-index = <0>;
606			};
607
608			pmucmc@7e850000 {
609				compatible = "apm,xgene-pmu-mc";
610				reg = <0x0 0x7e850000 0x0 0x1000>;
611				enable-bit-index = <1>;
612			};
613
614			pmucmc@7e890000 {
615				compatible = "apm,xgene-pmu-mc";
616				reg = <0x0 0x7e890000 0x0 0x1000>;
617				enable-bit-index = <2>;
618			};
619
620			pmucmc@7e8d0000 {
621				compatible = "apm,xgene-pmu-mc";
622				reg = <0x0 0x7e8d0000 0x0 0x1000>;
623				enable-bit-index = <3>;
624			};
625		};
626
627		pcie0: pcie@1f2b0000 {
628			status = "disabled";
629			device_type = "pci";
630			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
631			#interrupt-cells = <1>;
632			#size-cells = <2>;
633			#address-cells = <3>;
634			reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
635				0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
636			reg-names = "csr", "cfg";
637			ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000   /* io */
638				  0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000   /* mem */
639				  0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
640			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
641				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
642			bus-range = <0x00 0xff>;
643			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
644			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
645					 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
646					 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
647					 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
648			dma-coherent;
649			clocks = <&pcie0clk 0>;
650			msi-parent = <&msi>;
651		};
652
653		pcie1: pcie@1f2c0000 {
654			status = "disabled";
655			device_type = "pci";
656			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
657			#interrupt-cells = <1>;
658			#size-cells = <2>;
659			#address-cells = <3>;
660			reg = < 0x00 0x1f2c0000 0x0 0x00010000   /* Controller registers */
661				0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */
662			reg-names = "csr", "cfg";
663			ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000   /* io  */
664				  0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000   /* mem */
665				  0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
666			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
667				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
668			bus-range = <0x00 0xff>;
669			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
670			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
671					 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
672					 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
673					 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
674			dma-coherent;
675			clocks = <&pcie1clk 0>;
676			msi-parent = <&msi>;
677		};
678
679		pcie2: pcie@1f2d0000 {
680			status = "disabled";
681			device_type = "pci";
682			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
683			#interrupt-cells = <1>;
684			#size-cells = <2>;
685			#address-cells = <3>;
686			reg =  < 0x00 0x1f2d0000 0x0 0x00010000   /* Controller registers */
687				 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */
688			reg-names = "csr", "cfg";
689			ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000   /* io  */
690				  0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000   /* mem */
691				  0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
692			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
693				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
694			bus-range = <0x00 0xff>;
695			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
696			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
697					 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
698					 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
699					 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
700			dma-coherent;
701			clocks = <&pcie2clk 0>;
702			msi-parent = <&msi>;
703		};
704
705		pcie3: pcie@1f500000 {
706			status = "disabled";
707			device_type = "pci";
708			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
709			#interrupt-cells = <1>;
710			#size-cells = <2>;
711			#address-cells = <3>;
712			reg = < 0x00 0x1f500000 0x0 0x00010000   /* Controller registers */
713				0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */
714			reg-names = "csr", "cfg";
715			ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000   /* io  */
716				  0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000   /* mem */
717				  0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
718			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
719				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
720			bus-range = <0x00 0xff>;
721			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
722			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
723					 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
724					 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
725					 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
726			dma-coherent;
727			clocks = <&pcie3clk 0>;
728			msi-parent = <&msi>;
729		};
730
731		pcie4: pcie@1f510000 {
732			status = "disabled";
733			device_type = "pci";
734			compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
735			#interrupt-cells = <1>;
736			#size-cells = <2>;
737			#address-cells = <3>;
738			reg = < 0x00 0x1f510000 0x0 0x00010000   /* Controller registers */
739				0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */
740			reg-names = "csr", "cfg";
741			ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000   /* io  */
742				  0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000   /* mem */
743				  0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
744			dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
745				      0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
746			bus-range = <0x00 0xff>;
747			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
748			interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
749					 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
750					 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
751					 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
752			dma-coherent;
753			clocks = <&pcie4clk 0>;
754			msi-parent = <&msi>;
755		};
756
757		mailbox: mailbox@10540000 {
758			compatible = "apm,xgene-slimpro-mbox";
759			reg = <0x0 0x10540000 0x0 0xa000>;
760			#mbox-cells = <1>;
761			interrupts =    <0x0 0x0 0x4>,
762					<0x0 0x1 0x4>,
763					<0x0 0x2 0x4>,
764					<0x0 0x3 0x4>,
765					<0x0 0x4 0x4>,
766					<0x0 0x5 0x4>,
767					<0x0 0x6 0x4>,
768					<0x0 0x7 0x4>;
769		};
770
771		serial0: serial@1c020000 {
772			status = "disabled";
773			compatible = "ns16550a";
774			reg = <0 0x1c020000 0x0 0x1000>;
775			reg-shift = <2>;
776			clock-frequency = <10000000>; /* Updated by bootloader */
777			interrupt-parent = <&gic>;
778			interrupts = <0x0 0x4c 0x4>;
779		};
780
781		serial1: serial@1c021000 {
782			status = "disabled";
783			compatible = "ns16550a";
784			reg = <0 0x1c021000 0x0 0x1000>;
785			reg-shift = <2>;
786			clock-frequency = <10000000>; /* Updated by bootloader */
787			interrupt-parent = <&gic>;
788			interrupts = <0x0 0x4d 0x4>;
789		};
790
791		serial2: serial@1c022000 {
792			status = "disabled";
793			compatible = "ns16550a";
794			reg = <0 0x1c022000 0x0 0x1000>;
795			reg-shift = <2>;
796			clock-frequency = <10000000>; /* Updated by bootloader */
797			interrupt-parent = <&gic>;
798			interrupts = <0x0 0x4e 0x4>;
799		};
800
801		serial3: serial@1c023000 {
802			status = "disabled";
803			compatible = "ns16550a";
804			reg = <0 0x1c023000 0x0 0x1000>;
805			reg-shift = <2>;
806			clock-frequency = <10000000>; /* Updated by bootloader */
807			interrupt-parent = <&gic>;
808			interrupts = <0x0 0x4f 0x4>;
809		};
810
811		mmc0: mmc@1c000000 {
812			compatible = "arasan,sdhci-4.9a";
813			reg = <0x0 0x1c000000 0x0 0x100>;
814			interrupts = <0x0 0x49 0x4>;
815			dma-coherent;
816			no-1-8-v;
817			clock-names = "clk_xin", "clk_ahb";
818			clocks = <&sdioclk 0>, <&ahbclk 0>;
819		};
820
821		gfcgpio: gpio0@1701c000 {
822			compatible = "apm,xgene-gpio";
823			reg = <0x0 0x1701c000 0x0 0x40>;
824			gpio-controller;
825			#gpio-cells = <2>;
826		};
827
828		dwgpio: gpio@1c024000 {
829			compatible = "snps,dw-apb-gpio";
830			reg = <0x0 0x1c024000 0x0 0x1000>;
831			#address-cells = <1>;
832			#size-cells = <0>;
833
834			porta: gpio-controller@0 {
835				compatible = "snps,dw-apb-gpio-port";
836				gpio-controller;
837				#gpio-cells = <2>;
838				snps,nr-gpios = <32>;
839				reg = <0>;
840			};
841		};
842
843		i2c0: i2c@10512000 {
844			status = "disabled";
845			#address-cells = <1>;
846			#size-cells = <0>;
847			compatible = "snps,designware-i2c";
848			reg = <0x0 0x10512000 0x0 0x1000>;
849			interrupts = <0 0x44 0x4>;
850			clocks = <&ahbclk 0>;
851		};
852
853		phy1: phy@1f21a000 {
854			compatible = "apm,xgene-phy";
855			reg = <0x0 0x1f21a000 0x0 0x100>;
856			#phy-cells = <1>;
857			clocks = <&sataphy1clk 0>;
858			status = "disabled";
859			apm,tx-boost-gain = <30 30 30 30 30 30>;
860			apm,tx-eye-tuning = <2 10 10 2 10 10>;
861		};
862
863		phy2: phy@1f22a000 {
864			compatible = "apm,xgene-phy";
865			reg = <0x0 0x1f22a000 0x0 0x100>;
866			#phy-cells = <1>;
867			clocks = <&sataphy2clk 0>;
868			status = "okay";
869			apm,tx-boost-gain = <30 30 30 30 30 30>;
870			apm,tx-eye-tuning = <1 10 10 2 10 10>;
871		};
872
873		phy3: phy@1f23a000 {
874			compatible = "apm,xgene-phy";
875			reg = <0x0 0x1f23a000 0x0 0x100>;
876			#phy-cells = <1>;
877			clocks = <&sataphy3clk 0>;
878			status = "okay";
879			apm,tx-boost-gain = <31 31 31 31 31 31>;
880			apm,tx-eye-tuning = <2 10 10 2 10 10>;
881		};
882
883		sata1: sata@1a000000 {
884			compatible = "apm,xgene-ahci";
885			reg = <0x0 0x1a000000 0x0 0x1000>,
886			      <0x0 0x1f210000 0x0 0x1000>,
887			      <0x0 0x1f21d000 0x0 0x1000>,
888			      <0x0 0x1f21e000 0x0 0x1000>,
889			      <0x0 0x1f217000 0x0 0x1000>;
890			interrupts = <0x0 0x86 0x4>;
891			dma-coherent;
892			status = "disabled";
893			clocks = <&sata01clk 0>;
894			phys = <&phy1 0>;
895			phy-names = "sata-phy";
896		};
897
898		sata2: sata@1a400000 {
899			compatible = "apm,xgene-ahci";
900			reg = <0x0 0x1a400000 0x0 0x1000>,
901			      <0x0 0x1f220000 0x0 0x1000>,
902			      <0x0 0x1f22d000 0x0 0x1000>,
903			      <0x0 0x1f22e000 0x0 0x1000>,
904			      <0x0 0x1f227000 0x0 0x1000>;
905			interrupts = <0x0 0x87 0x4>;
906			dma-coherent;
907			status = "okay";
908			clocks = <&sata23clk 0>;
909			phys = <&phy2 0>;
910			phy-names = "sata-phy";
911		};
912
913		sata3: sata@1a800000 {
914			compatible = "apm,xgene-ahci";
915			reg = <0x0 0x1a800000 0x0 0x1000>,
916			      <0x0 0x1f230000 0x0 0x1000>,
917			      <0x0 0x1f23d000 0x0 0x1000>,
918			      <0x0 0x1f23e000 0x0 0x1000>;
919			interrupts = <0x0 0x88 0x4>;
920			dma-coherent;
921			status = "okay";
922			clocks = <&sata45clk 0>;
923			phys = <&phy3 0>;
924			phy-names = "sata-phy";
925		};
926
927		/* Node-name might need to be coded as dwusb for backward compatibility */
928		usb0: usb@19000000 {
929			status = "disabled";
930			compatible = "snps,dwc3";
931			reg = <0x0 0x19000000 0x0 0x100000>;
932			interrupts = <0x0 0x89 0x4>;
933			dma-coherent;
934			dr_mode = "host";
935		};
936
937		usb1: usb@19800000 {
938			status = "disabled";
939			compatible = "snps,dwc3";
940			reg = <0x0 0x19800000 0x0 0x100000>;
941			interrupts = <0x0 0x8a 0x4>;
942			dma-coherent;
943			dr_mode = "host";
944		};
945
946		sbgpio: gpio@17001000 {
947			compatible = "apm,xgene-gpio-sb";
948			reg = <0x0 0x17001000 0x0 0x400>;
949			#gpio-cells = <2>;
950			gpio-controller;
951			interrupts = 	<0x0 0x28 0x1>,
952					<0x0 0x29 0x1>,
953					<0x0 0x2a 0x1>,
954					<0x0 0x2b 0x1>,
955					<0x0 0x2c 0x1>,
956					<0x0 0x2d 0x1>;
957			interrupt-parent = <&gic>;
958			#interrupt-cells = <2>;
959			interrupt-controller;
960		};
961
962		rtc: rtc@10510000 {
963			compatible = "apm,xgene-rtc";
964			reg = <0x0 0x10510000 0x0 0x400>;
965			interrupts = <0x0 0x46 0x4>;
966			#clock-cells = <1>;
967			clocks = <&rtcclk 0>;
968		};
969
970		mdio: mdio@17020000 {
971			compatible = "apm,xgene-mdio-rgmii";
972			#address-cells = <1>;
973			#size-cells = <0>;
974			reg = <0x0 0x17020000 0x0 0xd100>;
975			clocks = <&menetclk 0>;
976		};
977
978		menet: ethernet@17020000 {
979			compatible = "apm,xgene-enet";
980			status = "disabled";
981			reg = <0x0 0x17020000 0x0 0xd100>,
982			      <0x0 0x17030000 0x0 0xc300>,
983			      <0x0 0x10000000 0x0 0x200>;
984			reg-names = "enet_csr", "ring_csr", "ring_cmd";
985			interrupts = <0x0 0x3c 0x4>;
986			dma-coherent;
987			clocks = <&menetclk 0>;
988			/* mac address will be overwritten by the bootloader */
989			local-mac-address = [00 00 00 00 00 00];
990			phy-connection-type = "rgmii";
991			phy-handle = <&menetphy>,<&menet0phy>;
992			mdio {
993				compatible = "apm,xgene-mdio";
994				#address-cells = <1>;
995				#size-cells = <0>;
996				menetphy: ethernet-phy@3 {
997					compatible = "ethernet-phy-id001c.c915";
998					reg = <0x3>;
999				};
1000
1001			};
1002		};
1003
1004		sgenet0: ethernet@1f210000 {
1005			compatible = "apm,xgene1-sgenet";
1006			status = "disabled";
1007			reg = <0x0 0x1f210000 0x0 0xd100>,
1008			      <0x0 0x1f200000 0x0 0xc300>,
1009			      <0x0 0x1b000000 0x0 0x200>;
1010			reg-names = "enet_csr", "ring_csr", "ring_cmd";
1011			interrupts = <0x0 0xa0 0x4>,
1012				     <0x0 0xa1 0x4>;
1013			dma-coherent;
1014			clocks = <&sge0clk 0>;
1015			local-mac-address = [00 00 00 00 00 00];
1016			phy-connection-type = "sgmii";
1017			phy-handle = <&sgenet0phy>;
1018		};
1019
1020		sgenet1: ethernet@1f210030 {
1021			compatible = "apm,xgene1-sgenet";
1022			status = "disabled";
1023			reg = <0x0 0x1f210030 0x0 0xd100>,
1024			      <0x0 0x1f200000 0x0 0xc300>,
1025			      <0x0 0x1b000000 0x0 0x8000>;
1026			reg-names = "enet_csr", "ring_csr", "ring_cmd";
1027			interrupts = <0x0 0xac 0x4>,
1028				     <0x0 0xad 0x4>;
1029			port-id = <1>;
1030			dma-coherent;
1031			local-mac-address = [00 00 00 00 00 00];
1032			phy-connection-type = "sgmii";
1033			phy-handle = <&sgenet1phy>;
1034		};
1035
1036		xgenet: ethernet@1f610000 {
1037			compatible = "apm,xgene1-xgenet";
1038			status = "disabled";
1039			reg = <0x0 0x1f610000 0x0 0xd100>,
1040			      <0x0 0x1f600000 0x0 0xc300>,
1041			      <0x0 0x18000000 0x0 0x200>;
1042			reg-names = "enet_csr", "ring_csr", "ring_cmd";
1043			interrupts = <0x0 0x60 0x4>,
1044				     <0x0 0x61 0x4>,
1045				     <0x0 0x62 0x4>,
1046				     <0x0 0x63 0x4>,
1047				     <0x0 0x64 0x4>,
1048				     <0x0 0x65 0x4>,
1049				     <0x0 0x66 0x4>,
1050				     <0x0 0x67 0x4>;
1051			channel = <0>;
1052			dma-coherent;
1053			clocks = <&xge0clk 0>;
1054			/* mac address will be overwritten by the bootloader */
1055			local-mac-address = [00 00 00 00 00 00];
1056			phy-connection-type = "xgmii";
1057		};
1058
1059		xgenet1: ethernet@1f620000 {
1060			compatible = "apm,xgene1-xgenet";
1061			status = "disabled";
1062			reg = <0x0 0x1f620000 0x0 0xd100>,
1063			      <0x0 0x1f600000 0x0 0xc300>,
1064			      <0x0 0x18000000 0x0 0x8000>;
1065			reg-names = "enet_csr", "ring_csr", "ring_cmd";
1066			interrupts = <0x0 0x6c 0x4>,
1067				     <0x0 0x6d 0x4>;
1068			port-id = <1>;
1069			dma-coherent;
1070			clocks = <&xge1clk 0>;
1071			/* mac address will be overwritten by the bootloader */
1072			local-mac-address = [00 00 00 00 00 00];
1073			phy-connection-type = "xgmii";
1074		};
1075
1076		rng: rng@10520000 {
1077			compatible = "apm,xgene-rng";
1078			reg = <0x0 0x10520000 0x0 0x100>;
1079			interrupts = <0x0 0x41 0x4>;
1080			clocks = <&rngpkaclk 0>;
1081		};
1082
1083		dma: dma@1f270000 {
1084			compatible = "apm,xgene-storm-dma";
1085			device_type = "dma";
1086			reg = <0x0 0x1f270000 0x0 0x10000>,
1087			      <0x0 0x1f200000 0x0 0x10000>,
1088			      <0x0 0x1b000000 0x0 0x400000>,
1089			      <0x0 0x1054a000 0x0 0x100>;
1090			interrupts = <0x0 0x82 0x4>,
1091				     <0x0 0xb8 0x4>,
1092				     <0x0 0xb9 0x4>,
1093				     <0x0 0xba 0x4>,
1094				     <0x0 0xbb 0x4>;
1095			dma-coherent;
1096			clocks = <&dmaclk 0>;
1097		};
1098	};
1099};
1100