1/* 2 * dts file for AppliedMicro (APM) X-Gene Storm SOC 3 * 4 * Copyright (C) 2013, Applied Micro Circuits Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 */ 11 12/ { 13 compatible = "apm,xgene-storm"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu@000 { 23 device_type = "cpu"; 24 compatible = "apm,potenza", "arm,armv8"; 25 reg = <0x0 0x000>; 26 enable-method = "spin-table"; 27 cpu-release-addr = <0x1 0x0000fff8>; 28 }; 29 cpu@001 { 30 device_type = "cpu"; 31 compatible = "apm,potenza", "arm,armv8"; 32 reg = <0x0 0x001>; 33 enable-method = "spin-table"; 34 cpu-release-addr = <0x1 0x0000fff8>; 35 }; 36 cpu@100 { 37 device_type = "cpu"; 38 compatible = "apm,potenza", "arm,armv8"; 39 reg = <0x0 0x100>; 40 enable-method = "spin-table"; 41 cpu-release-addr = <0x1 0x0000fff8>; 42 }; 43 cpu@101 { 44 device_type = "cpu"; 45 compatible = "apm,potenza", "arm,armv8"; 46 reg = <0x0 0x101>; 47 enable-method = "spin-table"; 48 cpu-release-addr = <0x1 0x0000fff8>; 49 }; 50 cpu@200 { 51 device_type = "cpu"; 52 compatible = "apm,potenza", "arm,armv8"; 53 reg = <0x0 0x200>; 54 enable-method = "spin-table"; 55 cpu-release-addr = <0x1 0x0000fff8>; 56 }; 57 cpu@201 { 58 device_type = "cpu"; 59 compatible = "apm,potenza", "arm,armv8"; 60 reg = <0x0 0x201>; 61 enable-method = "spin-table"; 62 cpu-release-addr = <0x1 0x0000fff8>; 63 }; 64 cpu@300 { 65 device_type = "cpu"; 66 compatible = "apm,potenza", "arm,armv8"; 67 reg = <0x0 0x300>; 68 enable-method = "spin-table"; 69 cpu-release-addr = <0x1 0x0000fff8>; 70 }; 71 cpu@301 { 72 device_type = "cpu"; 73 compatible = "apm,potenza", "arm,armv8"; 74 reg = <0x0 0x301>; 75 enable-method = "spin-table"; 76 cpu-release-addr = <0x1 0x0000fff8>; 77 }; 78 }; 79 80 gic: interrupt-controller@78010000 { 81 compatible = "arm,cortex-a15-gic"; 82 #interrupt-cells = <3>; 83 interrupt-controller; 84 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ 85 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ 86 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ 87 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ 88 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ 89 }; 90 91 timer { 92 compatible = "arm,armv8-timer"; 93 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ 94 <1 13 0xff01>, /* Non-secure Phys IRQ */ 95 <1 14 0xff01>, /* Virt IRQ */ 96 <1 15 0xff01>; /* Hyp IRQ */ 97 clock-frequency = <50000000>; 98 }; 99 100 soc { 101 compatible = "simple-bus"; 102 #address-cells = <2>; 103 #size-cells = <2>; 104 ranges; 105 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; 106 107 clocks { 108 #address-cells = <2>; 109 #size-cells = <2>; 110 ranges; 111 refclk: refclk { 112 compatible = "fixed-clock"; 113 #clock-cells = <1>; 114 clock-frequency = <100000000>; 115 clock-output-names = "refclk"; 116 }; 117 118 pcppll: pcppll@17000100 { 119 compatible = "apm,xgene-pcppll-clock"; 120 #clock-cells = <1>; 121 clocks = <&refclk 0>; 122 clock-names = "pcppll"; 123 reg = <0x0 0x17000100 0x0 0x1000>; 124 clock-output-names = "pcppll"; 125 type = <0>; 126 }; 127 128 socpll: socpll@17000120 { 129 compatible = "apm,xgene-socpll-clock"; 130 #clock-cells = <1>; 131 clocks = <&refclk 0>; 132 clock-names = "socpll"; 133 reg = <0x0 0x17000120 0x0 0x1000>; 134 clock-output-names = "socpll"; 135 type = <1>; 136 }; 137 138 socplldiv2: socplldiv2 { 139 compatible = "fixed-factor-clock"; 140 #clock-cells = <1>; 141 clocks = <&socpll 0>; 142 clock-names = "socplldiv2"; 143 clock-mult = <1>; 144 clock-div = <2>; 145 clock-output-names = "socplldiv2"; 146 }; 147 148 qmlclk: qmlclk { 149 compatible = "apm,xgene-device-clock"; 150 #clock-cells = <1>; 151 clocks = <&socplldiv2 0>; 152 clock-names = "qmlclk"; 153 reg = <0x0 0x1703C000 0x0 0x1000>; 154 reg-names = "csr-reg"; 155 clock-output-names = "qmlclk"; 156 }; 157 158 ethclk: ethclk { 159 compatible = "apm,xgene-device-clock"; 160 #clock-cells = <1>; 161 clocks = <&socplldiv2 0>; 162 clock-names = "ethclk"; 163 reg = <0x0 0x17000000 0x0 0x1000>; 164 reg-names = "div-reg"; 165 divider-offset = <0x238>; 166 divider-width = <0x9>; 167 divider-shift = <0x0>; 168 clock-output-names = "ethclk"; 169 }; 170 171 menetclk: menetclk { 172 compatible = "apm,xgene-device-clock"; 173 #clock-cells = <1>; 174 clocks = <ðclk 0>; 175 reg = <0x0 0x1702C000 0x0 0x1000>; 176 reg-names = "csr-reg"; 177 clock-output-names = "menetclk"; 178 }; 179 180 sge0clk: sge0clk@1f21c000 { 181 compatible = "apm,xgene-device-clock"; 182 #clock-cells = <1>; 183 clocks = <&socplldiv2 0>; 184 reg = <0x0 0x1f21c000 0x0 0x1000>; 185 reg-names = "csr-reg"; 186 csr-mask = <0x3>; 187 clock-output-names = "sge0clk"; 188 }; 189 190 sge1clk: sge1clk@1f21c000 { 191 compatible = "apm,xgene-device-clock"; 192 #clock-cells = <1>; 193 clocks = <&socplldiv2 0>; 194 reg = <0x0 0x1f21c000 0x0 0x1000>; 195 reg-names = "csr-reg"; 196 csr-mask = <0xc>; 197 clock-output-names = "sge1clk"; 198 }; 199 200 xge0clk: xge0clk@1f61c000 { 201 compatible = "apm,xgene-device-clock"; 202 #clock-cells = <1>; 203 clocks = <&socplldiv2 0>; 204 reg = <0x0 0x1f61c000 0x0 0x1000>; 205 reg-names = "csr-reg"; 206 csr-mask = <0x3>; 207 clock-output-names = "xge0clk"; 208 }; 209 210 sataphy1clk: sataphy1clk@1f21c000 { 211 compatible = "apm,xgene-device-clock"; 212 #clock-cells = <1>; 213 clocks = <&socplldiv2 0>; 214 reg = <0x0 0x1f21c000 0x0 0x1000>; 215 reg-names = "csr-reg"; 216 clock-output-names = "sataphy1clk"; 217 status = "disabled"; 218 csr-offset = <0x4>; 219 csr-mask = <0x00>; 220 enable-offset = <0x0>; 221 enable-mask = <0x06>; 222 }; 223 224 sataphy2clk: sataphy1clk@1f22c000 { 225 compatible = "apm,xgene-device-clock"; 226 #clock-cells = <1>; 227 clocks = <&socplldiv2 0>; 228 reg = <0x0 0x1f22c000 0x0 0x1000>; 229 reg-names = "csr-reg"; 230 clock-output-names = "sataphy2clk"; 231 status = "ok"; 232 csr-offset = <0x4>; 233 csr-mask = <0x3a>; 234 enable-offset = <0x0>; 235 enable-mask = <0x06>; 236 }; 237 238 sataphy3clk: sataphy1clk@1f23c000 { 239 compatible = "apm,xgene-device-clock"; 240 #clock-cells = <1>; 241 clocks = <&socplldiv2 0>; 242 reg = <0x0 0x1f23c000 0x0 0x1000>; 243 reg-names = "csr-reg"; 244 clock-output-names = "sataphy3clk"; 245 status = "ok"; 246 csr-offset = <0x4>; 247 csr-mask = <0x3a>; 248 enable-offset = <0x0>; 249 enable-mask = <0x06>; 250 }; 251 252 sata01clk: sata01clk@1f21c000 { 253 compatible = "apm,xgene-device-clock"; 254 #clock-cells = <1>; 255 clocks = <&socplldiv2 0>; 256 reg = <0x0 0x1f21c000 0x0 0x1000>; 257 reg-names = "csr-reg"; 258 clock-output-names = "sata01clk"; 259 csr-offset = <0x4>; 260 csr-mask = <0x05>; 261 enable-offset = <0x0>; 262 enable-mask = <0x39>; 263 }; 264 265 sata23clk: sata23clk@1f22c000 { 266 compatible = "apm,xgene-device-clock"; 267 #clock-cells = <1>; 268 clocks = <&socplldiv2 0>; 269 reg = <0x0 0x1f22c000 0x0 0x1000>; 270 reg-names = "csr-reg"; 271 clock-output-names = "sata23clk"; 272 csr-offset = <0x4>; 273 csr-mask = <0x05>; 274 enable-offset = <0x0>; 275 enable-mask = <0x39>; 276 }; 277 278 sata45clk: sata45clk@1f23c000 { 279 compatible = "apm,xgene-device-clock"; 280 #clock-cells = <1>; 281 clocks = <&socplldiv2 0>; 282 reg = <0x0 0x1f23c000 0x0 0x1000>; 283 reg-names = "csr-reg"; 284 clock-output-names = "sata45clk"; 285 csr-offset = <0x4>; 286 csr-mask = <0x05>; 287 enable-offset = <0x0>; 288 enable-mask = <0x39>; 289 }; 290 291 rtcclk: rtcclk@17000000 { 292 compatible = "apm,xgene-device-clock"; 293 #clock-cells = <1>; 294 clocks = <&socplldiv2 0>; 295 reg = <0x0 0x17000000 0x0 0x2000>; 296 reg-names = "csr-reg"; 297 csr-offset = <0xc>; 298 csr-mask = <0x2>; 299 enable-offset = <0x10>; 300 enable-mask = <0x2>; 301 clock-output-names = "rtcclk"; 302 }; 303 304 rngpkaclk: rngpkaclk@17000000 { 305 compatible = "apm,xgene-device-clock"; 306 #clock-cells = <1>; 307 clocks = <&socplldiv2 0>; 308 reg = <0x0 0x17000000 0x0 0x2000>; 309 reg-names = "csr-reg"; 310 csr-offset = <0xc>; 311 csr-mask = <0x10>; 312 enable-offset = <0x10>; 313 enable-mask = <0x10>; 314 clock-output-names = "rngpkaclk"; 315 }; 316 317 pcie0clk: pcie0clk@1f2bc000 { 318 status = "disabled"; 319 compatible = "apm,xgene-device-clock"; 320 #clock-cells = <1>; 321 clocks = <&socplldiv2 0>; 322 reg = <0x0 0x1f2bc000 0x0 0x1000>; 323 reg-names = "csr-reg"; 324 clock-output-names = "pcie0clk"; 325 }; 326 327 pcie1clk: pcie1clk@1f2cc000 { 328 status = "disabled"; 329 compatible = "apm,xgene-device-clock"; 330 #clock-cells = <1>; 331 clocks = <&socplldiv2 0>; 332 reg = <0x0 0x1f2cc000 0x0 0x1000>; 333 reg-names = "csr-reg"; 334 clock-output-names = "pcie1clk"; 335 }; 336 337 pcie2clk: pcie2clk@1f2dc000 { 338 status = "disabled"; 339 compatible = "apm,xgene-device-clock"; 340 #clock-cells = <1>; 341 clocks = <&socplldiv2 0>; 342 reg = <0x0 0x1f2dc000 0x0 0x1000>; 343 reg-names = "csr-reg"; 344 clock-output-names = "pcie2clk"; 345 }; 346 347 pcie3clk: pcie3clk@1f50c000 { 348 status = "disabled"; 349 compatible = "apm,xgene-device-clock"; 350 #clock-cells = <1>; 351 clocks = <&socplldiv2 0>; 352 reg = <0x0 0x1f50c000 0x0 0x1000>; 353 reg-names = "csr-reg"; 354 clock-output-names = "pcie3clk"; 355 }; 356 357 pcie4clk: pcie4clk@1f51c000 { 358 status = "disabled"; 359 compatible = "apm,xgene-device-clock"; 360 #clock-cells = <1>; 361 clocks = <&socplldiv2 0>; 362 reg = <0x0 0x1f51c000 0x0 0x1000>; 363 reg-names = "csr-reg"; 364 clock-output-names = "pcie4clk"; 365 }; 366 367 dmaclk: dmaclk@1f27c000 { 368 compatible = "apm,xgene-device-clock"; 369 #clock-cells = <1>; 370 clocks = <&socplldiv2 0>; 371 reg = <0x0 0x1f27c000 0x0 0x1000>; 372 reg-names = "csr-reg"; 373 clock-output-names = "dmaclk"; 374 }; 375 }; 376 377 msi: msi@79000000 { 378 compatible = "apm,xgene1-msi"; 379 msi-controller; 380 reg = <0x00 0x79000000 0x0 0x900000>; 381 interrupts = < 0x0 0x10 0x4 382 0x0 0x11 0x4 383 0x0 0x12 0x4 384 0x0 0x13 0x4 385 0x0 0x14 0x4 386 0x0 0x15 0x4 387 0x0 0x16 0x4 388 0x0 0x17 0x4 389 0x0 0x18 0x4 390 0x0 0x19 0x4 391 0x0 0x1a 0x4 392 0x0 0x1b 0x4 393 0x0 0x1c 0x4 394 0x0 0x1d 0x4 395 0x0 0x1e 0x4 396 0x0 0x1f 0x4>; 397 }; 398 399 csw: csw@7e200000 { 400 compatible = "apm,xgene-csw", "syscon"; 401 reg = <0x0 0x7e200000 0x0 0x1000>; 402 }; 403 404 mcba: mcba@7e700000 { 405 compatible = "apm,xgene-mcb", "syscon"; 406 reg = <0x0 0x7e700000 0x0 0x1000>; 407 }; 408 409 mcbb: mcbb@7e720000 { 410 compatible = "apm,xgene-mcb", "syscon"; 411 reg = <0x0 0x7e720000 0x0 0x1000>; 412 }; 413 414 efuse: efuse@1054a000 { 415 compatible = "apm,xgene-efuse", "syscon"; 416 reg = <0x0 0x1054a000 0x0 0x20>; 417 }; 418 419 edac@78800000 { 420 compatible = "apm,xgene-edac"; 421 #address-cells = <2>; 422 #size-cells = <2>; 423 ranges; 424 regmap-csw = <&csw>; 425 regmap-mcba = <&mcba>; 426 regmap-mcbb = <&mcbb>; 427 regmap-efuse = <&efuse>; 428 reg = <0x0 0x78800000 0x0 0x100>; 429 interrupts = <0x0 0x20 0x4>, 430 <0x0 0x21 0x4>, 431 <0x0 0x27 0x4>; 432 433 edacmc@7e800000 { 434 compatible = "apm,xgene-edac-mc"; 435 reg = <0x0 0x7e800000 0x0 0x1000>; 436 memory-controller = <0>; 437 }; 438 439 edacmc@7e840000 { 440 compatible = "apm,xgene-edac-mc"; 441 reg = <0x0 0x7e840000 0x0 0x1000>; 442 memory-controller = <1>; 443 }; 444 445 edacmc@7e880000 { 446 compatible = "apm,xgene-edac-mc"; 447 reg = <0x0 0x7e880000 0x0 0x1000>; 448 memory-controller = <2>; 449 }; 450 451 edacmc@7e8c0000 { 452 compatible = "apm,xgene-edac-mc"; 453 reg = <0x0 0x7e8c0000 0x0 0x1000>; 454 memory-controller = <3>; 455 }; 456 457 edacpmd@7c000000 { 458 compatible = "apm,xgene-edac-pmd"; 459 reg = <0x0 0x7c000000 0x0 0x200000>; 460 pmd-controller = <0>; 461 }; 462 463 edacpmd@7c200000 { 464 compatible = "apm,xgene-edac-pmd"; 465 reg = <0x0 0x7c200000 0x0 0x200000>; 466 pmd-controller = <1>; 467 }; 468 469 edacpmd@7c400000 { 470 compatible = "apm,xgene-edac-pmd"; 471 reg = <0x0 0x7c400000 0x0 0x200000>; 472 pmd-controller = <2>; 473 }; 474 475 edacpmd@7c600000 { 476 compatible = "apm,xgene-edac-pmd"; 477 reg = <0x0 0x7c600000 0x0 0x200000>; 478 pmd-controller = <3>; 479 }; 480 }; 481 482 pcie0: pcie@1f2b0000 { 483 status = "disabled"; 484 device_type = "pci"; 485 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 486 #interrupt-cells = <1>; 487 #size-cells = <2>; 488 #address-cells = <3>; 489 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ 490 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 491 reg-names = "csr", "cfg"; 492 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ 493 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ 494 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ 495 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 496 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 497 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 498 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 499 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 500 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 501 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; 502 dma-coherent; 503 clocks = <&pcie0clk 0>; 504 msi-parent = <&msi>; 505 }; 506 507 pcie1: pcie@1f2c0000 { 508 status = "disabled"; 509 device_type = "pci"; 510 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 511 #interrupt-cells = <1>; 512 #size-cells = <2>; 513 #address-cells = <3>; 514 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ 515 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 516 reg-names = "csr", "cfg"; 517 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ 518 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ 519 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ 520 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 521 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 522 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 523 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1 524 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1 525 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1 526 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>; 527 dma-coherent; 528 clocks = <&pcie1clk 0>; 529 msi-parent = <&msi>; 530 }; 531 532 pcie2: pcie@1f2d0000 { 533 status = "disabled"; 534 device_type = "pci"; 535 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 536 #interrupt-cells = <1>; 537 #size-cells = <2>; 538 #address-cells = <3>; 539 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ 540 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ 541 reg-names = "csr", "cfg"; 542 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ 543 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ 544 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ 545 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 546 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 547 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 548 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1 549 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1 550 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1 551 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>; 552 dma-coherent; 553 clocks = <&pcie2clk 0>; 554 msi-parent = <&msi>; 555 }; 556 557 pcie3: pcie@1f500000 { 558 status = "disabled"; 559 device_type = "pci"; 560 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 561 #interrupt-cells = <1>; 562 #size-cells = <2>; 563 #address-cells = <3>; 564 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ 565 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 566 reg-names = "csr", "cfg"; 567 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ 568 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ 569 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ 570 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 571 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 572 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 573 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1 574 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1 575 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1 576 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>; 577 dma-coherent; 578 clocks = <&pcie3clk 0>; 579 msi-parent = <&msi>; 580 }; 581 582 pcie4: pcie@1f510000 { 583 status = "disabled"; 584 device_type = "pci"; 585 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 586 #interrupt-cells = <1>; 587 #size-cells = <2>; 588 #address-cells = <3>; 589 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ 590 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ 591 reg-names = "csr", "cfg"; 592 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ 593 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ 594 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ 595 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 596 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 597 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 598 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1 599 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1 600 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1 601 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>; 602 dma-coherent; 603 clocks = <&pcie4clk 0>; 604 msi-parent = <&msi>; 605 }; 606 607 serial0: serial@1c020000 { 608 status = "disabled"; 609 device_type = "serial"; 610 compatible = "ns16550a"; 611 reg = <0 0x1c020000 0x0 0x1000>; 612 reg-shift = <2>; 613 clock-frequency = <10000000>; /* Updated by bootloader */ 614 interrupt-parent = <&gic>; 615 interrupts = <0x0 0x4c 0x4>; 616 }; 617 618 serial1: serial@1c021000 { 619 status = "disabled"; 620 device_type = "serial"; 621 compatible = "ns16550a"; 622 reg = <0 0x1c021000 0x0 0x1000>; 623 reg-shift = <2>; 624 clock-frequency = <10000000>; /* Updated by bootloader */ 625 interrupt-parent = <&gic>; 626 interrupts = <0x0 0x4d 0x4>; 627 }; 628 629 serial2: serial@1c022000 { 630 status = "disabled"; 631 device_type = "serial"; 632 compatible = "ns16550a"; 633 reg = <0 0x1c022000 0x0 0x1000>; 634 reg-shift = <2>; 635 clock-frequency = <10000000>; /* Updated by bootloader */ 636 interrupt-parent = <&gic>; 637 interrupts = <0x0 0x4e 0x4>; 638 }; 639 640 serial3: serial@1c023000 { 641 status = "disabled"; 642 device_type = "serial"; 643 compatible = "ns16550a"; 644 reg = <0 0x1c023000 0x0 0x1000>; 645 reg-shift = <2>; 646 clock-frequency = <10000000>; /* Updated by bootloader */ 647 interrupt-parent = <&gic>; 648 interrupts = <0x0 0x4f 0x4>; 649 }; 650 651 phy1: phy@1f21a000 { 652 compatible = "apm,xgene-phy"; 653 reg = <0x0 0x1f21a000 0x0 0x100>; 654 #phy-cells = <1>; 655 clocks = <&sataphy1clk 0>; 656 status = "disabled"; 657 apm,tx-boost-gain = <30 30 30 30 30 30>; 658 apm,tx-eye-tuning = <2 10 10 2 10 10>; 659 }; 660 661 phy2: phy@1f22a000 { 662 compatible = "apm,xgene-phy"; 663 reg = <0x0 0x1f22a000 0x0 0x100>; 664 #phy-cells = <1>; 665 clocks = <&sataphy2clk 0>; 666 status = "ok"; 667 apm,tx-boost-gain = <30 30 30 30 30 30>; 668 apm,tx-eye-tuning = <1 10 10 2 10 10>; 669 }; 670 671 phy3: phy@1f23a000 { 672 compatible = "apm,xgene-phy"; 673 reg = <0x0 0x1f23a000 0x0 0x100>; 674 #phy-cells = <1>; 675 clocks = <&sataphy3clk 0>; 676 status = "ok"; 677 apm,tx-boost-gain = <31 31 31 31 31 31>; 678 apm,tx-eye-tuning = <2 10 10 2 10 10>; 679 }; 680 681 sata1: sata@1a000000 { 682 compatible = "apm,xgene-ahci"; 683 reg = <0x0 0x1a000000 0x0 0x1000>, 684 <0x0 0x1f210000 0x0 0x1000>, 685 <0x0 0x1f21d000 0x0 0x1000>, 686 <0x0 0x1f21e000 0x0 0x1000>, 687 <0x0 0x1f217000 0x0 0x1000>; 688 interrupts = <0x0 0x86 0x4>; 689 dma-coherent; 690 status = "disabled"; 691 clocks = <&sata01clk 0>; 692 phys = <&phy1 0>; 693 phy-names = "sata-phy"; 694 }; 695 696 sata2: sata@1a400000 { 697 compatible = "apm,xgene-ahci"; 698 reg = <0x0 0x1a400000 0x0 0x1000>, 699 <0x0 0x1f220000 0x0 0x1000>, 700 <0x0 0x1f22d000 0x0 0x1000>, 701 <0x0 0x1f22e000 0x0 0x1000>, 702 <0x0 0x1f227000 0x0 0x1000>; 703 interrupts = <0x0 0x87 0x4>; 704 dma-coherent; 705 status = "ok"; 706 clocks = <&sata23clk 0>; 707 phys = <&phy2 0>; 708 phy-names = "sata-phy"; 709 }; 710 711 sata3: sata@1a800000 { 712 compatible = "apm,xgene-ahci"; 713 reg = <0x0 0x1a800000 0x0 0x1000>, 714 <0x0 0x1f230000 0x0 0x1000>, 715 <0x0 0x1f23d000 0x0 0x1000>, 716 <0x0 0x1f23e000 0x0 0x1000>; 717 interrupts = <0x0 0x88 0x4>; 718 dma-coherent; 719 status = "ok"; 720 clocks = <&sata45clk 0>; 721 phys = <&phy3 0>; 722 phy-names = "sata-phy"; 723 }; 724 725 sbgpio: sbgpio@17001000{ 726 compatible = "apm,xgene-gpio-sb"; 727 reg = <0x0 0x17001000 0x0 0x400>; 728 #gpio-cells = <2>; 729 gpio-controller; 730 interrupts = <0x0 0x28 0x1>, 731 <0x0 0x29 0x1>, 732 <0x0 0x2a 0x1>, 733 <0x0 0x2b 0x1>, 734 <0x0 0x2c 0x1>, 735 <0x0 0x2d 0x1>; 736 }; 737 738 rtc: rtc@10510000 { 739 compatible = "apm,xgene-rtc"; 740 reg = <0x0 0x10510000 0x0 0x400>; 741 interrupts = <0x0 0x46 0x4>; 742 #clock-cells = <1>; 743 clocks = <&rtcclk 0>; 744 }; 745 746 menet: ethernet@17020000 { 747 compatible = "apm,xgene-enet"; 748 status = "disabled"; 749 reg = <0x0 0x17020000 0x0 0xd100>, 750 <0x0 0X17030000 0x0 0Xc300>, 751 <0x0 0X10000000 0x0 0X200>; 752 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 753 interrupts = <0x0 0x3c 0x4>; 754 dma-coherent; 755 clocks = <&menetclk 0>; 756 /* mac address will be overwritten by the bootloader */ 757 local-mac-address = [00 00 00 00 00 00]; 758 phy-connection-type = "rgmii"; 759 phy-handle = <&menetphy>; 760 mdio { 761 compatible = "apm,xgene-mdio"; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 menetphy: menetphy@3 { 765 compatible = "ethernet-phy-id001c.c915"; 766 reg = <0x3>; 767 }; 768 769 }; 770 }; 771 772 sgenet0: ethernet@1f210000 { 773 compatible = "apm,xgene1-sgenet"; 774 status = "disabled"; 775 reg = <0x0 0x1f210000 0x0 0xd100>, 776 <0x0 0x1f200000 0x0 0Xc300>, 777 <0x0 0x1B000000 0x0 0X200>; 778 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 779 interrupts = <0x0 0xA0 0x4>, 780 <0x0 0xA1 0x4>; 781 dma-coherent; 782 clocks = <&sge0clk 0>; 783 local-mac-address = [00 00 00 00 00 00]; 784 phy-connection-type = "sgmii"; 785 }; 786 787 sgenet1: ethernet@1f210030 { 788 compatible = "apm,xgene1-sgenet"; 789 status = "disabled"; 790 reg = <0x0 0x1f210030 0x0 0xd100>, 791 <0x0 0x1f200000 0x0 0Xc300>, 792 <0x0 0x1B000000 0x0 0X8000>; 793 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 794 interrupts = <0x0 0xAC 0x4>, 795 <0x0 0xAD 0x4>; 796 port-id = <1>; 797 dma-coherent; 798 clocks = <&sge1clk 0>; 799 local-mac-address = [00 00 00 00 00 00]; 800 phy-connection-type = "sgmii"; 801 }; 802 803 xgenet: ethernet@1f610000 { 804 compatible = "apm,xgene1-xgenet"; 805 status = "disabled"; 806 reg = <0x0 0x1f610000 0x0 0xd100>, 807 <0x0 0x1f600000 0x0 0Xc300>, 808 <0x0 0x18000000 0x0 0X200>; 809 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 810 interrupts = <0x0 0x60 0x4>, 811 <0x0 0x61 0x4>; 812 dma-coherent; 813 clocks = <&xge0clk 0>; 814 /* mac address will be overwritten by the bootloader */ 815 local-mac-address = [00 00 00 00 00 00]; 816 phy-connection-type = "xgmii"; 817 }; 818 819 rng: rng@10520000 { 820 compatible = "apm,xgene-rng"; 821 reg = <0x0 0x10520000 0x0 0x100>; 822 interrupts = <0x0 0x41 0x4>; 823 clocks = <&rngpkaclk 0>; 824 }; 825 826 dma: dma@1f270000 { 827 compatible = "apm,xgene-storm-dma"; 828 device_type = "dma"; 829 reg = <0x0 0x1f270000 0x0 0x10000>, 830 <0x0 0x1f200000 0x0 0x10000>, 831 <0x0 0x1b000000 0x0 0x400000>, 832 <0x0 0x1054a000 0x0 0x100>; 833 interrupts = <0x0 0x82 0x4>, 834 <0x0 0xb8 0x4>, 835 <0x0 0xb9 0x4>, 836 <0x0 0xba 0x4>, 837 <0x0 0xbb 0x4>; 838 dma-coherent; 839 clocks = <&dmaclk 0>; 840 }; 841 }; 842}; 843