1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/meson-s4-gpio.h> 10#include <dt-bindings/clock/amlogic,s4-pll-clkc.h> 11#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h> 12#include <dt-bindings/power/meson-s4-power.h> 13#include <dt-bindings/reset/amlogic,meson-s4-reset.h> 14 15/ { 16 cpus { 17 #address-cells = <2>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a35"; 23 reg = <0x0 0x0>; 24 enable-method = "psci"; 25 }; 26 27 cpu1: cpu@1 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a35"; 30 reg = <0x0 0x1>; 31 enable-method = "psci"; 32 }; 33 34 cpu2: cpu@2 { 35 device_type = "cpu"; 36 compatible = "arm,cortex-a35"; 37 reg = <0x0 0x2>; 38 enable-method = "psci"; 39 }; 40 41 cpu3: cpu@3 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a35"; 44 reg = <0x0 0x3>; 45 enable-method = "psci"; 46 }; 47 }; 48 49 timer { 50 compatible = "arm,armv8-timer"; 51 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 53 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 54 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 55 }; 56 57 psci { 58 compatible = "arm,psci-1.0"; 59 method = "smc"; 60 }; 61 62 xtal: xtal-clk { 63 compatible = "fixed-clock"; 64 clock-frequency = <24000000>; 65 clock-output-names = "xtal"; 66 #clock-cells = <0>; 67 }; 68 69 firmware { 70 sm: secure-monitor { 71 compatible = "amlogic,meson-gxbb-sm"; 72 73 pwrc: power-controller { 74 compatible = "amlogic,meson-s4-pwrc"; 75 #power-domain-cells = <1>; 76 }; 77 }; 78 }; 79 80 soc { 81 compatible = "simple-bus"; 82 #address-cells = <2>; 83 #size-cells = <2>; 84 ranges; 85 86 gic: interrupt-controller@fff01000 { 87 compatible = "arm,gic-400"; 88 #interrupt-cells = <3>; 89 #address-cells = <0>; 90 interrupt-controller; 91 reg = <0x0 0xfff01000 0 0x1000>, 92 <0x0 0xfff02000 0 0x2000>, 93 <0x0 0xfff04000 0 0x2000>, 94 <0x0 0xfff06000 0 0x2000>; 95 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 96 }; 97 98 apb4: bus@fe000000 { 99 compatible = "simple-bus"; 100 reg = <0x0 0xfe000000 0x0 0x480000>; 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 104 105 clkc_periphs: clock-controller@0 { 106 compatible = "amlogic,s4-peripherals-clkc"; 107 reg = <0x0 0x0 0x0 0x49c>; 108 clocks = <&clkc_pll CLKID_FCLK_DIV2>, 109 <&clkc_pll CLKID_FCLK_DIV2P5>, 110 <&clkc_pll CLKID_FCLK_DIV3>, 111 <&clkc_pll CLKID_FCLK_DIV4>, 112 <&clkc_pll CLKID_FCLK_DIV5>, 113 <&clkc_pll CLKID_FCLK_DIV7>, 114 <&clkc_pll CLKID_HIFI_PLL>, 115 <&clkc_pll CLKID_GP0_PLL>, 116 <&clkc_pll CLKID_MPLL0>, 117 <&clkc_pll CLKID_MPLL1>, 118 <&clkc_pll CLKID_MPLL2>, 119 <&clkc_pll CLKID_MPLL3>, 120 <&clkc_pll CLKID_HDMI_PLL>, 121 <&xtal>; 122 clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", 123 "fclk_div4", "fclk_div5", "fclk_div7", 124 "hifi_pll", "gp0_pll", "mpll0", "mpll1", 125 "mpll2", "mpll3", "hdmi_pll", "xtal"; 126 #clock-cells = <1>; 127 }; 128 129 clkc_pll: clock-controller@8000 { 130 compatible = "amlogic,s4-pll-clkc"; 131 reg = <0x0 0x8000 0x0 0x1e8>; 132 clocks = <&xtal>; 133 clock-names = "xtal"; 134 #clock-cells = <1>; 135 }; 136 137 watchdog@2100 { 138 compatible = "amlogic,s4-wdt", "amlogic,t7-wdt"; 139 reg = <0x0 0x2100 0x0 0x10>; 140 clocks = <&xtal>; 141 }; 142 143 periphs_pinctrl: pinctrl@4000 { 144 compatible = "amlogic,meson-s4-periphs-pinctrl"; 145 #address-cells = <2>; 146 #size-cells = <2>; 147 ranges; 148 149 gpio: bank@4000 { 150 reg = <0x0 0x4000 0x0 0x004c>, 151 <0x0 0x40c0 0x0 0x0220>; 152 reg-names = "mux", "gpio"; 153 gpio-controller; 154 #gpio-cells = <2>; 155 gpio-ranges = <&periphs_pinctrl 0 0 82>; 156 }; 157 158 remote_pins: remote-pin { 159 mux { 160 groups = "remote_in"; 161 function = "remote_in"; 162 bias-disable; 163 }; 164 }; 165 166 i2c0_pins1: i2c0-pins1 { 167 mux { 168 groups = "i2c0_sda", 169 "i2c0_scl"; 170 function = "i2c0"; 171 drive-strength-microamp = <3000>; 172 bias-disable; 173 }; 174 }; 175 176 i2c1_pins1: i2c1-pins1 { 177 mux { 178 groups = "i2c1_sda_c", 179 "i2c1_scl_c"; 180 function = "i2c1"; 181 drive-strength-microamp = <3000>; 182 bias-disable; 183 }; 184 }; 185 186 i2c1_pins2: i2c1-pins2 { 187 mux { 188 groups = "i2c1_sda_d", 189 "i2c1_scl_d"; 190 function = "i2c1"; 191 drive-strength-microamp = <3000>; 192 bias-disable; 193 }; 194 }; 195 196 i2c1_pins3: i2c1-pins3 { 197 mux { 198 groups = "i2c1_sda_h", 199 "i2c1_scl_h"; 200 function = "i2c1"; 201 drive-strength-microamp = <3000>; 202 bias-disable; 203 }; 204 }; 205 206 i2c1_pins4: i2c1-pins4 { 207 mux { 208 groups = "i2c1_sda_x", 209 "i2c1_scl_x"; 210 function = "i2c1"; 211 drive-strength-microamp = <3000>; 212 bias-disable; 213 }; 214 }; 215 216 i2c2_pins1: i2c2-pins1 { 217 mux { 218 groups = "i2c2_sda_d", 219 "i2c2_scl_d"; 220 function = "i2c2"; 221 drive-strength-microamp = <3000>; 222 bias-disable; 223 }; 224 }; 225 226 i2c2_pins2: i2c2-pins2 { 227 mux { 228 groups = "i2c2_sda_h8", 229 "i2c2_scl_h9"; 230 function = "i2c2"; 231 drive-strength-microamp = <3000>; 232 bias-disable; 233 }; 234 }; 235 236 i2c2_pins3: i2c2-pins3 { 237 mux { 238 groups = "i2c2_sda_h0", 239 "i2c2_scl_h1"; 240 function = "i2c2"; 241 drive-strength-microamp = <3000>; 242 bias-disable; 243 }; 244 }; 245 246 i2c3_pins1: i2c3-pins1 { 247 mux { 248 groups = "i2c3_sda_x", 249 "i2c3_scl_x"; 250 function = "i2c3"; 251 drive-strength-microamp = <3000>; 252 bias-disable; 253 }; 254 }; 255 256 i2c3_pins2: i2c3-pins2 { 257 mux { 258 groups = "i2c3_sda_z", 259 "i2c3_scl_z"; 260 function = "i2c3"; 261 drive-strength-microamp = <3000>; 262 bias-disable; 263 }; 264 }; 265 266 i2c4_pins1: i2c4-pins1 { 267 mux { 268 groups = "i2c4_sda_c", 269 "i2c4_scl_c"; 270 function = "i2c4"; 271 drive-strength-microamp = <3000>; 272 bias-disable; 273 }; 274 }; 275 276 i2c4_pins2: i2c4-pins2 { 277 mux { 278 groups = "i2c4_sda_d", 279 "i2c4_scl_d"; 280 function = "i2c4"; 281 drive-strength-microamp = <3000>; 282 bias-disable; 283 }; 284 }; 285 286 i2c4_pins3: i2c4-pins3 { 287 mux { 288 groups = "i2c4_sda_z", 289 "i2c4_scl_z"; 290 function = "i2c4"; 291 drive-strength-microamp = <3000>; 292 bias-disable; 293 }; 294 }; 295 296 nand_pins: nand-pins { 297 mux { 298 groups = "emmc_nand_d0", 299 "emmc_nand_d1", 300 "emmc_nand_d2", 301 "emmc_nand_d3", 302 "emmc_nand_d4", 303 "emmc_nand_d5", 304 "emmc_nand_d6", 305 "emmc_nand_d7", 306 "nand_ce0", 307 "nand_ale", 308 "nand_cle", 309 "nand_wen_clk", 310 "nand_ren_wr"; 311 function = "nand"; 312 input-enable; 313 }; 314 }; 315 316 pwm_a_pins1: pwm-a-pins1 { 317 mux { 318 groups = "pwm_a_d"; 319 function = "pwm_a"; 320 }; 321 }; 322 323 pwm_a_pins2: pwm-a-pins2 { 324 mux { 325 groups = "pwm_a_x"; 326 function = "pwm_a"; 327 }; 328 }; 329 330 pwm_b_pins1: pwm-b-pins1 { 331 mux { 332 groups = "pwm_b_d"; 333 function = "pwm_b"; 334 }; 335 }; 336 337 pwm_b_pins2: pwm-b-pins2 { 338 mux { 339 groups = "pwm_b_x"; 340 function = "pwm_b"; 341 }; 342 }; 343 344 pwm_c_pins1: pwm-c-pins1 { 345 mux { 346 groups = "pwm_c_d"; 347 function = "pwm_c"; 348 }; 349 }; 350 351 pwm_c_pins2: pwm-c-pins2 { 352 mux { 353 groups = "pwm_c_x"; 354 function = "pwm_c"; 355 }; 356 }; 357 358 pwm_d_pins1: pwm-d-pins1 { 359 mux { 360 groups = "pwm_d_d"; 361 function = "pwm_d"; 362 }; 363 }; 364 365 pwm_d_pins2: pwm-d-pins2 { 366 mux { 367 groups = "pwm_d_h"; 368 function = "pwm_d"; 369 }; 370 }; 371 372 pwm_e_pins1: pwm-e-pins1 { 373 mux { 374 groups = "pwm_e_x"; 375 function = "pwm_e"; 376 }; 377 }; 378 379 pwm_e_pins2: pwm-e-pins2 { 380 mux { 381 groups = "pwm_e_z"; 382 function = "pwm_e"; 383 }; 384 }; 385 386 pwm_f_pins1: pwm-f-pins1 { 387 mux { 388 groups = "pwm_f_x"; 389 function = "pwm_f"; 390 }; 391 }; 392 393 pwm_f_pins2: pwm-f-pins2 { 394 mux { 395 groups = "pwm_f_z"; 396 function = "pwm_f"; 397 }; 398 }; 399 400 pwm_g_pins1: pwm-g-pins1 { 401 mux { 402 groups = "pwm_g_d"; 403 function = "pwm_g"; 404 }; 405 }; 406 407 pwm_g_pins2: pwm-g-pins2 { 408 mux { 409 groups = "pwm_g_z"; 410 function = "pwm_g"; 411 }; 412 }; 413 414 pwm_h_pins: pwm-h-pins { 415 mux { 416 groups = "pwm_h"; 417 function = "pwm_h"; 418 }; 419 }; 420 421 pwm_i_pins1: pwm-i-pins1 { 422 mux { 423 groups = "pwm_i_d"; 424 function = "pwm_i"; 425 }; 426 }; 427 428 pwm_i_pins2: pwm-i-pins2 { 429 mux { 430 groups = "pwm_i_h"; 431 function = "pwm_i"; 432 }; 433 }; 434 435 pwm_j_pins: pwm-j-pins { 436 mux { 437 groups = "pwm_j"; 438 function = "pwm_j"; 439 }; 440 }; 441 442 pwm_a_hiz_pins: pwm-a-hiz-pins { 443 mux { 444 groups = "pwm_a_hiz"; 445 function = "pwm_a_hiz"; 446 }; 447 }; 448 449 pwm_b_hiz_pins: pwm-b-hiz-pins { 450 mux { 451 groups = "pwm_b_hiz"; 452 function = "pwm_b_hiz"; 453 }; 454 }; 455 456 pwm_c_hiz_pins: pwm-c-hiz-pins { 457 mux { 458 groups = "pwm_c_hiz"; 459 function = "pwm_c_hiz"; 460 }; 461 }; 462 463 pwm_g_hiz_pins: pwm-g-hiz-pins { 464 mux { 465 groups = "pwm_g_hiz"; 466 function = "pwm_g_hiz"; 467 }; 468 }; 469 470 sdcard_pins: sdcard-pins { 471 mux { 472 groups = "sdcard_d0_c", 473 "sdcard_d1_c", 474 "sdcard_d2_c", 475 "sdcard_d3_c", 476 "sdcard_clk_c", 477 "sdcard_cmd_c"; 478 function = "sdcard"; 479 bias-pull-up; 480 drive-strength-microamp = <4000>; 481 }; 482 }; 483 484 sdcard_clk_gate_pins: sdcard-clk-gate-pins { 485 mux { 486 groups = "GPIOC_4"; 487 function = "gpio_periphs"; 488 bias-pull-down; 489 drive-strength-microamp = <4000>; 490 }; 491 }; 492 493 emmc_pins: emmc-pins { 494 mux-0 { 495 groups = "emmc_nand_d0", 496 "emmc_nand_d1", 497 "emmc_nand_d2", 498 "emmc_nand_d3", 499 "emmc_nand_d4", 500 "emmc_nand_d5", 501 "emmc_nand_d6", 502 "emmc_nand_d7", 503 "emmc_cmd"; 504 function = "emmc"; 505 bias-pull-up; 506 drive-strength-microamp = <4000>; 507 }; 508 mux-1 { 509 groups = "emmc_clk"; 510 function = "emmc"; 511 bias-pull-up; 512 drive-strength-microamp = <4000>; 513 }; 514 }; 515 516 emmc_ds_pins: emmc-ds-pins { 517 mux { 518 groups = "emmc_nand_ds"; 519 function = "emmc"; 520 bias-pull-down; 521 drive-strength-microamp = <4000>; 522 }; 523 }; 524 525 emmc_clk_gate_pins: emmc-clk-gate-pins { 526 mux { 527 groups = "GPIOB_8"; 528 function = "gpio_periphs"; 529 bias-pull-down; 530 drive-strength-microamp = <4000>; 531 }; 532 }; 533 534 sdio_pins: sdio-pins { 535 mux { 536 groups = "sdio_d0", 537 "sdio_d1", 538 "sdio_d2", 539 "sdio_d3", 540 "sdio_clk", 541 "sdio_cmd"; 542 function = "sdio"; 543 bias-pull-up; 544 drive-strength-microamp = <4000>; 545 }; 546 }; 547 548 sdio_clk_gate_pins: sdio-clk-gate-pins { 549 mux { 550 groups = "GPIOX_4"; 551 function = "gpio_periphs"; 552 bias-pull-down; 553 drive-strength-microamp = <4000>; 554 }; 555 }; 556 557 spicc0_pins_x: spicc0-pins_x { 558 mux { 559 groups = "spi_a_mosi_x", 560 "spi_a_miso_x", 561 "spi_a_clk_x"; 562 function = "spi_a"; 563 drive-strength-microamp = <3000>; 564 }; 565 }; 566 567 spicc0_pins_h: spicc0-pins-h { 568 mux { 569 groups = "spi_a_mosi_h", 570 "spi_a_miso_h", 571 "spi_a_clk_h"; 572 function = "spi_a"; 573 drive-strength-microamp = <3000>; 574 }; 575 }; 576 577 spicc0_pins_z: spicc0-pins-z { 578 mux { 579 groups = "spi_a_mosi_z", 580 "spi_a_miso_z", 581 "spi_a_clk_z"; 582 function = "spi_a"; 583 drive-strength-microamp = <3000>; 584 }; 585 }; 586 587 }; 588 589 gpio_intc: interrupt-controller@4080 { 590 compatible = "amlogic,meson-s4-gpio-intc", 591 "amlogic,meson-gpio-intc"; 592 reg = <0x0 0x4080 0x0 0x20>; 593 interrupt-controller; 594 #interrupt-cells = <2>; 595 amlogic,channel-interrupts = 596 <10 11 12 13 14 15 16 17 18 19 20 21>; 597 }; 598 599 eth_phy: mdio-multiplexer@28000 { 600 compatible = "amlogic,g12a-mdio-mux"; 601 reg = <0x0 0x28000 0x0 0xa4>; 602 603 #address-cells = <1>; 604 #size-cells = <0>; 605 clocks = <&clkc_periphs CLKID_ETHPHY>, 606 <&xtal>, 607 <&clkc_pll CLKID_MPLL_50M>; 608 clock-names = "pclk", "clkin0", "clkin1"; 609 mdio-parent-bus = <&mdio0>; 610 611 ext_mdio: mdio@0 { 612 reg = <0>; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 }; 616 617 int_mdio: mdio@1 { 618 reg = <1>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 622 internal_ephy: ethernet-phy@8 { 623 compatible = "ethernet-phy-id0180.3301", 624 "ethernet-phy-ieee802.3-c22"; 625 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 626 reg = <8>; 627 max-speed = <100>; 628 }; 629 }; 630 }; 631 632 spicc0: spi@50000 { 633 compatible = "amlogic,meson-g12a-spicc"; 634 reg = <0x0 0x50000 0x0 0x44>; 635 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&clkc_periphs CLKID_SPICC0>, 637 <&clkc_periphs CLKID_SPICC0_EN>; 638 clock-names = "core", "pclk"; 639 #address-cells = <1>; 640 #size-cells = <0>; 641 status = "disabled"; 642 }; 643 644 pwm_ab: pwm@58000 { 645 compatible = "amlogic,meson-s4-pwm"; 646 reg = <0x0 0x58000 0x0 0x24>; 647 clocks = <&clkc_periphs CLKID_PWM_A>, 648 <&clkc_periphs CLKID_PWM_B>; 649 #pwm-cells = <3>; 650 status = "disabled"; 651 }; 652 653 pwm_cd: pwm@5a000 { 654 compatible = "amlogic,meson-s4-pwm"; 655 reg = <0x0 0x5a000 0x0 0x24>; 656 clocks = <&clkc_periphs CLKID_PWM_C>, 657 <&clkc_periphs CLKID_PWM_D>; 658 #pwm-cells = <3>; 659 status = "disabled"; 660 }; 661 662 pwm_ef: pwm@5c000 { 663 compatible = "amlogic,meson-s4-pwm"; 664 reg = <0x0 0x5c000 0x0 0x24>; 665 clocks = <&clkc_periphs CLKID_PWM_E>, 666 <&clkc_periphs CLKID_PWM_F>; 667 #pwm-cells = <3>; 668 status = "disabled"; 669 }; 670 671 pwm_gh: pwm@5e000 { 672 compatible = "amlogic,meson-s4-pwm"; 673 reg = <0x0 0x5e000 0x0 0x24>; 674 clocks = <&clkc_periphs CLKID_PWM_G>, 675 <&clkc_periphs CLKID_PWM_H>; 676 #pwm-cells = <3>; 677 status = "disabled"; 678 }; 679 680 pwm_ij: pwm@60000 { 681 compatible = "amlogic,meson-s4-pwm"; 682 reg = <0x0 0x60000 0x0 0x24>; 683 clocks = <&clkc_periphs CLKID_PWM_I>, 684 <&clkc_periphs CLKID_PWM_J>; 685 #pwm-cells = <3>; 686 status = "disabled"; 687 }; 688 689 i2c0: i2c@66000 { 690 compatible = "amlogic,meson-axg-i2c"; 691 reg = <0x0 0x66000 0x0 0x20>; 692 interrupts = <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>; 693 clocks = <&clkc_periphs CLKID_I2C_M_A>; 694 #address-cells = <1>; 695 #size-cells = <0>; 696 status = "disabled"; 697 }; 698 699 i2c1: i2c@68000 { 700 compatible = "amlogic,meson-axg-i2c"; 701 reg = <0x0 0x68000 0x0 0x20>; 702 interrupts = <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>; 703 clocks = <&clkc_periphs CLKID_I2C_M_B>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 status = "disabled"; 707 }; 708 709 i2c2: i2c@6a000 { 710 compatible = "amlogic,meson-axg-i2c"; 711 reg = <0x0 0x6a000 0x0 0x20>; 712 interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; 713 clocks = <&clkc_periphs CLKID_I2C_M_C>; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 status = "disabled"; 717 }; 718 719 i2c3: i2c@6c000 { 720 compatible = "amlogic,meson-axg-i2c"; 721 reg = <0x0 0x6c000 0x0 0x20>; 722 interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>; 723 clocks = <&clkc_periphs CLKID_I2C_M_D>; 724 #address-cells = <1>; 725 #size-cells = <0>; 726 status = "disabled"; 727 }; 728 729 i2c4: i2c@6e000 { 730 compatible = "amlogic,meson-axg-i2c"; 731 reg = <0x0 0x6e000 0x0 0x20>; 732 interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>; 733 clocks = <&clkc_periphs CLKID_I2C_M_E>; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 status = "disabled"; 737 }; 738 739 nand: nand-controller@8c800 { 740 compatible = "amlogic,meson-axg-nfc"; 741 reg = <0x0 0x8c800 0x0 0x100>, <0x0 0x8c000 0x0 0x4>; 742 reg-names = "nfc", "emmc"; 743 interrupts = <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>; 744 clocks = <&clkc_periphs CLKID_SD_EMMC_C>, 745 <&clkc_pll CLKID_FCLK_DIV2>; 746 clock-names = "core", "device"; 747 status = "disabled"; 748 }; 749 750 uart_b: serial@7a000 { 751 compatible = "amlogic,meson-s4-uart", 752 "amlogic,meson-ao-uart"; 753 reg = <0x0 0x7a000 0x0 0x18>; 754 interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 755 clocks = <&xtal>, <&clkc_periphs CLKID_UART_B>, <&xtal>; 756 clock-names = "xtal", "pclk", "baud"; 757 status = "disabled"; 758 }; 759 760 reset: reset-controller@2000 { 761 compatible = "amlogic,meson-s4-reset"; 762 reg = <0x0 0x2000 0x0 0x98>; 763 #reset-cells = <1>; 764 }; 765 766 sec_ao: ao-secure@10220 { 767 compatible = "amlogic,s4-ao-secure", 768 "amlogic,meson-gx-ao-secure", 769 "syscon"; 770 reg = <0x0 0x10220 0x0 0x140>; 771 amlogic,has-chip-id; 772 }; 773 774 ir: ir@84040 { 775 compatible = "amlogic,meson-s4-ir"; 776 reg = <0x0 0x84040 0x0 0x30>; 777 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 778 status = "disabled"; 779 }; 780 781 hwrng: rng@440788 { 782 compatible = "amlogic,meson-s4-rng"; 783 reg = <0x0 0x440788 0x0 0x0c>; 784 }; 785 }; 786 787 ethmac: ethernet@fdc00000 { 788 compatible = "amlogic,meson-axg-dwmac", 789 "snps,dwmac-3.70a", 790 "snps,dwmac"; 791 reg = <0x0 0xfdc00000 0x0 0x10000>, 792 <0x0 0xfe024000 0x0 0x8>; 793 794 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 795 interrupt-names = "macirq"; 796 power-domains = <&pwrc PWRC_S4_ETH_ID>; 797 clocks = <&clkc_periphs CLKID_ETH>, 798 <&clkc_pll CLKID_FCLK_DIV2>, 799 <&clkc_pll CLKID_MPLL2>; 800 clock-names = "stmmaceth", "clkin0", "clkin1"; 801 rx-fifo-depth = <4096>; 802 tx-fifo-depth = <2048>; 803 status = "disabled"; 804 805 mdio0: mdio { 806 #address-cells = <1>; 807 #size-cells = <0>; 808 compatible = "snps,dwmac-mdio"; 809 }; 810 }; 811 812 sdio: mmc@fe088000 { 813 compatible = "amlogic,meson-axg-mmc"; 814 reg = <0x0 0xfe088000 0x0 0x800>; 815 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 816 clocks = <&clkc_periphs CLKID_SDEMMC_A>, 817 <&xtal>, 818 <&clkc_pll CLKID_FCLK_DIV2>; 819 clock-names = "core", "clkin0", "clkin1"; 820 resets = <&reset RESET_SD_EMMC_A>; 821 cap-sdio-irq; 822 keep-power-in-suspend; 823 status = "disabled"; 824 }; 825 826 sd: mmc@fe08a000 { 827 compatible = "amlogic,meson-axg-mmc"; 828 reg = <0x0 0xfe08a000 0x0 0x800>; 829 interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; 830 clocks = <&clkc_periphs CLKID_SDEMMC_B>, 831 <&clkc_periphs CLKID_SD_EMMC_B>, 832 <&clkc_pll CLKID_FCLK_DIV2>; 833 clock-names = "core", "clkin0", "clkin1"; 834 resets = <&reset RESET_SD_EMMC_B>; 835 status = "disabled"; 836 }; 837 838 emmc: mmc@fe08c000 { 839 compatible = "amlogic,meson-axg-mmc"; 840 reg = <0x0 0xfe08c000 0x0 0x800>; 841 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 842 clocks = <&clkc_periphs CLKID_NAND>, 843 <&xtal>, 844 <&clkc_pll CLKID_FCLK_DIV2>; 845 clock-names = "core", "clkin0", "clkin1"; 846 resets = <&reset RESET_NAND_EMMC>; 847 no-sdio; 848 no-sd; 849 status = "disabled"; 850 }; 851 }; 852}; 853