1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/meson-s4-gpio.h> 10#include <dt-bindings/clock/amlogic,s4-pll-clkc.h> 11#include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h> 12#include <dt-bindings/power/meson-s4-power.h> 13 14/ { 15 cpus { 16 #address-cells = <2>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a35"; 22 reg = <0x0 0x0>; 23 enable-method = "psci"; 24 }; 25 26 cpu1: cpu@1 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a35"; 29 reg = <0x0 0x1>; 30 enable-method = "psci"; 31 }; 32 33 cpu2: cpu@2 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a35"; 36 reg = <0x0 0x2>; 37 enable-method = "psci"; 38 }; 39 40 cpu3: cpu@3 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a35"; 43 reg = <0x0 0x3>; 44 enable-method = "psci"; 45 }; 46 }; 47 48 timer { 49 compatible = "arm,armv8-timer"; 50 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 51 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 53 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 54 }; 55 56 psci { 57 compatible = "arm,psci-1.0"; 58 method = "smc"; 59 }; 60 61 xtal: xtal-clk { 62 compatible = "fixed-clock"; 63 clock-frequency = <24000000>; 64 clock-output-names = "xtal"; 65 #clock-cells = <0>; 66 }; 67 68 firmware { 69 sm: secure-monitor { 70 compatible = "amlogic,meson-gxbb-sm"; 71 72 pwrc: power-controller { 73 compatible = "amlogic,meson-s4-pwrc"; 74 #power-domain-cells = <1>; 75 }; 76 }; 77 }; 78 79 soc { 80 compatible = "simple-bus"; 81 #address-cells = <2>; 82 #size-cells = <2>; 83 ranges; 84 85 gic: interrupt-controller@fff01000 { 86 compatible = "arm,gic-400"; 87 #interrupt-cells = <3>; 88 #address-cells = <0>; 89 interrupt-controller; 90 reg = <0x0 0xfff01000 0 0x1000>, 91 <0x0 0xfff02000 0 0x2000>, 92 <0x0 0xfff04000 0 0x2000>, 93 <0x0 0xfff06000 0 0x2000>; 94 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 95 }; 96 97 apb4: bus@fe000000 { 98 compatible = "simple-bus"; 99 reg = <0x0 0xfe000000 0x0 0x480000>; 100 #address-cells = <2>; 101 #size-cells = <2>; 102 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 103 104 clkc_periphs: clock-controller@0 { 105 compatible = "amlogic,s4-peripherals-clkc"; 106 reg = <0x0 0x0 0x0 0x49c>; 107 clocks = <&clkc_pll CLKID_FCLK_DIV2>, 108 <&clkc_pll CLKID_FCLK_DIV2P5>, 109 <&clkc_pll CLKID_FCLK_DIV3>, 110 <&clkc_pll CLKID_FCLK_DIV4>, 111 <&clkc_pll CLKID_FCLK_DIV5>, 112 <&clkc_pll CLKID_FCLK_DIV7>, 113 <&clkc_pll CLKID_HIFI_PLL>, 114 <&clkc_pll CLKID_GP0_PLL>, 115 <&clkc_pll CLKID_MPLL0>, 116 <&clkc_pll CLKID_MPLL1>, 117 <&clkc_pll CLKID_MPLL2>, 118 <&clkc_pll CLKID_MPLL3>, 119 <&clkc_pll CLKID_HDMI_PLL>, 120 <&xtal>; 121 clock-names = "fclk_div2", "fclk_div2p5", "fclk_div3", 122 "fclk_div4", "fclk_div5", "fclk_div7", 123 "hifi_pll", "gp0_pll", "mpll0", "mpll1", 124 "mpll2", "mpll3", "hdmi_pll", "xtal"; 125 #clock-cells = <1>; 126 }; 127 128 clkc_pll: clock-controller@8000 { 129 compatible = "amlogic,s4-pll-clkc"; 130 reg = <0x0 0x8000 0x0 0x1e8>; 131 clocks = <&xtal>; 132 clock-names = "xtal"; 133 #clock-cells = <1>; 134 }; 135 136 watchdog@2100 { 137 compatible = "amlogic,s4-wdt", "amlogic,t7-wdt"; 138 reg = <0x0 0x2100 0x0 0x10>; 139 clocks = <&xtal>; 140 }; 141 142 periphs_pinctrl: pinctrl@4000 { 143 compatible = "amlogic,meson-s4-periphs-pinctrl"; 144 #address-cells = <2>; 145 #size-cells = <2>; 146 ranges; 147 148 gpio: bank@4000 { 149 reg = <0x0 0x4000 0x0 0x004c>, 150 <0x0 0x40c0 0x0 0x0220>; 151 reg-names = "mux", "gpio"; 152 gpio-controller; 153 #gpio-cells = <2>; 154 gpio-ranges = <&periphs_pinctrl 0 0 82>; 155 }; 156 157 remote_pins: remote-pin { 158 mux { 159 groups = "remote_in"; 160 function = "remote_in"; 161 bias-disable; 162 }; 163 }; 164 165 i2c0_pins1: i2c0-pins1 { 166 mux { 167 groups = "i2c0_sda", 168 "i2c0_scl"; 169 function = "i2c0"; 170 drive-strength-microamp = <3000>; 171 bias-disable; 172 }; 173 }; 174 175 i2c1_pins1: i2c1-pins1 { 176 mux { 177 groups = "i2c1_sda_c", 178 "i2c1_scl_c"; 179 function = "i2c1"; 180 drive-strength-microamp = <3000>; 181 bias-disable; 182 }; 183 }; 184 185 i2c1_pins2: i2c1-pins2 { 186 mux { 187 groups = "i2c1_sda_d", 188 "i2c1_scl_d"; 189 function = "i2c1"; 190 drive-strength-microamp = <3000>; 191 bias-disable; 192 }; 193 }; 194 195 i2c1_pins3: i2c1-pins3 { 196 mux { 197 groups = "i2c1_sda_h", 198 "i2c1_scl_h"; 199 function = "i2c1"; 200 drive-strength-microamp = <3000>; 201 bias-disable; 202 }; 203 }; 204 205 i2c1_pins4: i2c1-pins4 { 206 mux { 207 groups = "i2c1_sda_x", 208 "i2c1_scl_x"; 209 function = "i2c1"; 210 drive-strength-microamp = <3000>; 211 bias-disable; 212 }; 213 }; 214 215 i2c2_pins1: i2c2-pins1 { 216 mux { 217 groups = "i2c2_sda_d", 218 "i2c2_scl_d"; 219 function = "i2c2"; 220 drive-strength-microamp = <3000>; 221 bias-disable; 222 }; 223 }; 224 225 i2c2_pins2: i2c2-pins2 { 226 mux { 227 groups = "i2c2_sda_h8", 228 "i2c2_scl_h9"; 229 function = "i2c2"; 230 drive-strength-microamp = <3000>; 231 bias-disable; 232 }; 233 }; 234 235 i2c2_pins3: i2c2-pins3 { 236 mux { 237 groups = "i2c2_sda_h0", 238 "i2c2_scl_h1"; 239 function = "i2c2"; 240 drive-strength-microamp = <3000>; 241 bias-disable; 242 }; 243 }; 244 245 i2c3_pins1: i2c3-pins1 { 246 mux { 247 groups = "i2c3_sda_x", 248 "i2c3_scl_x"; 249 function = "i2c3"; 250 drive-strength-microamp = <3000>; 251 bias-disable; 252 }; 253 }; 254 255 i2c3_pins2: i2c3-pins2 { 256 mux { 257 groups = "i2c3_sda_z", 258 "i2c3_scl_z"; 259 function = "i2c3"; 260 drive-strength-microamp = <3000>; 261 bias-disable; 262 }; 263 }; 264 265 i2c4_pins1: i2c4-pins1 { 266 mux { 267 groups = "i2c4_sda_c", 268 "i2c4_scl_c"; 269 function = "i2c4"; 270 drive-strength-microamp = <3000>; 271 bias-disable; 272 }; 273 }; 274 275 i2c4_pins2: i2c4-pins2 { 276 mux { 277 groups = "i2c4_sda_d", 278 "i2c4_scl_d"; 279 function = "i2c4"; 280 drive-strength-microamp = <3000>; 281 bias-disable; 282 }; 283 }; 284 285 i2c4_pins3: i2c4-pins3 { 286 mux { 287 groups = "i2c4_sda_z", 288 "i2c4_scl_z"; 289 function = "i2c4"; 290 drive-strength-microamp = <3000>; 291 bias-disable; 292 }; 293 }; 294 295 nand_pins: nand-pins { 296 mux { 297 groups = "emmc_nand_d0", 298 "emmc_nand_d1", 299 "emmc_nand_d2", 300 "emmc_nand_d3", 301 "emmc_nand_d4", 302 "emmc_nand_d5", 303 "emmc_nand_d6", 304 "emmc_nand_d7", 305 "nand_ce0", 306 "nand_ale", 307 "nand_cle", 308 "nand_wen_clk", 309 "nand_ren_wr"; 310 function = "nand"; 311 input-enable; 312 }; 313 }; 314 315 pwm_a_pins1: pwm-a-pins1 { 316 mux { 317 groups = "pwm_a_d"; 318 function = "pwm_a"; 319 }; 320 }; 321 322 pwm_a_pins2: pwm-a-pins2 { 323 mux { 324 groups = "pwm_a_x"; 325 function = "pwm_a"; 326 }; 327 }; 328 329 pwm_b_pins1: pwm-b-pins1 { 330 mux { 331 groups = "pwm_b_d"; 332 function = "pwm_b"; 333 }; 334 }; 335 336 pwm_b_pins2: pwm-b-pins2 { 337 mux { 338 groups = "pwm_b_x"; 339 function = "pwm_b"; 340 }; 341 }; 342 343 pwm_c_pins1: pwm-c-pins1 { 344 mux { 345 groups = "pwm_c_d"; 346 function = "pwm_c"; 347 }; 348 }; 349 350 pwm_c_pins2: pwm-c-pins2 { 351 mux { 352 groups = "pwm_c_x"; 353 function = "pwm_c"; 354 }; 355 }; 356 357 pwm_d_pins1: pwm-d-pins1 { 358 mux { 359 groups = "pwm_d_d"; 360 function = "pwm_d"; 361 }; 362 }; 363 364 pwm_d_pins2: pwm-d-pins2 { 365 mux { 366 groups = "pwm_d_h"; 367 function = "pwm_d"; 368 }; 369 }; 370 371 pwm_e_pins1: pwm-e-pins1 { 372 mux { 373 groups = "pwm_e_x"; 374 function = "pwm_e"; 375 }; 376 }; 377 378 pwm_e_pins2: pwm-e-pins2 { 379 mux { 380 groups = "pwm_e_z"; 381 function = "pwm_e"; 382 }; 383 }; 384 385 pwm_f_pins1: pwm-f-pins1 { 386 mux { 387 groups = "pwm_f_x"; 388 function = "pwm_f"; 389 }; 390 }; 391 392 pwm_f_pins2: pwm-f-pins2 { 393 mux { 394 groups = "pwm_f_z"; 395 function = "pwm_f"; 396 }; 397 }; 398 399 pwm_g_pins1: pwm-g-pins1 { 400 mux { 401 groups = "pwm_g_d"; 402 function = "pwm_g"; 403 }; 404 }; 405 406 pwm_g_pins2: pwm-g-pins2 { 407 mux { 408 groups = "pwm_g_z"; 409 function = "pwm_g"; 410 }; 411 }; 412 413 pwm_h_pins: pwm-h-pins { 414 mux { 415 groups = "pwm_h"; 416 function = "pwm_h"; 417 }; 418 }; 419 420 pwm_i_pins1: pwm-i-pins1 { 421 mux { 422 groups = "pwm_i_d"; 423 function = "pwm_i"; 424 }; 425 }; 426 427 pwm_i_pins2: pwm-i-pins2 { 428 mux { 429 groups = "pwm_i_h"; 430 function = "pwm_i"; 431 }; 432 }; 433 434 pwm_j_pins: pwm-j-pins { 435 mux { 436 groups = "pwm_j"; 437 function = "pwm_j"; 438 }; 439 }; 440 441 pwm_a_hiz_pins: pwm-a-hiz-pins { 442 mux { 443 groups = "pwm_a_hiz"; 444 function = "pwm_a_hiz"; 445 }; 446 }; 447 448 pwm_b_hiz_pins: pwm-b-hiz-pins { 449 mux { 450 groups = "pwm_b_hiz"; 451 function = "pwm_b_hiz"; 452 }; 453 }; 454 455 pwm_c_hiz_pins: pwm-c-hiz-pins { 456 mux { 457 groups = "pwm_c_hiz"; 458 function = "pwm_c_hiz"; 459 }; 460 }; 461 462 pwm_g_hiz_pins: pwm-g-hiz-pins { 463 mux { 464 groups = "pwm_g_hiz"; 465 function = "pwm_g_hiz"; 466 }; 467 }; 468 469 spicc0_pins_x: spicc0-pins_x { 470 mux { 471 groups = "spi_a_mosi_x", 472 "spi_a_miso_x", 473 "spi_a_clk_x"; 474 function = "spi_a"; 475 drive-strength-microamp = <3000>; 476 }; 477 }; 478 479 spicc0_pins_h: spicc0-pins-h { 480 mux { 481 groups = "spi_a_mosi_h", 482 "spi_a_miso_h", 483 "spi_a_clk_h"; 484 function = "spi_a"; 485 drive-strength-microamp = <3000>; 486 }; 487 }; 488 489 spicc0_pins_z: spicc0-pins-z { 490 mux { 491 groups = "spi_a_mosi_z", 492 "spi_a_miso_z", 493 "spi_a_clk_z"; 494 function = "spi_a"; 495 drive-strength-microamp = <3000>; 496 }; 497 }; 498 499 }; 500 501 gpio_intc: interrupt-controller@4080 { 502 compatible = "amlogic,meson-s4-gpio-intc", 503 "amlogic,meson-gpio-intc"; 504 reg = <0x0 0x4080 0x0 0x20>; 505 interrupt-controller; 506 #interrupt-cells = <2>; 507 amlogic,channel-interrupts = 508 <10 11 12 13 14 15 16 17 18 19 20 21>; 509 }; 510 511 eth_phy: mdio-multiplexer@28000 { 512 compatible = "amlogic,g12a-mdio-mux"; 513 reg = <0x0 0x28000 0x0 0xa4>; 514 515 #address-cells = <1>; 516 #size-cells = <0>; 517 clocks = <&clkc_periphs CLKID_ETHPHY>, 518 <&xtal>, 519 <&clkc_pll CLKID_MPLL_50M>; 520 clock-names = "pclk", "clkin0", "clkin1"; 521 mdio-parent-bus = <&mdio0>; 522 523 ext_mdio: mdio@0 { 524 reg = <0>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 }; 528 529 int_mdio: mdio@1 { 530 reg = <1>; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 534 internal_ephy: ethernet-phy@8 { 535 compatible = "ethernet-phy-id0180.3301", 536 "ethernet-phy-ieee802.3-c22"; 537 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 538 reg = <8>; 539 max-speed = <100>; 540 }; 541 }; 542 }; 543 544 spicc0: spi@50000 { 545 compatible = "amlogic,meson-g12a-spicc"; 546 reg = <0x0 0x50000 0x0 0x44>; 547 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&clkc_periphs CLKID_SPICC0>, 549 <&clkc_periphs CLKID_SPICC0_EN>; 550 clock-names = "core", "pclk"; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 status = "disabled"; 554 }; 555 556 pwm_ab: pwm@58000 { 557 compatible = "amlogic,meson-s4-pwm"; 558 reg = <0x0 0x58000 0x0 0x24>; 559 clocks = <&clkc_periphs CLKID_PWM_A>, 560 <&clkc_periphs CLKID_PWM_B>; 561 #pwm-cells = <3>; 562 status = "disabled"; 563 }; 564 565 pwm_cd: pwm@5a000 { 566 compatible = "amlogic,meson-s4-pwm"; 567 reg = <0x0 0x5a000 0x0 0x24>; 568 clocks = <&clkc_periphs CLKID_PWM_C>, 569 <&clkc_periphs CLKID_PWM_D>; 570 #pwm-cells = <3>; 571 status = "disabled"; 572 }; 573 574 pwm_ef: pwm@5c000 { 575 compatible = "amlogic,meson-s4-pwm"; 576 reg = <0x0 0x5c000 0x0 0x24>; 577 clocks = <&clkc_periphs CLKID_PWM_E>, 578 <&clkc_periphs CLKID_PWM_F>; 579 #pwm-cells = <3>; 580 status = "disabled"; 581 }; 582 583 pwm_gh: pwm@5e000 { 584 compatible = "amlogic,meson-s4-pwm"; 585 reg = <0x0 0x5e000 0x0 0x24>; 586 clocks = <&clkc_periphs CLKID_PWM_G>, 587 <&clkc_periphs CLKID_PWM_H>; 588 #pwm-cells = <3>; 589 status = "disabled"; 590 }; 591 592 pwm_ij: pwm@60000 { 593 compatible = "amlogic,meson-s4-pwm"; 594 reg = <0x0 0x60000 0x0 0x24>; 595 clocks = <&clkc_periphs CLKID_PWM_I>, 596 <&clkc_periphs CLKID_PWM_J>; 597 #pwm-cells = <3>; 598 status = "disabled"; 599 }; 600 601 i2c0: i2c@66000 { 602 compatible = "amlogic,meson-axg-i2c"; 603 reg = <0x0 0x66000 0x0 0x20>; 604 interrupts = <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>; 605 clocks = <&clkc_periphs CLKID_I2C_M_A>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 status = "disabled"; 609 }; 610 611 i2c1: i2c@68000 { 612 compatible = "amlogic,meson-axg-i2c"; 613 reg = <0x0 0x68000 0x0 0x20>; 614 interrupts = <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>; 615 clocks = <&clkc_periphs CLKID_I2C_M_B>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 status = "disabled"; 619 }; 620 621 i2c2: i2c@6a000 { 622 compatible = "amlogic,meson-axg-i2c"; 623 reg = <0x0 0x6a000 0x0 0x20>; 624 interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>; 625 clocks = <&clkc_periphs CLKID_I2C_M_C>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629 }; 630 631 i2c3: i2c@6c000 { 632 compatible = "amlogic,meson-axg-i2c"; 633 reg = <0x0 0x6c000 0x0 0x20>; 634 interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>; 635 clocks = <&clkc_periphs CLKID_I2C_M_D>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 status = "disabled"; 639 }; 640 641 i2c4: i2c@6e000 { 642 compatible = "amlogic,meson-axg-i2c"; 643 reg = <0x0 0x6e000 0x0 0x20>; 644 interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>; 645 clocks = <&clkc_periphs CLKID_I2C_M_E>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 status = "disabled"; 649 }; 650 651 nand: nand-controller@8c800 { 652 compatible = "amlogic,meson-axg-nfc"; 653 reg = <0x0 0x8c800 0x0 0x100>, <0x0 0x8c000 0x0 0x4>; 654 reg-names = "nfc", "emmc"; 655 interrupts = <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>; 656 clocks = <&clkc_periphs CLKID_SD_EMMC_C>, 657 <&clkc_pll CLKID_FCLK_DIV2>; 658 clock-names = "core", "device"; 659 status = "disabled"; 660 }; 661 662 uart_b: serial@7a000 { 663 compatible = "amlogic,meson-s4-uart", 664 "amlogic,meson-ao-uart"; 665 reg = <0x0 0x7a000 0x0 0x18>; 666 interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>; 667 clocks = <&xtal>, <&clkc_periphs CLKID_UART_B>, <&xtal>; 668 clock-names = "xtal", "pclk", "baud"; 669 status = "disabled"; 670 }; 671 672 reset: reset-controller@2000 { 673 compatible = "amlogic,meson-s4-reset"; 674 reg = <0x0 0x2000 0x0 0x98>; 675 #reset-cells = <1>; 676 }; 677 678 ir: ir@84040 { 679 compatible = "amlogic,meson-s4-ir"; 680 reg = <0x0 0x84040 0x0 0x30>; 681 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 682 status = "disabled"; 683 }; 684 685 hwrng: rng@440788 { 686 compatible = "amlogic,meson-s4-rng"; 687 reg = <0x0 0x440788 0x0 0x0c>; 688 }; 689 }; 690 691 ethmac: ethernet@fdc00000 { 692 compatible = "amlogic,meson-axg-dwmac", 693 "snps,dwmac-3.70a", 694 "snps,dwmac"; 695 reg = <0x0 0xfdc00000 0x0 0x10000>, 696 <0x0 0xfe024000 0x0 0x8>; 697 698 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 699 interrupt-names = "macirq"; 700 power-domains = <&pwrc PWRC_S4_ETH_ID>; 701 clocks = <&clkc_periphs CLKID_ETH>, 702 <&clkc_pll CLKID_FCLK_DIV2>, 703 <&clkc_pll CLKID_MPLL2>; 704 clock-names = "stmmaceth", "clkin0", "clkin1"; 705 rx-fifo-depth = <4096>; 706 tx-fifo-depth = <2048>; 707 status = "disabled"; 708 709 mdio0: mdio { 710 #address-cells = <1>; 711 #size-cells = <0>; 712 compatible = "snps,dwmac-mdio"; 713 }; 714 }; 715 }; 716}; 717