xref: /linux/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi (revision 27988c96687667e74df1a9a3b8662519bc1c29c9) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Endless Computers, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include "meson-gx.dtsi"
8#include <dt-bindings/clock/gxbb-clkc.h>
9#include <dt-bindings/clock/gxbb-aoclkc.h>
10#include <dt-bindings/gpio/meson-gxl-gpio.h>
11#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
12
13/ {
14	compatible = "amlogic,meson-gxl";
15
16	soc {
17		usb0: usb@c9000000 {
18			status = "disabled";
19			compatible = "amlogic,meson-gxl-dwc3";
20			#address-cells = <2>;
21			#size-cells = <2>;
22			ranges;
23
24			clocks = <&clkc CLKID_USB>;
25			clock-names = "usb_general";
26			resets = <&reset RESET_USB_OTG>;
27			reset-names = "usb_otg";
28
29			dwc3: dwc3@c9000000 {
30				compatible = "snps,dwc3";
31				reg = <0x0 0xc9000000 0x0 0x100000>;
32				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
33				dr_mode = "host";
34				maximum-speed = "high-speed";
35				snps,dis_u2_susphy_quirk;
36				phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>;
37			};
38		};
39	};
40};
41
42&apb {
43	usb2_phy0: phy@78000 {
44		compatible = "amlogic,meson-gxl-usb2-phy";
45		#phy-cells = <0>;
46		reg = <0x0 0x78000 0x0 0x20>;
47		clocks = <&clkc CLKID_USB>;
48		clock-names = "phy";
49		resets = <&reset RESET_USB_OTG>;
50		reset-names = "phy";
51		status = "okay";
52	};
53
54	usb2_phy1: phy@78020 {
55		compatible = "amlogic,meson-gxl-usb2-phy";
56		#phy-cells = <0>;
57		reg = <0x0 0x78020 0x0 0x20>;
58		clocks = <&clkc CLKID_USB>;
59		clock-names = "phy";
60		resets = <&reset RESET_USB_OTG>;
61		reset-names = "phy";
62		status = "okay";
63	};
64
65	usb3_phy: phy@78080 {
66		compatible = "amlogic,meson-gxl-usb3-phy";
67		#phy-cells = <0>;
68		reg = <0x0 0x78080 0x0 0x20>;
69		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
70		clocks = <&clkc CLKID_USB>, <&clkc_AO CLKID_AO_CEC_32K>;
71		clock-names = "phy", "peripheral";
72		resets = <&reset RESET_USB_OTG>, <&reset RESET_USB_OTG>;
73		reset-names = "phy", "peripheral";
74		status = "okay";
75	};
76};
77
78&efuse {
79	clocks = <&clkc CLKID_EFUSE>;
80};
81
82&ethmac {
83	reg = <0x0 0xc9410000 0x0 0x10000
84	       0x0 0xc8834540 0x0 0x4>;
85
86	clocks = <&clkc CLKID_ETH>,
87		 <&clkc CLKID_FCLK_DIV2>,
88		 <&clkc CLKID_MPLL2>;
89	clock-names = "stmmaceth", "clkin0", "clkin1";
90
91	mdio0: mdio {
92		#address-cells = <1>;
93		#size-cells = <0>;
94		compatible = "snps,dwmac-mdio";
95	};
96};
97
98&aobus {
99	pinctrl_aobus: pinctrl@14 {
100		compatible = "amlogic,meson-gxl-aobus-pinctrl";
101		#address-cells = <2>;
102		#size-cells = <2>;
103		ranges;
104
105		gpio_ao: bank@14 {
106			reg = <0x0 0x00014 0x0 0x8>,
107			      <0x0 0x0002c 0x0 0x4>,
108			      <0x0 0x00024 0x0 0x8>;
109			reg-names = "mux", "pull", "gpio";
110			gpio-controller;
111			#gpio-cells = <2>;
112			gpio-ranges = <&pinctrl_aobus 0 0 14>;
113		};
114
115		uart_ao_a_pins: uart_ao_a {
116			mux {
117				groups = "uart_tx_ao_a", "uart_rx_ao_a";
118				function = "uart_ao";
119				bias-disable;
120			};
121		};
122
123		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
124			mux {
125				groups = "uart_cts_ao_a",
126				       "uart_rts_ao_a";
127				function = "uart_ao";
128				bias-disable;
129			};
130		};
131
132		uart_ao_b_pins: uart_ao_b {
133			mux {
134				groups = "uart_tx_ao_b", "uart_rx_ao_b";
135				function = "uart_ao_b";
136				bias-disable;
137			};
138		};
139
140		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
141			mux {
142				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
143				function = "uart_ao_b";
144				bias-disable;
145			};
146		};
147
148		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
149			mux {
150				groups = "uart_cts_ao_b",
151				       "uart_rts_ao_b";
152				function = "uart_ao_b";
153				bias-disable;
154			};
155		};
156
157		remote_input_ao_pins: remote_input_ao {
158			mux {
159				groups = "remote_input_ao";
160				function = "remote_input_ao";
161				bias-disable;
162			};
163		};
164
165		i2c_ao_pins: i2c_ao {
166			mux {
167				groups = "i2c_sck_ao",
168				       "i2c_sda_ao";
169				function = "i2c_ao";
170				bias-disable;
171			};
172		};
173
174		pwm_ao_a_3_pins: pwm_ao_a_3 {
175			mux {
176				groups = "pwm_ao_a_3";
177				function = "pwm_ao_a";
178				bias-disable;
179			};
180		};
181
182		pwm_ao_a_8_pins: pwm_ao_a_8 {
183			mux {
184				groups = "pwm_ao_a_8";
185				function = "pwm_ao_a";
186				bias-disable;
187			};
188		};
189
190		pwm_ao_b_pins: pwm_ao_b {
191			mux {
192				groups = "pwm_ao_b";
193				function = "pwm_ao_b";
194				bias-disable;
195			};
196		};
197
198		pwm_ao_b_6_pins: pwm_ao_b_6 {
199			mux {
200				groups = "pwm_ao_b_6";
201				function = "pwm_ao_b";
202				bias-disable;
203			};
204		};
205
206		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
207			mux {
208				groups = "i2s_out_ch23_ao";
209				function = "i2s_out_ao";
210				bias-disable;
211			};
212		};
213
214		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
215			mux {
216				groups = "i2s_out_ch45_ao";
217				function = "i2s_out_ao";
218				bias-disable;
219			};
220		};
221
222		spdif_out_ao_6_pins: spdif_out_ao_6 {
223			mux {
224				groups = "spdif_out_ao_6";
225				function = "spdif_out_ao";
226				bias-disable;
227			};
228		};
229
230		spdif_out_ao_9_pins: spdif_out_ao_9 {
231			mux {
232				groups = "spdif_out_ao_9";
233				function = "spdif_out_ao";
234				bias-disable;
235			};
236		};
237
238		ao_cec_pins: ao_cec {
239			mux {
240				groups = "ao_cec";
241				function = "cec_ao";
242				bias-disable;
243			};
244		};
245
246		ee_cec_pins: ee_cec {
247			mux {
248				groups = "ee_cec";
249				function = "cec_ao";
250				bias-disable;
251			};
252		};
253	};
254};
255
256&cec_AO {
257	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
258	clock-names = "core";
259};
260
261&clkc_AO {
262	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
263	clocks = <&xtal>, <&clkc CLKID_CLK81>;
264	clock-names = "xtal", "mpeg-clk";
265};
266
267&gpio_intc {
268	compatible = "amlogic,meson-gpio-intc",
269		     "amlogic,meson-gxl-gpio-intc";
270	status = "okay";
271};
272
273&hdmi_tx {
274	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
275	resets = <&reset RESET_HDMITX_CAPB3>,
276		 <&reset RESET_HDMI_SYSTEM_RESET>,
277		 <&reset RESET_HDMI_TX>;
278	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
279	clocks = <&clkc CLKID_HDMI_PCLK>,
280		 <&clkc CLKID_CLK81>,
281		 <&clkc CLKID_GCLK_VENCI_INT0>;
282	clock-names = "isfr", "iahb", "venci";
283};
284
285&sysctrl {
286	clkc: clock-controller {
287		compatible = "amlogic,gxl-clkc";
288		#clock-cells = <1>;
289		clocks = <&xtal>;
290		clock-names = "xtal";
291	};
292};
293
294&i2c_A {
295	clocks = <&clkc CLKID_I2C>;
296};
297
298&i2c_AO {
299	clocks = <&clkc CLKID_AO_I2C>;
300};
301
302&i2c_B {
303	clocks = <&clkc CLKID_I2C>;
304};
305
306&i2c_C {
307	clocks = <&clkc CLKID_I2C>;
308};
309
310&periphs {
311	pinctrl_periphs: pinctrl@4b0 {
312		compatible = "amlogic,meson-gxl-periphs-pinctrl";
313		#address-cells = <2>;
314		#size-cells = <2>;
315		ranges;
316
317		gpio: bank@4b0 {
318			reg = <0x0 0x004b0 0x0 0x28>,
319			      <0x0 0x004e8 0x0 0x14>,
320			      <0x0 0x00520 0x0 0x14>,
321			      <0x0 0x00430 0x0 0x40>;
322			reg-names = "mux", "pull", "pull-enable", "gpio";
323			gpio-controller;
324			#gpio-cells = <2>;
325			gpio-ranges = <&pinctrl_periphs 0 0 100>;
326		};
327
328		emmc_pins: emmc {
329			mux-0 {
330				groups = "emmc_nand_d07",
331				       "emmc_cmd";
332				function = "emmc";
333				bias-pull-up;
334			};
335
336			mux-1 {
337				groups = "emmc_clk";
338				function = "emmc";
339				bias-disable;
340			};
341		};
342
343		emmc_ds_pins: emmc-ds {
344			mux {
345				groups = "emmc_ds";
346				function = "emmc";
347				bias-pull-down;
348			};
349		};
350
351		emmc_clk_gate_pins: emmc_clk_gate {
352			mux {
353				groups = "BOOT_8";
354				function = "gpio_periphs";
355				bias-pull-down;
356			};
357		};
358
359		nor_pins: nor {
360			mux {
361				groups = "nor_d",
362				       "nor_q",
363				       "nor_c",
364				       "nor_cs";
365				function = "nor";
366				bias-disable;
367			};
368		};
369
370		spi_pins: spi-pins {
371			mux {
372				groups = "spi_miso",
373					"spi_mosi",
374					"spi_sclk";
375				function = "spi";
376				bias-disable;
377			};
378		};
379
380		spi_ss0_pins: spi-ss0 {
381			mux {
382				groups = "spi_ss0";
383				function = "spi";
384				bias-disable;
385			};
386		};
387
388		sdcard_pins: sdcard {
389			mux-0 {
390				groups = "sdcard_d0",
391				       "sdcard_d1",
392				       "sdcard_d2",
393				       "sdcard_d3",
394				       "sdcard_cmd";
395				function = "sdcard";
396				bias-pull-up;
397			};
398
399			mux-1 {
400				groups = "sdcard_clk";
401				function = "sdcard";
402				bias-disable;
403			};
404		};
405
406		sdcard_clk_gate_pins: sdcard_clk_gate {
407			mux {
408				groups = "CARD_2";
409				function = "gpio_periphs";
410				bias-pull-down;
411			};
412		};
413
414		sdio_pins: sdio {
415			mux-0 {
416				groups = "sdio_d0",
417				       "sdio_d1",
418				       "sdio_d2",
419				       "sdio_d3",
420				       "sdio_cmd";
421				function = "sdio";
422				bias-pull-up;
423			};
424
425			mux-1 {
426				groups = "sdio_clk";
427				function = "sdio";
428				bias-disable;
429			};
430		};
431
432		sdio_clk_gate_pins: sdio_clk_gate {
433			mux {
434				groups = "GPIOX_4";
435				function = "gpio_periphs";
436				bias-pull-down;
437			};
438		};
439
440		sdio_irq_pins: sdio_irq {
441			mux {
442				groups = "sdio_irq";
443				function = "sdio";
444				bias-disable;
445			};
446		};
447
448		uart_a_pins: uart_a {
449			mux {
450				groups = "uart_tx_a",
451				       "uart_rx_a";
452				function = "uart_a";
453				bias-disable;
454			};
455		};
456
457		uart_a_cts_rts_pins: uart_a_cts_rts {
458			mux {
459				groups = "uart_cts_a",
460				       "uart_rts_a";
461				function = "uart_a";
462				bias-disable;
463			};
464		};
465
466		uart_b_pins: uart_b {
467			mux {
468				groups = "uart_tx_b",
469				       "uart_rx_b";
470				function = "uart_b";
471				bias-disable;
472			};
473		};
474
475		uart_b_cts_rts_pins: uart_b_cts_rts {
476			mux {
477				groups = "uart_cts_b",
478				       "uart_rts_b";
479				function = "uart_b";
480				bias-disable;
481			};
482		};
483
484		uart_c_pins: uart_c {
485			mux {
486				groups = "uart_tx_c",
487				       "uart_rx_c";
488				function = "uart_c";
489				bias-disable;
490			};
491		};
492
493		uart_c_cts_rts_pins: uart_c_cts_rts {
494			mux {
495				groups = "uart_cts_c",
496				       "uart_rts_c";
497				function = "uart_c";
498				bias-disable;
499			};
500		};
501
502		i2c_a_pins: i2c_a {
503			mux {
504				groups = "i2c_sck_a",
505				     "i2c_sda_a";
506				function = "i2c_a";
507				bias-disable;
508			};
509		};
510
511		i2c_b_pins: i2c_b {
512			mux {
513				groups = "i2c_sck_b",
514				      "i2c_sda_b";
515				function = "i2c_b";
516				bias-disable;
517			};
518		};
519
520		i2c_c_pins: i2c_c {
521			mux {
522				groups = "i2c_sck_c",
523				      "i2c_sda_c";
524				function = "i2c_c";
525				bias-disable;
526			};
527		};
528
529		eth_pins: eth_c {
530			mux {
531				groups = "eth_mdio",
532				       "eth_mdc",
533				       "eth_clk_rx_clk",
534				       "eth_rx_dv",
535				       "eth_rxd0",
536				       "eth_rxd1",
537				       "eth_rxd2",
538				       "eth_rxd3",
539				       "eth_rgmii_tx_clk",
540				       "eth_tx_en",
541				       "eth_txd0",
542				       "eth_txd1",
543				       "eth_txd2",
544				       "eth_txd3";
545				function = "eth";
546				bias-disable;
547			};
548		};
549
550		eth_link_led_pins: eth_link_led {
551			mux {
552				groups = "eth_link_led";
553				function = "eth_led";
554				bias-disable;
555			};
556		};
557
558		eth_act_led_pins: eth_act_led {
559			mux {
560				groups = "eth_act_led";
561				function = "eth_led";
562			};
563		};
564
565		pwm_a_pins: pwm_a {
566			mux {
567				groups = "pwm_a";
568				function = "pwm_a";
569				bias-disable;
570			};
571		};
572
573		pwm_b_pins: pwm_b {
574			mux {
575				groups = "pwm_b";
576				function = "pwm_b";
577				bias-disable;
578			};
579		};
580
581		pwm_c_pins: pwm_c {
582			mux {
583				groups = "pwm_c";
584				function = "pwm_c";
585				bias-disable;
586			};
587		};
588
589		pwm_d_pins: pwm_d {
590			mux {
591				groups = "pwm_d";
592				function = "pwm_d";
593				bias-disable;
594			};
595		};
596
597		pwm_e_pins: pwm_e {
598			mux {
599				groups = "pwm_e";
600				function = "pwm_e";
601				bias-disable;
602			};
603		};
604
605		pwm_f_clk_pins: pwm_f_clk {
606			mux {
607				groups = "pwm_f_clk";
608				function = "pwm_f";
609				bias-disable;
610			};
611		};
612
613		pwm_f_x_pins: pwm_f_x {
614			mux {
615				groups = "pwm_f_x";
616				function = "pwm_f";
617				bias-disable;
618			};
619		};
620
621		hdmi_hpd_pins: hdmi_hpd {
622			mux {
623				groups = "hdmi_hpd";
624				function = "hdmi_hpd";
625				bias-disable;
626			};
627		};
628
629		hdmi_i2c_pins: hdmi_i2c {
630			mux {
631				groups = "hdmi_sda", "hdmi_scl";
632				function = "hdmi_i2c";
633				bias-disable;
634			};
635		};
636
637		i2s_am_clk_pins: i2s_am_clk {
638			mux {
639				groups = "i2s_am_clk";
640				function = "i2s_out";
641				bias-disable;
642			};
643		};
644
645		i2s_out_ao_clk_pins: i2s_out_ao_clk {
646			mux {
647				groups = "i2s_out_ao_clk";
648				function = "i2s_out";
649				bias-disable;
650			};
651		};
652
653		i2s_out_lr_clk_pins: i2s_out_lr_clk {
654			mux {
655				groups = "i2s_out_lr_clk";
656				function = "i2s_out";
657				bias-disable;
658			};
659		};
660
661		i2s_out_ch01_pins: i2s_out_ch01 {
662			mux {
663				groups = "i2s_out_ch01";
664				function = "i2s_out";
665				bias-disable;
666			};
667		};
668		i2sout_ch23_z_pins: i2sout_ch23_z {
669			mux {
670				groups = "i2sout_ch23_z";
671				function = "i2s_out";
672				bias-disable;
673			};
674		};
675
676		i2sout_ch45_z_pins: i2sout_ch45_z {
677			mux {
678				groups = "i2sout_ch45_z";
679				function = "i2s_out";
680				bias-disable;
681			};
682		};
683
684		i2sout_ch67_z_pins: i2sout_ch67_z {
685			mux {
686				groups = "i2sout_ch67_z";
687				function = "i2s_out";
688				bias-disable;
689			};
690		};
691
692		spdif_out_h_pins: spdif_out_ao_h {
693			mux {
694				groups = "spdif_out_h";
695				function = "spdif_out";
696				bias-disable;
697			};
698		};
699	};
700
701	eth-phy-mux {
702		compatible = "mdio-mux-mmioreg", "mdio-mux";
703		#address-cells = <1>;
704		#size-cells = <0>;
705		reg = <0x0 0x55c 0x0 0x4>;
706		mux-mask = <0xffffffff>;
707		mdio-parent-bus = <&mdio0>;
708
709		internal_mdio: mdio@e40908ff {
710			reg = <0xe40908ff>;
711			#address-cells = <1>;
712			#size-cells = <0>;
713
714			internal_phy: ethernet-phy@8 {
715				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
716				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
717				reg = <8>;
718				max-speed = <100>;
719			};
720		};
721
722		external_mdio: mdio@2009087f {
723			reg = <0x2009087f>;
724			#address-cells = <1>;
725			#size-cells = <0>;
726		};
727	};
728};
729
730&pwrc_vpu {
731	resets = <&reset RESET_VIU>,
732		 <&reset RESET_VENC>,
733		 <&reset RESET_VCBUS>,
734		 <&reset RESET_BT656>,
735		 <&reset RESET_DVIN_RESET>,
736		 <&reset RESET_RDMA>,
737		 <&reset RESET_VENCI>,
738		 <&reset RESET_VENCP>,
739		 <&reset RESET_VDAC>,
740		 <&reset RESET_VDI6>,
741		 <&reset RESET_VENCL>,
742		 <&reset RESET_VID_LOCK>;
743	clocks = <&clkc CLKID_VPU>,
744	         <&clkc CLKID_VAPB>;
745	clock-names = "vpu", "vapb";
746	/*
747	 * VPU clocking is provided by two identical clock paths
748	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
749	 * free mux to safely change frequency while running.
750	 * Same for VAPB but with a final gate after the glitch free mux.
751	 */
752	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
753			  <&clkc CLKID_VPU_0>,
754			  <&clkc CLKID_VPU>, /* Glitch free mux */
755			  <&clkc CLKID_VAPB_0_SEL>,
756			  <&clkc CLKID_VAPB_0>,
757			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
758	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
759				 <0>, /* Do Nothing */
760				 <&clkc CLKID_VPU_0>,
761				 <&clkc CLKID_FCLK_DIV4>,
762				 <0>, /* Do Nothing */
763				 <&clkc CLKID_VAPB_0>;
764	assigned-clock-rates = <0>, /* Do Nothing */
765			       <666666666>,
766			       <0>, /* Do Nothing */
767			       <0>, /* Do Nothing */
768			       <250000000>,
769			       <0>; /* Do Nothing */
770};
771
772&saradc {
773	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
774	clocks = <&xtal>,
775		 <&clkc CLKID_SAR_ADC>,
776		 <&clkc CLKID_SAR_ADC_CLK>,
777		 <&clkc CLKID_SAR_ADC_SEL>;
778	clock-names = "clkin", "core", "adc_clk", "adc_sel";
779};
780
781&sd_emmc_a {
782	clocks = <&clkc CLKID_SD_EMMC_A>,
783		 <&clkc CLKID_SD_EMMC_A_CLK0>,
784		 <&clkc CLKID_FCLK_DIV2>;
785	clock-names = "core", "clkin0", "clkin1";
786	resets = <&reset RESET_SD_EMMC_A>;
787};
788
789&sd_emmc_b {
790	clocks = <&clkc CLKID_SD_EMMC_B>,
791		 <&clkc CLKID_SD_EMMC_B_CLK0>,
792		 <&clkc CLKID_FCLK_DIV2>;
793	clock-names = "core", "clkin0", "clkin1";
794	resets = <&reset RESET_SD_EMMC_B>;
795};
796
797&sd_emmc_c {
798	clocks = <&clkc CLKID_SD_EMMC_C>,
799		 <&clkc CLKID_SD_EMMC_C_CLK0>,
800		 <&clkc CLKID_FCLK_DIV2>;
801	clock-names = "core", "clkin0", "clkin1";
802	resets = <&reset RESET_SD_EMMC_C>;
803};
804
805&simplefb_hdmi {
806	clocks = <&clkc CLKID_HDMI_PCLK>,
807		 <&clkc CLKID_CLK81>,
808		 <&clkc CLKID_GCLK_VENCI_INT0>;
809};
810
811&spicc {
812	clocks = <&clkc CLKID_SPICC>;
813	clock-names = "core";
814	resets = <&reset RESET_PERIPHS_SPICC>;
815	num-cs = <1>;
816};
817
818&spifc {
819	clocks = <&clkc CLKID_SPI>;
820};
821
822&uart_A {
823	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
824	clock-names = "xtal", "pclk", "baud";
825};
826
827&uart_AO {
828	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
829	clock-names = "xtal", "pclk", "baud";
830};
831
832&uart_AO_B {
833	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
834	clock-names = "xtal", "pclk", "baud";
835};
836
837&uart_B {
838	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
839	clock-names = "xtal", "pclk", "baud";
840};
841
842&uart_C {
843	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
844	clock-names = "xtal", "pclk", "baud";
845};
846
847&vpu {
848	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
849	power-domains = <&pwrc_vpu>;
850};
851