xref: /linux/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi (revision dd5b2498d845f925904cb2afabb6ba11bfc317c5) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Andreas Färber
4 */
5
6#include "meson-gx.dtsi"
7#include <dt-bindings/gpio/meson-gxbb-gpio.h>
8#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
9#include <dt-bindings/clock/gxbb-clkc.h>
10#include <dt-bindings/clock/gxbb-aoclkc.h>
11#include <dt-bindings/reset/gxbb-aoclkc.h>
12
13/ {
14	compatible = "amlogic,meson-gxbb";
15
16	soc {
17		usb0_phy: phy@c0000000 {
18			compatible = "amlogic,meson-gxbb-usb2-phy";
19			#phy-cells = <0>;
20			reg = <0x0 0xc0000000 0x0 0x20>;
21			resets = <&reset RESET_USB_OTG>;
22			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
23			clock-names = "usb_general", "usb";
24			status = "disabled";
25		};
26
27		usb1_phy: phy@c0000020 {
28			compatible = "amlogic,meson-gxbb-usb2-phy";
29			#phy-cells = <0>;
30			reg = <0x0 0xc0000020 0x0 0x20>;
31			resets = <&reset RESET_USB_OTG>;
32			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
33			clock-names = "usb_general", "usb";
34			status = "disabled";
35		};
36
37		usb0: usb@c9000000 {
38			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
39			reg = <0x0 0xc9000000 0x0 0x40000>;
40			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
41			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
42			clock-names = "otg";
43			phys = <&usb0_phy>;
44			phy-names = "usb2-phy";
45			dr_mode = "host";
46			status = "disabled";
47		};
48
49		usb1: usb@c9100000 {
50			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
51			reg = <0x0 0xc9100000 0x0 0x40000>;
52			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
53			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
54			clock-names = "otg";
55			phys = <&usb1_phy>;
56			phy-names = "usb2-phy";
57			dr_mode = "host";
58			status = "disabled";
59		};
60	};
61};
62
63&aobus {
64	pinctrl_aobus: pinctrl@14 {
65		compatible = "amlogic,meson-gxbb-aobus-pinctrl";
66		#address-cells = <2>;
67		#size-cells = <2>;
68		ranges;
69
70		gpio_ao: bank@14 {
71			reg = <0x0 0x00014 0x0 0x8>,
72			      <0x0 0x0002c 0x0 0x4>,
73			      <0x0 0x00024 0x0 0x8>;
74			reg-names = "mux", "pull", "gpio";
75			gpio-controller;
76			#gpio-cells = <2>;
77			gpio-ranges = <&pinctrl_aobus 0 0 14>;
78		};
79
80		uart_ao_a_pins: uart_ao_a {
81			mux {
82				groups = "uart_tx_ao_a", "uart_rx_ao_a";
83				function = "uart_ao";
84				bias-disable;
85			};
86		};
87
88		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
89			mux {
90				groups = "uart_cts_ao_a",
91				       "uart_rts_ao_a";
92				function = "uart_ao";
93				bias-disable;
94			};
95		};
96
97		uart_ao_b_pins: uart_ao_b {
98			mux {
99				groups = "uart_tx_ao_b", "uart_rx_ao_b";
100				function = "uart_ao_b";
101				bias-disable;
102			};
103		};
104
105		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
106			mux {
107				groups = "uart_cts_ao_b",
108				       "uart_rts_ao_b";
109				function = "uart_ao_b";
110				bias-disable;
111			};
112		};
113
114		remote_input_ao_pins: remote_input_ao {
115			mux {
116				groups = "remote_input_ao";
117				function = "remote_input_ao";
118				bias-disable;
119			};
120		};
121
122		i2c_ao_pins: i2c_ao {
123			mux {
124				groups = "i2c_sck_ao",
125				       "i2c_sda_ao";
126				function = "i2c_ao";
127				bias-disable;
128			};
129		};
130
131		pwm_ao_a_3_pins: pwm_ao_a_3 {
132			mux {
133				groups = "pwm_ao_a_3";
134				function = "pwm_ao_a_3";
135				bias-disable;
136			};
137		};
138
139		pwm_ao_a_6_pins: pwm_ao_a_6 {
140			mux {
141				groups = "pwm_ao_a_6";
142				function = "pwm_ao_a_6";
143				bias-disable;
144			};
145		};
146
147		pwm_ao_a_12_pins: pwm_ao_a_12 {
148			mux {
149				groups = "pwm_ao_a_12";
150				function = "pwm_ao_a_12";
151				bias-disable;
152			};
153		};
154
155		pwm_ao_b_pins: pwm_ao_b {
156			mux {
157				groups = "pwm_ao_b";
158				function = "pwm_ao_b";
159				bias-disable;
160			};
161		};
162
163		i2s_am_clk_pins: i2s_am_clk {
164			mux {
165				groups = "i2s_am_clk";
166				function = "i2s_out_ao";
167				bias-disable;
168			};
169		};
170
171		i2s_out_ao_clk_pins: i2s_out_ao_clk {
172			mux {
173				groups = "i2s_out_ao_clk";
174				function = "i2s_out_ao";
175				bias-disable;
176			};
177		};
178
179		i2s_out_lr_clk_pins: i2s_out_lr_clk {
180			mux {
181				groups = "i2s_out_lr_clk";
182				function = "i2s_out_ao";
183				bias-disable;
184			};
185		};
186
187		i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
188			mux {
189				groups = "i2s_out_ch01_ao";
190				function = "i2s_out_ao";
191				bias-disable;
192			};
193		};
194
195		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
196			mux {
197				groups = "i2s_out_ch23_ao";
198				function = "i2s_out_ao";
199				bias-disable;
200			};
201		};
202
203		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
204			mux {
205				groups = "i2s_out_ch45_ao";
206				function = "i2s_out_ao";
207				bias-disable;
208			};
209		};
210
211		spdif_out_ao_6_pins: spdif_out_ao_6 {
212			mux {
213				groups = "spdif_out_ao_6";
214				function = "spdif_out_ao";
215			};
216		};
217
218		spdif_out_ao_13_pins: spdif_out_ao_13 {
219			mux {
220				groups = "spdif_out_ao_13";
221				function = "spdif_out_ao";
222				bias-disable;
223			};
224		};
225
226		ao_cec_pins: ao_cec {
227			mux {
228				groups = "ao_cec";
229				function = "cec_ao";
230				bias-disable;
231			};
232		};
233
234		ee_cec_pins: ee_cec {
235			mux {
236				groups = "ee_cec";
237				function = "cec_ao";
238				bias-disable;
239			};
240		};
241	};
242};
243
244&apb {
245	mali: gpu@c0000 {
246		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
247		reg = <0x0 0xc0000 0x0 0x40000>;
248		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
249			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
250			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
251			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
252			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
253			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
254			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
255			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
256			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
257			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
258		interrupt-names = "gp", "gpmmu", "pp", "pmu",
259			"pp0", "ppmmu0", "pp1", "ppmmu1",
260			"pp2", "ppmmu2";
261		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
262		clock-names = "bus", "core";
263
264		/*
265		 * Mali clocking is provided by two identical clock paths
266		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
267		 * free mux to safely change frequency while running.
268		 */
269		assigned-clocks = <&clkc CLKID_GP0_PLL>,
270				  <&clkc CLKID_MALI_0_SEL>,
271				  <&clkc CLKID_MALI_0>,
272				  <&clkc CLKID_MALI>; /* Glitch free mux */
273		assigned-clock-parents = <0>, /* Do Nothing */
274					 <&clkc CLKID_GP0_PLL>,
275					 <0>, /* Do Nothing */
276					 <&clkc CLKID_MALI_0>;
277		assigned-clock-rates = <744000000>,
278				       <0>, /* Do Nothing */
279				       <744000000>,
280				       <0>; /* Do Nothing */
281	};
282};
283
284&cbus {
285	spifc: spi@8c80 {
286		compatible = "amlogic,meson-gxbb-spifc";
287		reg = <0x0 0x08c80 0x0 0x80>;
288		#address-cells = <1>;
289		#size-cells = <0>;
290		clocks = <&clkc CLKID_SPI>;
291		status = "disabled";
292	};
293};
294
295&cec_AO {
296	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
297	clock-names = "core";
298};
299
300&clkc_AO {
301	compatible = "amlogic,meson-gxbb-aoclkc", "amlogic,meson-gx-aoclkc";
302	clocks = <&xtal>, <&clkc CLKID_CLK81>;
303	clock-names = "xtal", "mpeg-clk";
304};
305
306&efuse {
307	clocks = <&clkc CLKID_EFUSE>;
308};
309
310&ethmac {
311	clocks = <&clkc CLKID_ETH>,
312		 <&clkc CLKID_FCLK_DIV2>,
313		 <&clkc CLKID_MPLL2>;
314	clock-names = "stmmaceth", "clkin0", "clkin1";
315};
316
317&gpio_intc {
318	compatible = "amlogic,meson-gpio-intc",
319		     "amlogic,meson-gxbb-gpio-intc";
320	status = "okay";
321};
322
323&hdmi_tx {
324	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
325	resets = <&reset RESET_HDMITX_CAPB3>,
326		 <&reset RESET_HDMI_SYSTEM_RESET>,
327		 <&reset RESET_HDMI_TX>;
328	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
329	clocks = <&clkc CLKID_HDMI_PCLK>,
330		 <&clkc CLKID_CLK81>,
331		 <&clkc CLKID_GCLK_VENCI_INT0>;
332	clock-names = "isfr", "iahb", "venci";
333};
334
335&sysctrl {
336	clkc: clock-controller {
337		compatible = "amlogic,gxbb-clkc";
338		#clock-cells = <1>;
339		clocks = <&xtal>;
340		clock-names = "xtal";
341	};
342};
343
344&hwrng {
345	clocks = <&clkc CLKID_RNG0>;
346	clock-names = "core";
347};
348
349&i2c_A {
350	clocks = <&clkc CLKID_I2C>;
351};
352
353&i2c_AO {
354	clocks = <&clkc CLKID_AO_I2C>;
355};
356
357&i2c_B {
358	clocks = <&clkc CLKID_I2C>;
359};
360
361&i2c_C {
362	clocks = <&clkc CLKID_I2C>;
363};
364
365&periphs {
366	pinctrl_periphs: pinctrl@4b0 {
367		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
368		#address-cells = <2>;
369		#size-cells = <2>;
370		ranges;
371
372		gpio: bank@4b0 {
373			reg = <0x0 0x004b0 0x0 0x28>,
374			      <0x0 0x004e8 0x0 0x14>,
375			      <0x0 0x00520 0x0 0x14>,
376			      <0x0 0x00430 0x0 0x40>;
377			reg-names = "mux", "pull", "pull-enable", "gpio";
378			gpio-controller;
379			#gpio-cells = <2>;
380			gpio-ranges = <&pinctrl_periphs 0 0 119>;
381		};
382
383		emmc_pins: emmc {
384			mux {
385				groups = "emmc_nand_d07",
386				       "emmc_cmd",
387				       "emmc_clk";
388				function = "emmc";
389				bias-disable;
390			};
391		};
392
393		emmc_ds_pins: emmc-ds {
394			mux {
395				groups = "emmc_ds";
396				function = "emmc";
397				bias-disable;
398			};
399		};
400
401		emmc_clk_gate_pins: emmc_clk_gate {
402			mux {
403				groups = "BOOT_8";
404				function = "gpio_periphs";
405				bias-pull-down;
406			};
407		};
408
409		nor_pins: nor {
410			mux {
411				groups = "nor_d",
412				       "nor_q",
413				       "nor_c",
414				       "nor_cs";
415				function = "nor";
416				bias-disable;
417			};
418		};
419
420		spi_pins: spi-pins {
421			mux {
422				groups = "spi_miso",
423					"spi_mosi",
424					"spi_sclk";
425				function = "spi";
426				bias-disable;
427			};
428		};
429
430		spi_ss0_pins: spi-ss0 {
431			mux {
432				groups = "spi_ss0";
433				function = "spi";
434				bias-disable;
435			};
436		};
437
438		sdcard_pins: sdcard {
439			mux {
440				groups = "sdcard_d0",
441				       "sdcard_d1",
442				       "sdcard_d2",
443				       "sdcard_d3",
444				       "sdcard_cmd",
445				       "sdcard_clk";
446				function = "sdcard";
447				bias-disable;
448			};
449		};
450
451		sdcard_clk_gate_pins: sdcard_clk_gate {
452			mux {
453				groups = "CARD_2";
454				function = "gpio_periphs";
455				bias-pull-down;
456			};
457		};
458
459		sdio_pins: sdio {
460			mux {
461				groups = "sdio_d0",
462				       "sdio_d1",
463				       "sdio_d2",
464				       "sdio_d3",
465				       "sdio_cmd",
466				       "sdio_clk";
467				function = "sdio";
468				bias-disable;
469			};
470		};
471
472		sdio_clk_gate_pins: sdio_clk_gate {
473			mux {
474				groups = "GPIOX_4";
475				function = "gpio_periphs";
476				bias-pull-down;
477			};
478		};
479
480		sdio_irq_pins: sdio_irq {
481			mux {
482				groups = "sdio_irq";
483				function = "sdio";
484				bias-disable;
485			};
486		};
487
488		uart_a_pins: uart_a {
489			mux {
490				groups = "uart_tx_a",
491				       "uart_rx_a";
492				function = "uart_a";
493				bias-disable;
494			};
495		};
496
497		uart_a_cts_rts_pins: uart_a_cts_rts {
498			mux {
499				groups = "uart_cts_a",
500				       "uart_rts_a";
501				function = "uart_a";
502				bias-disable;
503			};
504		};
505
506		uart_b_pins: uart_b {
507			mux {
508				groups = "uart_tx_b",
509				       "uart_rx_b";
510				function = "uart_b";
511				bias-disable;
512			};
513		};
514
515		uart_b_cts_rts_pins: uart_b_cts_rts {
516			mux {
517				groups = "uart_cts_b",
518				       "uart_rts_b";
519				function = "uart_b";
520				bias-disable;
521			};
522		};
523
524		uart_c_pins: uart_c {
525			mux {
526				groups = "uart_tx_c",
527				       "uart_rx_c";
528				function = "uart_c";
529				bias-disable;
530			};
531		};
532
533		uart_c_cts_rts_pins: uart_c_cts_rts {
534			mux {
535				groups = "uart_cts_c",
536				       "uart_rts_c";
537				function = "uart_c";
538				bias-disable;
539			};
540		};
541
542		i2c_a_pins: i2c_a {
543			mux {
544				groups = "i2c_sck_a",
545				       "i2c_sda_a";
546				function = "i2c_a";
547				bias-disable;
548			};
549		};
550
551		i2c_b_pins: i2c_b {
552			mux {
553				groups = "i2c_sck_b",
554				       "i2c_sda_b";
555				function = "i2c_b";
556				bias-disable;
557			};
558		};
559
560		i2c_c_pins: i2c_c {
561			mux {
562				groups = "i2c_sck_c",
563				       "i2c_sda_c";
564				function = "i2c_c";
565				bias-disable;
566			};
567		};
568
569		eth_rgmii_pins: eth-rgmii {
570			mux {
571				groups = "eth_mdio",
572				       "eth_mdc",
573				       "eth_clk_rx_clk",
574				       "eth_rx_dv",
575				       "eth_rxd0",
576				       "eth_rxd1",
577				       "eth_rxd2",
578				       "eth_rxd3",
579				       "eth_rgmii_tx_clk",
580				       "eth_tx_en",
581				       "eth_txd0",
582				       "eth_txd1",
583				       "eth_txd2",
584				       "eth_txd3";
585				function = "eth";
586				bias-disable;
587			};
588		};
589
590		eth_rmii_pins: eth-rmii {
591			mux {
592				groups = "eth_mdio",
593				       "eth_mdc",
594				       "eth_clk_rx_clk",
595				       "eth_rx_dv",
596				       "eth_rxd0",
597				       "eth_rxd1",
598				       "eth_tx_en",
599				       "eth_txd0",
600				       "eth_txd1";
601				function = "eth";
602				bias-disable;
603			};
604		};
605
606		pwm_a_x_pins: pwm_a_x {
607			mux {
608				groups = "pwm_a_x";
609				function = "pwm_a_x";
610				bias-disable;
611			};
612		};
613
614		pwm_a_y_pins: pwm_a_y {
615			mux {
616				groups = "pwm_a_y";
617				function = "pwm_a_y";
618				bias-disable;
619			};
620		};
621
622		pwm_b_pins: pwm_b {
623			mux {
624				groups = "pwm_b";
625				function = "pwm_b";
626				bias-disable;
627			};
628		};
629
630		pwm_d_pins: pwm_d {
631			mux {
632				groups = "pwm_d";
633				function = "pwm_d";
634				bias-disable;
635			};
636		};
637
638		pwm_e_pins: pwm_e {
639			mux {
640				groups = "pwm_e";
641				function = "pwm_e";
642				bias-disable;
643			};
644		};
645
646		pwm_f_x_pins: pwm_f_x {
647			mux {
648				groups = "pwm_f_x";
649				function = "pwm_f_x";
650				bias-disable;
651			};
652		};
653
654		pwm_f_y_pins: pwm_f_y {
655			mux {
656				groups = "pwm_f_y";
657				function = "pwm_f_y";
658				bias-disable;
659			};
660		};
661
662		hdmi_hpd_pins: hdmi_hpd {
663			mux {
664				groups = "hdmi_hpd";
665				function = "hdmi_hpd";
666				bias-disable;
667			};
668		};
669
670		hdmi_i2c_pins: hdmi_i2c {
671			mux {
672				groups = "hdmi_sda", "hdmi_scl";
673				function = "hdmi_i2c";
674				bias-disable;
675			};
676		};
677
678		i2sout_ch23_y_pins: i2sout_ch23_y {
679			mux {
680				groups = "i2sout_ch23_y";
681				function = "i2s_out";
682				bias-disable;
683			};
684		};
685
686		i2sout_ch45_y_pins: i2sout_ch45_y {
687			mux {
688				groups = "i2sout_ch45_y";
689				function = "i2s_out";
690				bias-disable;
691			};
692		};
693
694		i2sout_ch67_y_pins: i2sout_ch67_y {
695			mux {
696				groups = "i2sout_ch67_y";
697				function = "i2s_out";
698				bias-disable;
699			};
700		};
701
702		spdif_out_y_pins: spdif_out_y {
703			mux {
704				groups = "spdif_out_y";
705				function = "spdif_out";
706				bias-disable;
707			};
708		};
709	};
710};
711
712&pwrc_vpu {
713	resets = <&reset RESET_VIU>,
714		 <&reset RESET_VENC>,
715		 <&reset RESET_VCBUS>,
716		 <&reset RESET_BT656>,
717		 <&reset RESET_DVIN_RESET>,
718		 <&reset RESET_RDMA>,
719		 <&reset RESET_VENCI>,
720		 <&reset RESET_VENCP>,
721		 <&reset RESET_VDAC>,
722		 <&reset RESET_VDI6>,
723		 <&reset RESET_VENCL>,
724		 <&reset RESET_VID_LOCK>;
725	clocks = <&clkc CLKID_VPU>,
726	         <&clkc CLKID_VAPB>;
727	clock-names = "vpu", "vapb";
728	/*
729	 * VPU clocking is provided by two identical clock paths
730	 * VPU_0 and VPU_1 muxed to a single clock by a glitch
731	 * free mux to safely change frequency while running.
732	 * Same for VAPB but with a final gate after the glitch free mux.
733	 */
734	assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
735			  <&clkc CLKID_VPU_0>,
736			  <&clkc CLKID_VPU>, /* Glitch free mux */
737			  <&clkc CLKID_VAPB_0_SEL>,
738			  <&clkc CLKID_VAPB_0>,
739			  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
740	assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
741				 <0>, /* Do Nothing */
742				 <&clkc CLKID_VPU_0>,
743				 <&clkc CLKID_FCLK_DIV4>,
744				 <0>, /* Do Nothing */
745				 <&clkc CLKID_VAPB_0>;
746	assigned-clock-rates = <0>, /* Do Nothing */
747			       <666666666>,
748			       <0>, /* Do Nothing */
749			       <0>, /* Do Nothing */
750			       <250000000>,
751			       <0>; /* Do Nothing */
752};
753
754&saradc {
755	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
756	clocks = <&xtal>,
757		 <&clkc CLKID_SAR_ADC>,
758		 <&clkc CLKID_SAR_ADC_CLK>,
759		 <&clkc CLKID_SAR_ADC_SEL>;
760	clock-names = "clkin", "core", "adc_clk", "adc_sel";
761};
762
763&sd_emmc_a {
764	clocks = <&clkc CLKID_SD_EMMC_A>,
765		 <&clkc CLKID_SD_EMMC_A_CLK0>,
766		 <&clkc CLKID_FCLK_DIV2>;
767	clock-names = "core", "clkin0", "clkin1";
768	resets = <&reset RESET_SD_EMMC_A>;
769};
770
771&sd_emmc_b {
772	clocks = <&clkc CLKID_SD_EMMC_B>,
773		 <&clkc CLKID_SD_EMMC_B_CLK0>,
774		 <&clkc CLKID_FCLK_DIV2>;
775	clock-names = "core", "clkin0", "clkin1";
776	resets = <&reset RESET_SD_EMMC_B>;
777};
778
779&sd_emmc_c {
780	clocks = <&clkc CLKID_SD_EMMC_C>,
781		 <&clkc CLKID_SD_EMMC_C_CLK0>,
782		 <&clkc CLKID_FCLK_DIV2>;
783	clock-names = "core", "clkin0", "clkin1";
784	resets = <&reset RESET_SD_EMMC_C>;
785};
786
787&simplefb_hdmi {
788	clocks = <&clkc CLKID_HDMI_PCLK>,
789		 <&clkc CLKID_CLK81>,
790		 <&clkc CLKID_GCLK_VENCI_INT0>;
791};
792
793&spicc {
794	clocks = <&clkc CLKID_SPICC>;
795	clock-names = "core";
796	resets = <&reset RESET_PERIPHS_SPICC>;
797	num-cs = <1>;
798};
799
800&spifc {
801	clocks = <&clkc CLKID_SPI>;
802};
803
804&uart_A {
805	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
806	clock-names = "xtal", "pclk", "baud";
807};
808
809&uart_AO {
810	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
811	clock-names = "xtal", "pclk", "baud";
812};
813
814&uart_AO_B {
815	clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
816	clock-names = "xtal", "pclk", "baud";
817};
818
819&uart_B {
820	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
821	clock-names = "xtal", "pclk", "baud";
822};
823
824&uart_C {
825	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
826	clock-names = "xtal", "pclk", "baud";
827};
828
829&vpu {
830	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
831	power-domains = <&pwrc_vpu>;
832};
833