1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Andreas Färber 4 * 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Neil Armstrong <narmstrong@baylibre.com> 7 * 8 * Copyright (c) 2016 Endless Computers, Inc. 9 * Author: Carlo Caione <carlo@endlessm.com> 10 */ 11 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 reserved-memory { 22 #address-cells = <2>; 23 #size-cells = <2>; 24 ranges; 25 26 /* 16 MiB reserved for Hardware ROM Firmware */ 27 hwrom_reserved: hwrom@0 { 28 reg = <0x0 0x0 0x0 0x1000000>; 29 no-map; 30 }; 31 32 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 33 secmon_reserved: secmon@10000000 { 34 reg = <0x0 0x10000000 0x0 0x200000>; 35 no-map; 36 }; 37 38 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 39 secmon_reserved_alt: secmon@5000000 { 40 reg = <0x0 0x05000000 0x0 0x300000>; 41 no-map; 42 }; 43 44 linux,cma { 45 compatible = "shared-dma-pool"; 46 reusable; 47 size = <0x0 0x10000000>; 48 alignment = <0x0 0x400000>; 49 linux,cma-default; 50 }; 51 }; 52 53 chosen { 54 #address-cells = <2>; 55 #size-cells = <2>; 56 ranges; 57 58 simplefb_cvbs: framebuffer-cvbs { 59 compatible = "amlogic,simple-framebuffer", 60 "simple-framebuffer"; 61 amlogic,pipeline = "vpu-cvbs"; 62 power-domains = <&pwrc_vpu>; 63 status = "disabled"; 64 }; 65 66 simplefb_hdmi: framebuffer-hdmi { 67 compatible = "amlogic,simple-framebuffer", 68 "simple-framebuffer"; 69 amlogic,pipeline = "vpu-hdmi"; 70 power-domains = <&pwrc_vpu>; 71 status = "disabled"; 72 }; 73 }; 74 75 cpus { 76 #address-cells = <0x2>; 77 #size-cells = <0x0>; 78 79 cpu0: cpu@0 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53"; 82 reg = <0x0 0x0>; 83 enable-method = "psci"; 84 next-level-cache = <&l2>; 85 clocks = <&scpi_dvfs 0>; 86 }; 87 88 cpu1: cpu@1 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x0 0x1>; 92 enable-method = "psci"; 93 next-level-cache = <&l2>; 94 clocks = <&scpi_dvfs 0>; 95 }; 96 97 cpu2: cpu@2 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x0 0x2>; 101 enable-method = "psci"; 102 next-level-cache = <&l2>; 103 clocks = <&scpi_dvfs 0>; 104 }; 105 106 cpu3: cpu@3 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x0 0x3>; 110 enable-method = "psci"; 111 next-level-cache = <&l2>; 112 clocks = <&scpi_dvfs 0>; 113 }; 114 115 l2: l2-cache0 { 116 compatible = "cache"; 117 }; 118 }; 119 120 arm-pmu { 121 compatible = "arm,cortex-a53-pmu"; 122 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 126 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 127 }; 128 129 psci { 130 compatible = "arm,psci-0.2"; 131 method = "smc"; 132 }; 133 134 timer { 135 compatible = "arm,armv8-timer"; 136 interrupts = <GIC_PPI 13 137 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 138 <GIC_PPI 14 139 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 140 <GIC_PPI 11 141 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 142 <GIC_PPI 10 143 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 144 }; 145 146 xtal: xtal-clk { 147 compatible = "fixed-clock"; 148 clock-frequency = <24000000>; 149 clock-output-names = "xtal"; 150 #clock-cells = <0>; 151 }; 152 153 firmware { 154 sm: secure-monitor { 155 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; 156 }; 157 }; 158 159 efuse: efuse { 160 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 read-only; 164 165 sn: sn@14 { 166 reg = <0x14 0x10>; 167 }; 168 169 eth_mac: eth_mac@34 { 170 reg = <0x34 0x10>; 171 }; 172 173 bid: bid@46 { 174 reg = <0x46 0x30>; 175 }; 176 }; 177 178 scpi { 179 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; 180 mboxes = <&mailbox 1 &mailbox 2>; 181 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 182 183 scpi_clocks: clocks { 184 compatible = "arm,scpi-clocks"; 185 186 scpi_dvfs: scpi_clocks@0 { 187 compatible = "arm,scpi-dvfs-clocks"; 188 #clock-cells = <1>; 189 clock-indices = <0>; 190 clock-output-names = "vcpu"; 191 }; 192 }; 193 194 scpi_sensors: sensors { 195 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; 196 #thermal-sensor-cells = <1>; 197 }; 198 }; 199 200 soc { 201 compatible = "simple-bus"; 202 #address-cells = <2>; 203 #size-cells = <2>; 204 ranges; 205 206 cbus: bus@c1100000 { 207 compatible = "simple-bus"; 208 reg = <0x0 0xc1100000 0x0 0x100000>; 209 #address-cells = <2>; 210 #size-cells = <2>; 211 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; 212 213 gpio_intc: interrupt-controller@9880 { 214 compatible = "amlogic,meson-gpio-intc"; 215 reg = <0x0 0x9880 0x0 0x10>; 216 interrupt-controller; 217 #interrupt-cells = <2>; 218 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 219 status = "disabled"; 220 }; 221 222 reset: reset-controller@4404 { 223 compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; 224 reg = <0x0 0x04404 0x0 0x9c>; 225 #reset-cells = <1>; 226 }; 227 228 uart_A: serial@84c0 { 229 compatible = "amlogic,meson-gx-uart"; 230 reg = <0x0 0x84c0 0x0 0x18>; 231 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 232 status = "disabled"; 233 }; 234 235 uart_B: serial@84dc { 236 compatible = "amlogic,meson-gx-uart"; 237 reg = <0x0 0x84dc 0x0 0x18>; 238 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 239 status = "disabled"; 240 }; 241 242 i2c_A: i2c@8500 { 243 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 244 reg = <0x0 0x08500 0x0 0x20>; 245 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 status = "disabled"; 249 }; 250 251 pwm_ab: pwm@8550 { 252 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 253 reg = <0x0 0x08550 0x0 0x10>; 254 #pwm-cells = <3>; 255 status = "disabled"; 256 }; 257 258 pwm_cd: pwm@8650 { 259 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 260 reg = <0x0 0x08650 0x0 0x10>; 261 #pwm-cells = <3>; 262 status = "disabled"; 263 }; 264 265 saradc: adc@8680 { 266 compatible = "amlogic,meson-saradc"; 267 reg = <0x0 0x8680 0x0 0x34>; 268 #io-channel-cells = <1>; 269 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 270 status = "disabled"; 271 }; 272 273 pwm_ef: pwm@86c0 { 274 compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; 275 reg = <0x0 0x086c0 0x0 0x10>; 276 #pwm-cells = <3>; 277 status = "disabled"; 278 }; 279 280 uart_C: serial@8700 { 281 compatible = "amlogic,meson-gx-uart"; 282 reg = <0x0 0x8700 0x0 0x18>; 283 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 284 status = "disabled"; 285 }; 286 287 clock-measure@8758 { 288 compatible = "amlogic,meson-gx-clk-measure"; 289 reg = <0x0 0x8758 0x0 0x10>; 290 }; 291 292 i2c_B: i2c@87c0 { 293 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 294 reg = <0x0 0x087c0 0x0 0x20>; 295 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 status = "disabled"; 299 }; 300 301 i2c_C: i2c@87e0 { 302 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 303 reg = <0x0 0x087e0 0x0 0x20>; 304 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 status = "disabled"; 308 }; 309 310 spicc: spi@8d80 { 311 compatible = "amlogic,meson-gx-spicc"; 312 reg = <0x0 0x08d80 0x0 0x80>; 313 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 314 #address-cells = <1>; 315 #size-cells = <0>; 316 status = "disabled"; 317 }; 318 319 spifc: spi@8c80 { 320 compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc"; 321 reg = <0x0 0x08c80 0x0 0x80>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 status = "disabled"; 325 }; 326 327 watchdog@98d0 { 328 compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt"; 329 reg = <0x0 0x098d0 0x0 0x10>; 330 clocks = <&xtal>; 331 }; 332 }; 333 334 gic: interrupt-controller@c4301000 { 335 compatible = "arm,gic-400"; 336 reg = <0x0 0xc4301000 0 0x1000>, 337 <0x0 0xc4302000 0 0x2000>, 338 <0x0 0xc4304000 0 0x2000>, 339 <0x0 0xc4306000 0 0x2000>; 340 interrupt-controller; 341 interrupts = <GIC_PPI 9 342 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 343 #interrupt-cells = <3>; 344 #address-cells = <0>; 345 }; 346 347 sram: sram@c8000000 { 348 compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram"; 349 reg = <0x0 0xc8000000 0x0 0x14000>; 350 351 #address-cells = <1>; 352 #size-cells = <1>; 353 ranges = <0 0x0 0xc8000000 0x14000>; 354 355 cpu_scp_lpri: scp-shmem@0 { 356 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; 357 reg = <0x13000 0x400>; 358 }; 359 360 cpu_scp_hpri: scp-shmem@200 { 361 compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; 362 reg = <0x13400 0x400>; 363 }; 364 }; 365 366 aobus: bus@c8100000 { 367 compatible = "simple-bus"; 368 reg = <0x0 0xc8100000 0x0 0x100000>; 369 #address-cells = <2>; 370 #size-cells = <2>; 371 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; 372 373 sysctrl_AO: sys-ctrl@0 { 374 compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; 375 reg = <0x0 0x0 0x0 0x100>; 376 377 pwrc_vpu: power-controller-vpu { 378 compatible = "amlogic,meson-gx-pwrc-vpu"; 379 #power-domain-cells = <0>; 380 amlogic,hhi-sysctrl = <&sysctrl>; 381 }; 382 383 clkc_AO: clock-controller { 384 compatible = "amlogic,meson-gx-aoclkc"; 385 #clock-cells = <1>; 386 #reset-cells = <1>; 387 }; 388 }; 389 390 cec_AO: cec@100 { 391 compatible = "amlogic,meson-gx-ao-cec"; 392 reg = <0x0 0x00100 0x0 0x14>; 393 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 394 }; 395 396 sec_AO: ao-secure@140 { 397 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 398 reg = <0x0 0x140 0x0 0x140>; 399 amlogic,has-chip-id; 400 }; 401 402 uart_AO: serial@4c0 { 403 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 404 reg = <0x0 0x004c0 0x0 0x18>; 405 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 406 status = "disabled"; 407 }; 408 409 uart_AO_B: serial@4e0 { 410 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 411 reg = <0x0 0x004e0 0x0 0x18>; 412 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 413 status = "disabled"; 414 }; 415 416 i2c_AO: i2c@500 { 417 compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; 418 reg = <0x0 0x500 0x0 0x20>; 419 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 status = "disabled"; 423 }; 424 425 pwm_AO_ab: pwm@550 { 426 compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; 427 reg = <0x0 0x00550 0x0 0x10>; 428 #pwm-cells = <3>; 429 status = "disabled"; 430 }; 431 432 ir: ir@580 { 433 compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; 434 reg = <0x0 0x00580 0x0 0x40>; 435 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 436 status = "disabled"; 437 }; 438 }; 439 440 periphs: periphs@c8834000 { 441 compatible = "simple-bus"; 442 reg = <0x0 0xc8834000 0x0 0x2000>; 443 #address-cells = <2>; 444 #size-cells = <2>; 445 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; 446 447 hwrng: rng { 448 compatible = "amlogic,meson-rng"; 449 reg = <0x0 0x0 0x0 0x4>; 450 }; 451 }; 452 453 dmcbus: bus@c8838000 { 454 compatible = "simple-bus"; 455 reg = <0x0 0xc8838000 0x0 0x400>; 456 #address-cells = <2>; 457 #size-cells = <2>; 458 ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>; 459 460 canvas: video-lut@48 { 461 compatible = "amlogic,canvas"; 462 reg = <0x0 0x48 0x0 0x14>; 463 }; 464 }; 465 466 hiubus: bus@c883c000 { 467 compatible = "simple-bus"; 468 reg = <0x0 0xc883c000 0x0 0x2000>; 469 #address-cells = <2>; 470 #size-cells = <2>; 471 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; 472 473 sysctrl: system-controller@0 { 474 compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; 475 reg = <0 0 0 0x400>; 476 }; 477 478 mailbox: mailbox@404 { 479 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 480 reg = <0 0x404 0 0x4c>; 481 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 482 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 483 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 484 #mbox-cells = <1>; 485 }; 486 }; 487 488 ethmac: ethernet@c9410000 { 489 compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 490 reg = <0x0 0xc9410000 0x0 0x10000 491 0x0 0xc8834540 0x0 0x4>; 492 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 493 interrupt-names = "macirq"; 494 status = "disabled"; 495 }; 496 497 apb: apb@d0000000 { 498 compatible = "simple-bus"; 499 reg = <0x0 0xd0000000 0x0 0x200000>; 500 #address-cells = <2>; 501 #size-cells = <2>; 502 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; 503 504 sd_emmc_a: mmc@70000 { 505 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 506 reg = <0x0 0x70000 0x0 0x800>; 507 interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; 508 status = "disabled"; 509 }; 510 511 sd_emmc_b: mmc@72000 { 512 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 513 reg = <0x0 0x72000 0x0 0x800>; 514 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 515 status = "disabled"; 516 }; 517 518 sd_emmc_c: mmc@74000 { 519 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 520 reg = <0x0 0x74000 0x0 0x800>; 521 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 522 status = "disabled"; 523 }; 524 }; 525 526 vpu: vpu@d0100000 { 527 compatible = "amlogic,meson-gx-vpu"; 528 reg = <0x0 0xd0100000 0x0 0x100000>, 529 <0x0 0xc883c000 0x0 0x1000>, 530 <0x0 0xc8838000 0x0 0x1000>; 531 reg-names = "vpu", "hhi", "dmc"; 532 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 amlogic,canvas = <&canvas>; 536 537 /* CVBS VDAC output port */ 538 cvbs_vdac_port: port@0 { 539 reg = <0>; 540 }; 541 542 /* HDMI-TX output port */ 543 hdmi_tx_port: port@1 { 544 reg = <1>; 545 546 hdmi_tx_out: endpoint { 547 remote-endpoint = <&hdmi_tx_in>; 548 }; 549 }; 550 }; 551 552 hdmi_tx: hdmi-tx@c883a000 { 553 compatible = "amlogic,meson-gx-dw-hdmi"; 554 reg = <0x0 0xc883a000 0x0 0x1c>; 555 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 status = "disabled"; 559 560 /* VPU VENC Input */ 561 hdmi_tx_venc_port: port@0 { 562 reg = <0>; 563 564 hdmi_tx_in: endpoint { 565 remote-endpoint = <&hdmi_tx_out>; 566 }; 567 }; 568 569 /* TMDS Output */ 570 hdmi_tx_tmds_port: port@1 { 571 reg = <1>; 572 }; 573 }; 574 }; 575}; 576