1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Andreas Färber 4 * 5 * Copyright (c) 2016 BayLibre, SAS. 6 * Author: Neil Armstrong <narmstrong@baylibre.com> 7 * 8 * Copyright (c) 2016 Endless Computers, Inc. 9 * Author: Carlo Caione <carlo@endlessm.com> 10 */ 11 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/power/meson-gxbb-power.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 mmc0 = &sd_emmc_b; /* SD card */ 25 mmc1 = &sd_emmc_c; /* eMMC */ 26 mmc2 = &sd_emmc_a; /* SDIO */ 27 }; 28 29 reserved-memory { 30 #address-cells = <2>; 31 #size-cells = <2>; 32 ranges; 33 34 /* 16 MiB reserved for Hardware ROM Firmware */ 35 hwrom_reserved: hwrom@0 { 36 reg = <0x0 0x0 0x0 0x1000000>; 37 no-map; 38 }; 39 40 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 41 secmon_reserved: secmon@10000000 { 42 reg = <0x0 0x10000000 0x0 0x200000>; 43 no-map; 44 }; 45 46 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 47 secmon_reserved_alt: secmon@5000000 { 48 reg = <0x0 0x05000000 0x0 0x300000>; 49 no-map; 50 }; 51 52 /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ 53 secmon_reserved_bl32: secmon@5300000 { 54 reg = <0x0 0x05300000 0x0 0x2000000>; 55 no-map; 56 }; 57 58 linux,cma { 59 compatible = "shared-dma-pool"; 60 reusable; 61 size = <0x0 0x10000000>; 62 alignment = <0x0 0x400000>; 63 linux,cma-default; 64 }; 65 }; 66 67 chosen { 68 #address-cells = <2>; 69 #size-cells = <2>; 70 ranges; 71 72 simplefb_cvbs: framebuffer-cvbs { 73 compatible = "amlogic,simple-framebuffer", 74 "simple-framebuffer"; 75 amlogic,pipeline = "vpu-cvbs"; 76 power-domains = <&pwrc PWRC_GXBB_VPU_ID>; 77 status = "disabled"; 78 }; 79 80 simplefb_hdmi: framebuffer-hdmi { 81 compatible = "amlogic,simple-framebuffer", 82 "simple-framebuffer"; 83 amlogic,pipeline = "vpu-hdmi"; 84 power-domains = <&pwrc PWRC_GXBB_VPU_ID>; 85 status = "disabled"; 86 }; 87 }; 88 89 cpus { 90 #address-cells = <0x2>; 91 #size-cells = <0x0>; 92 93 cpu0: cpu@0 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x0>; 97 enable-method = "psci"; 98 d-cache-line-size = <32>; 99 d-cache-size = <0x8000>; 100 d-cache-sets = <32>; 101 i-cache-line-size = <32>; 102 i-cache-size = <0x8000>; 103 i-cache-sets = <32>; 104 next-level-cache = <&l2>; 105 clocks = <&scpi_dvfs 0>; 106 #cooling-cells = <2>; 107 }; 108 109 cpu1: cpu@1 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a53"; 112 reg = <0x0 0x1>; 113 enable-method = "psci"; 114 d-cache-line-size = <32>; 115 d-cache-size = <0x8000>; 116 d-cache-sets = <32>; 117 i-cache-line-size = <32>; 118 i-cache-size = <0x8000>; 119 i-cache-sets = <32>; 120 next-level-cache = <&l2>; 121 clocks = <&scpi_dvfs 0>; 122 #cooling-cells = <2>; 123 }; 124 125 cpu2: cpu@2 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a53"; 128 reg = <0x0 0x2>; 129 enable-method = "psci"; 130 d-cache-line-size = <32>; 131 d-cache-size = <0x8000>; 132 d-cache-sets = <32>; 133 i-cache-line-size = <32>; 134 i-cache-size = <0x8000>; 135 i-cache-sets = <32>; 136 next-level-cache = <&l2>; 137 clocks = <&scpi_dvfs 0>; 138 #cooling-cells = <2>; 139 }; 140 141 cpu3: cpu@3 { 142 device_type = "cpu"; 143 compatible = "arm,cortex-a53"; 144 reg = <0x0 0x3>; 145 enable-method = "psci"; 146 d-cache-line-size = <32>; 147 d-cache-size = <0x8000>; 148 d-cache-sets = <32>; 149 i-cache-line-size = <32>; 150 i-cache-size = <0x8000>; 151 i-cache-sets = <32>; 152 next-level-cache = <&l2>; 153 clocks = <&scpi_dvfs 0>; 154 #cooling-cells = <2>; 155 }; 156 157 l2: l2-cache0 { 158 compatible = "cache"; 159 cache-level = <2>; 160 cache-unified; 161 cache-size = <0x80000>; /* L2. 512 KB */ 162 cache-line-size = <64>; 163 cache-sets = <512>; 164 }; 165 }; 166 167 thermal-zones { 168 cpu-thermal { 169 polling-delay-passive = <250>; /* milliseconds */ 170 polling-delay = <1000>; /* milliseconds */ 171 172 thermal-sensors = <&scpi_sensors 0>; 173 174 trips { 175 cpu_passive: cpu-passive { 176 temperature = <80000>; /* millicelsius */ 177 hysteresis = <2000>; /* millicelsius */ 178 type = "passive"; 179 }; 180 181 cpu_hot: cpu-hot { 182 temperature = <90000>; /* millicelsius */ 183 hysteresis = <2000>; /* millicelsius */ 184 type = "hot"; 185 }; 186 187 cpu_critical: cpu-critical { 188 temperature = <110000>; /* millicelsius */ 189 hysteresis = <2000>; /* millicelsius */ 190 type = "critical"; 191 }; 192 }; 193 194 cpu_cooling_maps: cooling-maps { 195 map0 { 196 trip = <&cpu_passive>; 197 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 198 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 199 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 200 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 201 }; 202 203 map1 { 204 trip = <&cpu_hot>; 205 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 206 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 207 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 208 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 209 }; 210 }; 211 }; 212 }; 213 214 arm-pmu { 215 compatible = "arm,cortex-a53-pmu"; 216 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 220 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 221 }; 222 223 psci { 224 compatible = "arm,psci-0.2"; 225 method = "smc"; 226 }; 227 228 timer { 229 compatible = "arm,armv8-timer"; 230 interrupts = <GIC_PPI 13 231 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 232 <GIC_PPI 14 233 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 234 <GIC_PPI 11 235 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 236 <GIC_PPI 10 237 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 238 }; 239 240 xtal: xtal-clk { 241 compatible = "fixed-clock"; 242 clock-frequency = <24000000>; 243 clock-output-names = "xtal"; 244 #clock-cells = <0>; 245 }; 246 247 firmware { 248 sm: secure-monitor { 249 compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; 250 }; 251 }; 252 253 efuse: efuse { 254 compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; 255 #address-cells = <1>; 256 #size-cells = <1>; 257 read-only; 258 secure-monitor = <&sm>; 259 260 sn: sn@14 { 261 reg = <0x14 0x10>; 262 }; 263 264 eth_mac: eth-mac@34 { 265 reg = <0x34 0x10>; 266 }; 267 268 bid: bid@46 { 269 reg = <0x46 0x30>; 270 }; 271 }; 272 273 scpi { 274 compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; 275 mboxes = <&mailbox 1 &mailbox 2>; 276 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 277 278 scpi_clocks: clocks { 279 compatible = "arm,scpi-clocks"; 280 281 scpi_dvfs: clocks-0 { 282 compatible = "arm,scpi-dvfs-clocks"; 283 #clock-cells = <1>; 284 clock-indices = <0>; 285 clock-output-names = "vcpu"; 286 }; 287 }; 288 289 scpi_sensors: sensors { 290 compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; 291 #thermal-sensor-cells = <1>; 292 }; 293 }; 294 295 soc { 296 compatible = "simple-bus"; 297 #address-cells = <2>; 298 #size-cells = <2>; 299 ranges; 300 301 cbus: bus@c1100000 { 302 compatible = "simple-bus"; 303 reg = <0x0 0xc1100000 0x0 0x100000>; 304 #address-cells = <2>; 305 #size-cells = <2>; 306 ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; 307 308 gpio_intc: interrupt-controller@9880 { 309 compatible = "amlogic,meson-gpio-intc"; 310 reg = <0x0 0x9880 0x0 0x10>; 311 interrupt-controller; 312 #interrupt-cells = <2>; 313 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 314 status = "disabled"; 315 }; 316 317 reset: reset-controller@4404 { 318 compatible = "amlogic,meson-gxbb-reset"; 319 reg = <0x0 0x04404 0x0 0x9c>; 320 #reset-cells = <1>; 321 }; 322 323 aiu: audio-controller@5400 { 324 compatible = "amlogic,aiu"; 325 #sound-dai-cells = <2>; 326 sound-name-prefix = "AIU"; 327 reg = <0x0 0x5400 0x0 0x2ac>; 328 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 329 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>; 330 interrupt-names = "i2s", "spdif"; 331 status = "disabled"; 332 }; 333 334 uart_A: serial@84c0 { 335 compatible = "amlogic,meson-gx-uart"; 336 reg = <0x0 0x84c0 0x0 0x18>; 337 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 338 status = "disabled"; 339 fifo-size = <128>; 340 }; 341 342 uart_B: serial@84dc { 343 compatible = "amlogic,meson-gx-uart"; 344 reg = <0x0 0x84dc 0x0 0x18>; 345 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 346 status = "disabled"; 347 }; 348 349 i2c_A: i2c@8500 { 350 compatible = "amlogic,meson-gxbb-i2c"; 351 reg = <0x0 0x08500 0x0 0x20>; 352 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 status = "disabled"; 356 }; 357 358 pwm_ab: pwm@8550 { 359 compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2"; 360 reg = <0x0 0x08550 0x0 0x10>; 361 #pwm-cells = <3>; 362 status = "disabled"; 363 }; 364 365 pwm_cd: pwm@8650 { 366 compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2"; 367 reg = <0x0 0x08650 0x0 0x10>; 368 #pwm-cells = <3>; 369 status = "disabled"; 370 }; 371 372 saradc: adc@8680 { 373 compatible = "amlogic,meson-saradc"; 374 reg = <0x0 0x8680 0x0 0x34>; 375 #io-channel-cells = <1>; 376 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 377 status = "disabled"; 378 }; 379 380 pwm_ef: pwm@86c0 { 381 compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2"; 382 reg = <0x0 0x086c0 0x0 0x10>; 383 #pwm-cells = <3>; 384 status = "disabled"; 385 }; 386 387 uart_C: serial@8700 { 388 compatible = "amlogic,meson-gx-uart"; 389 reg = <0x0 0x8700 0x0 0x18>; 390 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 391 status = "disabled"; 392 }; 393 394 clock-measure@8758 { 395 compatible = "amlogic,meson-gx-clk-measure"; 396 reg = <0x0 0x8758 0x0 0x10>; 397 }; 398 399 i2c_B: i2c@87c0 { 400 compatible = "amlogic,meson-gxbb-i2c"; 401 reg = <0x0 0x087c0 0x0 0x20>; 402 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 403 #address-cells = <1>; 404 #size-cells = <0>; 405 status = "disabled"; 406 }; 407 408 i2c_C: i2c@87e0 { 409 compatible = "amlogic,meson-gxbb-i2c"; 410 reg = <0x0 0x087e0 0x0 0x20>; 411 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 status = "disabled"; 415 }; 416 417 spicc: spi@8d80 { 418 compatible = "amlogic,meson-gx-spicc"; 419 reg = <0x0 0x08d80 0x0 0x80>; 420 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 421 #address-cells = <1>; 422 #size-cells = <0>; 423 status = "disabled"; 424 }; 425 426 spifc: spi@8c80 { 427 compatible = "amlogic,meson-gxbb-spifc"; 428 reg = <0x0 0x08c80 0x0 0x80>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 status = "disabled"; 432 }; 433 434 watchdog@98d0 { 435 compatible = "amlogic,meson-gxbb-wdt"; 436 reg = <0x0 0x098d0 0x0 0x10>; 437 clocks = <&xtal>; 438 }; 439 }; 440 441 gic: interrupt-controller@c4301000 { 442 compatible = "arm,gic-400"; 443 reg = <0x0 0xc4301000 0 0x1000>, 444 <0x0 0xc4302000 0 0x2000>, 445 <0x0 0xc4304000 0 0x2000>, 446 <0x0 0xc4306000 0 0x2000>; 447 interrupt-controller; 448 interrupts = <GIC_PPI 9 449 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 450 #interrupt-cells = <3>; 451 #address-cells = <0>; 452 }; 453 454 sram: sram@c8000000 { 455 compatible = "mmio-sram"; 456 reg = <0x0 0xc8000000 0x0 0x14000>; 457 458 #address-cells = <1>; 459 #size-cells = <1>; 460 ranges = <0 0x0 0xc8000000 0x14000>; 461 462 cpu_scp_lpri: scp-sram@0 { 463 compatible = "amlogic,meson-gxbb-scp-shmem"; 464 reg = <0x13000 0x400>; 465 }; 466 467 cpu_scp_hpri: scp-sram@200 { 468 compatible = "amlogic,meson-gxbb-scp-shmem"; 469 reg = <0x13400 0x400>; 470 }; 471 }; 472 473 aobus: bus@c8100000 { 474 compatible = "simple-bus"; 475 reg = <0x0 0xc8100000 0x0 0x100000>; 476 #address-cells = <2>; 477 #size-cells = <2>; 478 ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; 479 480 sysctrl_AO: sys-ctrl@0 { 481 compatible = "amlogic,meson-gx-ao-sysctrl", "simple-mfd", "syscon"; 482 reg = <0x0 0x0 0x0 0x100>; 483 484 clkc_AO: clock-controller { 485 compatible = "amlogic,meson-gx-aoclkc"; 486 #clock-cells = <1>; 487 #reset-cells = <1>; 488 }; 489 }; 490 491 cec_AO: cec@100 { 492 compatible = "amlogic,meson-gx-ao-cec"; 493 reg = <0x0 0x00100 0x0 0x14>; 494 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 495 status = "disabled"; 496 }; 497 498 sec_AO: ao-secure@140 { 499 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 500 reg = <0x0 0x140 0x0 0x140>; 501 amlogic,has-chip-id; 502 }; 503 504 uart_AO: serial@4c0 { 505 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 506 reg = <0x0 0x004c0 0x0 0x18>; 507 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 508 status = "disabled"; 509 }; 510 511 uart_AO_B: serial@4e0 { 512 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 513 reg = <0x0 0x004e0 0x0 0x18>; 514 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 515 status = "disabled"; 516 }; 517 518 i2c_AO: i2c@500 { 519 compatible = "amlogic,meson-gxbb-i2c"; 520 reg = <0x0 0x500 0x0 0x20>; 521 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 status = "disabled"; 525 }; 526 527 pwm_AO_ab: pwm@550 { 528 compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2"; 529 reg = <0x0 0x00550 0x0 0x10>; 530 #pwm-cells = <3>; 531 status = "disabled"; 532 }; 533 534 ir: ir@580 { 535 compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; 536 reg = <0x0 0x00580 0x0 0x40>; 537 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 538 status = "disabled"; 539 }; 540 }; 541 542 vdec: video-codec@c8820000 { 543 compatible = "amlogic,gx-vdec"; 544 reg = <0x0 0xc8820000 0x0 0x10000>, 545 <0x0 0xc110a580 0x0 0xe4>; 546 reg-names = "dos", "esparser"; 547 548 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 549 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 550 interrupt-names = "vdec", "esparser"; 551 552 amlogic,ao-sysctrl = <&sysctrl_AO>; 553 amlogic,canvas = <&canvas>; 554 }; 555 556 periphs: bus@c8834000 { 557 compatible = "simple-bus"; 558 reg = <0x0 0xc8834000 0x0 0x2000>; 559 #address-cells = <2>; 560 #size-cells = <2>; 561 ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; 562 563 hwrng: rng@0 { 564 compatible = "amlogic,meson-rng"; 565 reg = <0x0 0x0 0x0 0x4>; 566 }; 567 }; 568 569 dmcbus: bus@c8838000 { 570 compatible = "simple-bus"; 571 reg = <0x0 0xc8838000 0x0 0x400>; 572 #address-cells = <2>; 573 #size-cells = <2>; 574 ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x400>; 575 576 canvas: video-lut@48 { 577 compatible = "amlogic,canvas"; 578 reg = <0x0 0x48 0x0 0x14>; 579 }; 580 }; 581 582 hiubus: bus@c883c000 { 583 compatible = "simple-bus"; 584 reg = <0x0 0xc883c000 0x0 0x2000>; 585 #address-cells = <2>; 586 #size-cells = <2>; 587 ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; 588 589 sysctrl: system-controller@0 { 590 compatible = "amlogic,meson-gx-hhi-sysctrl", "simple-mfd", "syscon"; 591 reg = <0 0 0 0x400>; 592 593 pwrc: power-controller { 594 compatible = "amlogic,meson-gxbb-pwrc"; 595 #power-domain-cells = <1>; 596 amlogic,ao-sysctrl = <&sysctrl_AO>; 597 }; 598 }; 599 600 mailbox: mailbox@404 { 601 compatible = "amlogic,meson-gxbb-mhu"; 602 reg = <0 0x404 0 0x4c>; 603 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 604 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 605 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 606 #mbox-cells = <1>; 607 }; 608 }; 609 610 ethmac: ethernet@c9410000 { 611 compatible = "amlogic,meson-gxbb-dwmac", 612 "snps,dwmac-3.70a", 613 "snps,dwmac"; 614 reg = <0x0 0xc9410000 0x0 0x10000>, 615 <0x0 0xc8834540 0x0 0x4>; 616 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 617 interrupt-names = "macirq"; 618 rx-fifo-depth = <4096>; 619 tx-fifo-depth = <2048>; 620 power-domains = <&pwrc PWRC_GXBB_ETHERNET_MEM_ID>; 621 status = "disabled"; 622 }; 623 624 apb: apb@d0000000 { 625 compatible = "simple-bus"; 626 reg = <0x0 0xd0000000 0x0 0x200000>; 627 #address-cells = <2>; 628 #size-cells = <2>; 629 ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; 630 631 sd_emmc_a: mmc@70000 { 632 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 633 reg = <0x0 0x70000 0x0 0x800>; 634 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 635 status = "disabled"; 636 }; 637 638 sd_emmc_b: mmc@72000 { 639 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 640 reg = <0x0 0x72000 0x0 0x800>; 641 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 642 status = "disabled"; 643 }; 644 645 sd_emmc_c: mmc@74000 { 646 compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; 647 reg = <0x0 0x74000 0x0 0x800>; 648 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 649 status = "disabled"; 650 }; 651 }; 652 653 vpu: vpu@d0100000 { 654 compatible = "amlogic,meson-gx-vpu"; 655 reg = <0x0 0xd0100000 0x0 0x100000>, 656 <0x0 0xc883c000 0x0 0x1000>; 657 reg-names = "vpu", "hhi"; 658 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 659 #address-cells = <1>; 660 #size-cells = <0>; 661 amlogic,canvas = <&canvas>; 662 663 /* CVBS VDAC output port */ 664 cvbs_vdac_port: port@0 { 665 reg = <0>; 666 }; 667 668 /* HDMI-TX output port */ 669 hdmi_tx_port: port@1 { 670 reg = <1>; 671 672 hdmi_tx_out: endpoint { 673 remote-endpoint = <&hdmi_tx_in>; 674 }; 675 }; 676 }; 677 678 hdmi_tx: hdmi-tx@c883a000 { 679 compatible = "amlogic,meson-gx-dw-hdmi"; 680 reg = <0x0 0xc883a000 0x0 0x1c>; 681 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 #sound-dai-cells = <0>; 685 sound-name-prefix = "HDMITX"; 686 status = "disabled"; 687 688 /* VPU VENC Input */ 689 hdmi_tx_venc_port: port@0 { 690 reg = <0>; 691 692 hdmi_tx_in: endpoint { 693 remote-endpoint = <&hdmi_tx_out>; 694 }; 695 }; 696 697 /* TMDS Output */ 698 hdmi_tx_tmds_port: port@1 { 699 reg = <1>; 700 }; 701 }; 702 }; 703}; 704