1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 */ 6 7#include "meson-g12.dtsi" 8 9/ { 10 compatible = "amlogic,g12b"; 11 12 cpus { 13 #address-cells = <0x2>; 14 #size-cells = <0x0>; 15 16 cpu-map { 17 cluster0 { 18 core0 { 19 cpu = <&cpu0>; 20 }; 21 22 core1 { 23 cpu = <&cpu1>; 24 }; 25 }; 26 27 cluster1 { 28 core0 { 29 cpu = <&cpu100>; 30 }; 31 32 core1 { 33 cpu = <&cpu101>; 34 }; 35 36 core2 { 37 cpu = <&cpu102>; 38 }; 39 40 core3 { 41 cpu = <&cpu103>; 42 }; 43 }; 44 }; 45 46 cpu0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 capacity-dmips-mhz = <592>; 52 d-cache-line-size = <32>; 53 d-cache-size = <0x8000>; 54 d-cache-sets = <32>; 55 i-cache-line-size = <32>; 56 i-cache-size = <0x8000>; 57 i-cache-sets = <32>; 58 next-level-cache = <&l2_cache_l>; 59 #cooling-cells = <2>; 60 }; 61 62 cpu1: cpu@1 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53"; 65 reg = <0x0 0x1>; 66 enable-method = "psci"; 67 capacity-dmips-mhz = <592>; 68 d-cache-line-size = <32>; 69 d-cache-size = <0x8000>; 70 d-cache-sets = <32>; 71 i-cache-line-size = <32>; 72 i-cache-size = <0x8000>; 73 i-cache-sets = <32>; 74 next-level-cache = <&l2_cache_l>; 75 #cooling-cells = <2>; 76 }; 77 78 cpu100: cpu@100 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a73"; 81 reg = <0x0 0x100>; 82 enable-method = "psci"; 83 capacity-dmips-mhz = <1024>; 84 d-cache-line-size = <32>; 85 d-cache-size = <0x8000>; 86 d-cache-sets = <32>; 87 i-cache-line-size = <32>; 88 i-cache-size = <0x8000>; 89 i-cache-sets = <32>; 90 next-level-cache = <&l2_cache_l>; 91 #cooling-cells = <2>; 92 }; 93 94 cpu101: cpu@101 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a73"; 97 reg = <0x0 0x101>; 98 enable-method = "psci"; 99 capacity-dmips-mhz = <1024>; 100 d-cache-line-size = <32>; 101 d-cache-size = <0x8000>; 102 d-cache-sets = <32>; 103 i-cache-line-size = <32>; 104 i-cache-size = <0x8000>; 105 i-cache-sets = <32>; 106 next-level-cache = <&l2_cache_l>; 107 #cooling-cells = <2>; 108 }; 109 110 cpu102: cpu@102 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a73"; 113 reg = <0x0 0x102>; 114 enable-method = "psci"; 115 capacity-dmips-mhz = <1024>; 116 d-cache-line-size = <64>; 117 d-cache-size = <0x10000>; 118 d-cache-sets = <64>; 119 i-cache-line-size = <64>; 120 i-cache-size = <0x10000>; 121 i-cache-sets = <64>; 122 next-level-cache = <&l2_cache_b>; 123 #cooling-cells = <2>; 124 }; 125 126 cpu103: cpu@103 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a73"; 129 reg = <0x0 0x103>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <1024>; 132 d-cache-line-size = <64>; 133 d-cache-size = <0x10000>; 134 d-cache-sets = <64>; 135 i-cache-line-size = <64>; 136 i-cache-size = <0x10000>; 137 i-cache-sets = <64>; 138 next-level-cache = <&l2_cache_b>; 139 #cooling-cells = <2>; 140 }; 141 142 l2_cache_l: l2-cache-cluster0 { 143 compatible = "cache"; 144 cache-level = <2>; 145 cache-unified; 146 cache-size = <0x40000>; /* L2. 256 KB */ 147 cache-line-size = <64>; 148 cache-sets = <512>; 149 }; 150 151 l2_cache_b: l2-cache-cluster1 { 152 compatible = "cache"; 153 cache-level = <2>; 154 cache-unified; 155 cache-size = <0x100000>; /* L2. 1MB */ 156 cache-line-size = <64>; 157 cache-sets = <512>; 158 }; 159 }; 160}; 161 162&clkc { 163 compatible = "amlogic,g12b-clkc"; 164}; 165 166&cpu_thermal { 167 cooling-maps { 168 map0 { 169 trip = <&cpu_passive>; 170 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 171 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 172 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 173 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 174 <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 175 <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 176 }; 177 map1 { 178 trip = <&cpu_hot>; 179 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 180 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 181 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 182 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 183 <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 184 <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 185 }; 186 }; 187}; 188 189&mali { 190 dma-coherent; 191}; 192 193&pmu { 194 compatible = "amlogic,g12b-ddr-pmu"; 195}; 196 197&npu { 198 power-domains = <&pwrc PWRC_G12A_NNA_ID>; 199}; 200