1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 mmc0 = &sd_emmc_b; /* SD card */ 22 mmc1 = &sd_emmc_c; /* eMMC */ 23 mmc2 = &sd_emmc_a; /* SDIO */ 24 }; 25 26 chosen { 27 #address-cells = <2>; 28 #size-cells = <2>; 29 ranges; 30 31 simplefb_cvbs: framebuffer-cvbs { 32 compatible = "amlogic,simple-framebuffer", 33 "simple-framebuffer"; 34 amlogic,pipeline = "vpu-cvbs"; 35 clocks = <&clkc CLKID_HDMI>, 36 <&clkc CLKID_HTX_PCLK>, 37 <&clkc CLKID_VPU_INTR>; 38 status = "disabled"; 39 }; 40 41 simplefb_hdmi: framebuffer-hdmi { 42 compatible = "amlogic,simple-framebuffer", 43 "simple-framebuffer"; 44 amlogic,pipeline = "vpu-hdmi"; 45 clocks = <&clkc CLKID_HDMI>, 46 <&clkc CLKID_HTX_PCLK>, 47 <&clkc CLKID_VPU_INTR>; 48 status = "disabled"; 49 }; 50 }; 51 52 efuse: efuse { 53 compatible = "amlogic,meson-gxbb-efuse"; 54 clocks = <&clkc CLKID_EFUSE>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 read-only; 58 secure-monitor = <&sm>; 59 }; 60 61 gpu_opp_table: opp-table-gpu { 62 compatible = "operating-points-v2"; 63 64 opp-124999998 { 65 opp-hz = /bits/ 64 <124999998>; 66 opp-microvolt = <800000>; 67 }; 68 opp-249999996 { 69 opp-hz = /bits/ 64 <249999996>; 70 opp-microvolt = <800000>; 71 }; 72 opp-285714281 { 73 opp-hz = /bits/ 64 <285714281>; 74 opp-microvolt = <800000>; 75 }; 76 opp-399999994 { 77 opp-hz = /bits/ 64 <399999994>; 78 opp-microvolt = <800000>; 79 }; 80 opp-499999992 { 81 opp-hz = /bits/ 64 <499999992>; 82 opp-microvolt = <800000>; 83 }; 84 opp-666666656 { 85 opp-hz = /bits/ 64 <666666656>; 86 opp-microvolt = <800000>; 87 }; 88 opp-799999987 { 89 opp-hz = /bits/ 64 <799999987>; 90 opp-microvolt = <800000>; 91 }; 92 }; 93 94 psci { 95 compatible = "arm,psci-1.0"; 96 method = "smc"; 97 }; 98 99 reserved-memory { 100 #address-cells = <2>; 101 #size-cells = <2>; 102 ranges; 103 104 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 105 secmon_reserved: secmon@5000000 { 106 reg = <0x0 0x05000000 0x0 0x300000>; 107 no-map; 108 }; 109 110 /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ 111 secmon_reserved_bl32: secmon@5300000 { 112 reg = <0x0 0x05300000 0x0 0x2000000>; 113 no-map; 114 }; 115 116 linux,cma { 117 compatible = "shared-dma-pool"; 118 reusable; 119 size = <0x0 0x10000000>; 120 alignment = <0x0 0x400000>; 121 linux,cma-default; 122 }; 123 }; 124 125 sm: secure-monitor { 126 compatible = "amlogic,meson-gxbb-sm"; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 #address-cells = <2>; 132 #size-cells = <2>; 133 ranges; 134 135 pcie: pcie@fc000000 { 136 compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; 137 reg = <0x0 0xfc000000 0x0 0x400000>, 138 <0x0 0xff648000 0x0 0x2000>, 139 <0x0 0xfc400000 0x0 0x200000>; 140 reg-names = "elbi", "cfg", "config"; 141 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 142 #interrupt-cells = <1>; 143 interrupt-map-mask = <0 0 0 0>; 144 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 145 bus-range = <0x0 0xff>; 146 #address-cells = <3>; 147 #size-cells = <2>; 148 device_type = "pci"; 149 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>, 150 <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; 151 152 clocks = <&clkc CLKID_PCIE_PHY 153 &clkc CLKID_PCIE_COMB 154 &clkc CLKID_PCIE_PLL>; 155 clock-names = "general", 156 "pclk", 157 "port"; 158 resets = <&reset RESET_PCIE_CTRL_A>, 159 <&reset RESET_PCIE_APB>; 160 reset-names = "port", 161 "apb"; 162 num-lanes = <1>; 163 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; 164 phy-names = "pcie"; 165 status = "disabled"; 166 }; 167 168 ethmac: ethernet@ff3f0000 { 169 compatible = "amlogic,meson-g12a-dwmac", 170 "snps,dwmac-3.70a", 171 "snps,dwmac"; 172 reg = <0x0 0xff3f0000 0x0 0x10000>, 173 <0x0 0xff634540 0x0 0x8>; 174 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 175 interrupt-names = "macirq"; 176 clocks = <&clkc CLKID_ETH>, 177 <&clkc CLKID_FCLK_DIV2>, 178 <&clkc CLKID_MPLL2>, 179 <&clkc CLKID_FCLK_DIV2>; 180 clock-names = "stmmaceth", "clkin0", "clkin1", 181 "timing-adjustment"; 182 rx-fifo-depth = <4096>; 183 tx-fifo-depth = <2048>; 184 status = "disabled"; 185 186 mdio0: mdio { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 compatible = "snps,dwmac-mdio"; 190 }; 191 }; 192 193 apb: bus@ff600000 { 194 compatible = "simple-bus"; 195 reg = <0x0 0xff600000 0x0 0x200000>; 196 #address-cells = <2>; 197 #size-cells = <2>; 198 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 199 200 hdmi_tx: hdmi-tx@0 { 201 compatible = "amlogic,meson-g12a-dw-hdmi"; 202 reg = <0x0 0x0 0x0 0x10000>; 203 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 204 resets = <&reset RESET_HDMITX_CAPB3>, 205 <&reset RESET_HDMITX_PHY>, 206 <&reset RESET_HDMITX>; 207 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 208 clocks = <&clkc CLKID_HDMI>, 209 <&clkc CLKID_HTX_PCLK>, 210 <&clkc CLKID_VPU_INTR>; 211 clock-names = "isfr", "iahb", "venci"; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 #sound-dai-cells = <0>; 215 status = "disabled"; 216 217 /* VPU VENC Input */ 218 hdmi_tx_venc_port: port@0 { 219 reg = <0>; 220 221 hdmi_tx_in: endpoint { 222 remote-endpoint = <&hdmi_tx_out>; 223 }; 224 }; 225 226 /* TMDS Output */ 227 hdmi_tx_tmds_port: port@1 { 228 reg = <1>; 229 }; 230 }; 231 232 apb_efuse: bus@30000 { 233 compatible = "simple-bus"; 234 reg = <0x0 0x30000 0x0 0x2000>; 235 #address-cells = <2>; 236 #size-cells = <2>; 237 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 238 239 hwrng: rng@218 { 240 compatible = "amlogic,meson-rng"; 241 reg = <0x0 0x218 0x0 0x4>; 242 clocks = <&clkc CLKID_RNG0>; 243 clock-names = "core"; 244 }; 245 }; 246 247 acodec: audio-controller@32000 { 248 compatible = "amlogic,t9015"; 249 reg = <0x0 0x32000 0x0 0x14>; 250 #sound-dai-cells = <0>; 251 sound-name-prefix = "ACODEC"; 252 clocks = <&clkc CLKID_AUDIO_CODEC>; 253 clock-names = "pclk"; 254 resets = <&reset RESET_AUDIO_CODEC>; 255 status = "disabled"; 256 }; 257 258 periphs: bus@34400 { 259 compatible = "simple-bus"; 260 reg = <0x0 0x34400 0x0 0x400>; 261 #address-cells = <2>; 262 #size-cells = <2>; 263 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 264 265 periphs_pinctrl: pinctrl@40 { 266 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 267 #address-cells = <2>; 268 #size-cells = <2>; 269 ranges; 270 271 gpio: bank@40 { 272 reg = <0x0 0x40 0x0 0x4c>, 273 <0x0 0xe8 0x0 0x18>, 274 <0x0 0x120 0x0 0x18>, 275 <0x0 0x2c0 0x0 0x40>, 276 <0x0 0x340 0x0 0x1c>; 277 reg-names = "gpio", 278 "pull", 279 "pull-enable", 280 "mux", 281 "ds"; 282 gpio-controller; 283 #gpio-cells = <2>; 284 gpio-ranges = <&periphs_pinctrl 0 0 86>; 285 }; 286 287 cec_ao_a_h_pins: cec_ao_a_h { 288 mux { 289 groups = "cec_ao_a_h"; 290 function = "cec_ao_a_h"; 291 bias-disable; 292 }; 293 }; 294 295 cec_ao_b_h_pins: cec_ao_b_h { 296 mux { 297 groups = "cec_ao_b_h"; 298 function = "cec_ao_b_h"; 299 bias-disable; 300 }; 301 }; 302 303 emmc_ctrl_pins: emmc-ctrl { 304 mux-0 { 305 groups = "emmc_cmd"; 306 function = "emmc"; 307 bias-pull-up; 308 drive-strength-microamp = <4000>; 309 }; 310 311 mux-1 { 312 groups = "emmc_clk"; 313 function = "emmc"; 314 bias-disable; 315 drive-strength-microamp = <4000>; 316 }; 317 }; 318 319 emmc_data_4b_pins: emmc-data-4b { 320 mux-0 { 321 groups = "emmc_nand_d0", 322 "emmc_nand_d1", 323 "emmc_nand_d2", 324 "emmc_nand_d3"; 325 function = "emmc"; 326 bias-pull-up; 327 drive-strength-microamp = <4000>; 328 }; 329 }; 330 331 emmc_data_8b_pins: emmc-data-8b { 332 mux-0 { 333 groups = "emmc_nand_d0", 334 "emmc_nand_d1", 335 "emmc_nand_d2", 336 "emmc_nand_d3", 337 "emmc_nand_d4", 338 "emmc_nand_d5", 339 "emmc_nand_d6", 340 "emmc_nand_d7"; 341 function = "emmc"; 342 bias-pull-up; 343 drive-strength-microamp = <4000>; 344 }; 345 }; 346 347 emmc_ds_pins: emmc-ds { 348 mux { 349 groups = "emmc_nand_ds"; 350 function = "emmc"; 351 bias-pull-down; 352 drive-strength-microamp = <4000>; 353 }; 354 }; 355 356 emmc_clk_gate_pins: emmc_clk_gate { 357 mux { 358 groups = "BOOT_8"; 359 function = "gpio_periphs"; 360 bias-pull-down; 361 drive-strength-microamp = <4000>; 362 }; 363 }; 364 365 hdmitx_ddc_pins: hdmitx_ddc { 366 mux { 367 groups = "hdmitx_sda", 368 "hdmitx_sck"; 369 function = "hdmitx"; 370 bias-disable; 371 drive-strength-microamp = <4000>; 372 }; 373 }; 374 375 hdmitx_hpd_pins: hdmitx_hpd { 376 mux { 377 groups = "hdmitx_hpd_in"; 378 function = "hdmitx"; 379 bias-disable; 380 }; 381 }; 382 383 384 i2c0_sda_c_pins: i2c0-sda-c { 385 mux { 386 groups = "i2c0_sda_c"; 387 function = "i2c0"; 388 bias-disable; 389 drive-strength-microamp = <3000>; 390 391 }; 392 }; 393 394 i2c0_sck_c_pins: i2c0-sck-c { 395 mux { 396 groups = "i2c0_sck_c"; 397 function = "i2c0"; 398 bias-disable; 399 drive-strength-microamp = <3000>; 400 }; 401 }; 402 403 i2c0_sda_z0_pins: i2c0-sda-z0 { 404 mux { 405 groups = "i2c0_sda_z0"; 406 function = "i2c0"; 407 bias-disable; 408 drive-strength-microamp = <3000>; 409 }; 410 }; 411 412 i2c0_sck_z1_pins: i2c0-sck-z1 { 413 mux { 414 groups = "i2c0_sck_z1"; 415 function = "i2c0"; 416 bias-disable; 417 drive-strength-microamp = <3000>; 418 }; 419 }; 420 421 i2c0_sda_z7_pins: i2c0-sda-z7 { 422 mux { 423 groups = "i2c0_sda_z7"; 424 function = "i2c0"; 425 bias-disable; 426 drive-strength-microamp = <3000>; 427 }; 428 }; 429 430 i2c0_sda_z8_pins: i2c0-sda-z8 { 431 mux { 432 groups = "i2c0_sda_z8"; 433 function = "i2c0"; 434 bias-disable; 435 drive-strength-microamp = <3000>; 436 }; 437 }; 438 439 i2c1_sda_x_pins: i2c1-sda-x { 440 mux { 441 groups = "i2c1_sda_x"; 442 function = "i2c1"; 443 bias-disable; 444 drive-strength-microamp = <3000>; 445 }; 446 }; 447 448 i2c1_sck_x_pins: i2c1-sck-x { 449 mux { 450 groups = "i2c1_sck_x"; 451 function = "i2c1"; 452 bias-disable; 453 drive-strength-microamp = <3000>; 454 }; 455 }; 456 457 i2c1_sda_h2_pins: i2c1-sda-h2 { 458 mux { 459 groups = "i2c1_sda_h2"; 460 function = "i2c1"; 461 bias-disable; 462 drive-strength-microamp = <3000>; 463 }; 464 }; 465 466 i2c1_sck_h3_pins: i2c1-sck-h3 { 467 mux { 468 groups = "i2c1_sck_h3"; 469 function = "i2c1"; 470 bias-disable; 471 drive-strength-microamp = <3000>; 472 }; 473 }; 474 475 i2c1_sda_h6_pins: i2c1-sda-h6 { 476 mux { 477 groups = "i2c1_sda_h6"; 478 function = "i2c1"; 479 bias-disable; 480 drive-strength-microamp = <3000>; 481 }; 482 }; 483 484 i2c1_sck_h7_pins: i2c1-sck-h7 { 485 mux { 486 groups = "i2c1_sck_h7"; 487 function = "i2c1"; 488 bias-disable; 489 drive-strength-microamp = <3000>; 490 }; 491 }; 492 493 i2c2_sda_x_pins: i2c2-sda-x { 494 mux { 495 groups = "i2c2_sda_x"; 496 function = "i2c2"; 497 bias-disable; 498 drive-strength-microamp = <3000>; 499 }; 500 }; 501 502 i2c2_sck_x_pins: i2c2-sck-x { 503 mux { 504 groups = "i2c2_sck_x"; 505 function = "i2c2"; 506 bias-disable; 507 drive-strength-microamp = <3000>; 508 }; 509 }; 510 511 i2c2_sda_z_pins: i2c2-sda-z { 512 mux { 513 groups = "i2c2_sda_z"; 514 function = "i2c2"; 515 bias-disable; 516 drive-strength-microamp = <3000>; 517 }; 518 }; 519 520 i2c2_sck_z_pins: i2c2-sck-z { 521 mux { 522 groups = "i2c2_sck_z"; 523 function = "i2c2"; 524 bias-disable; 525 drive-strength-microamp = <3000>; 526 }; 527 }; 528 529 i2c3_sda_h_pins: i2c3-sda-h { 530 mux { 531 groups = "i2c3_sda_h"; 532 function = "i2c3"; 533 bias-disable; 534 drive-strength-microamp = <3000>; 535 }; 536 }; 537 538 i2c3_sck_h_pins: i2c3-sck-h { 539 mux { 540 groups = "i2c3_sck_h"; 541 function = "i2c3"; 542 bias-disable; 543 drive-strength-microamp = <3000>; 544 }; 545 }; 546 547 i2c3_sda_a_pins: i2c3-sda-a { 548 mux { 549 groups = "i2c3_sda_a"; 550 function = "i2c3"; 551 bias-disable; 552 drive-strength-microamp = <3000>; 553 }; 554 }; 555 556 i2c3_sck_a_pins: i2c3-sck-a { 557 mux { 558 groups = "i2c3_sck_a"; 559 function = "i2c3"; 560 bias-disable; 561 drive-strength-microamp = <3000>; 562 }; 563 }; 564 565 mclk0_a_pins: mclk0-a { 566 mux { 567 groups = "mclk0_a"; 568 function = "mclk0"; 569 bias-disable; 570 drive-strength-microamp = <3000>; 571 }; 572 }; 573 574 mclk1_a_pins: mclk1-a { 575 mux { 576 groups = "mclk1_a"; 577 function = "mclk1"; 578 bias-disable; 579 drive-strength-microamp = <3000>; 580 }; 581 }; 582 583 mclk1_x_pins: mclk1-x { 584 mux { 585 groups = "mclk1_x"; 586 function = "mclk1"; 587 bias-disable; 588 drive-strength-microamp = <3000>; 589 }; 590 }; 591 592 mclk1_z_pins: mclk1-z { 593 mux { 594 groups = "mclk1_z"; 595 function = "mclk1"; 596 bias-disable; 597 drive-strength-microamp = <3000>; 598 }; 599 }; 600 601 nor_pins: nor { 602 mux { 603 groups = "nor_d", 604 "nor_q", 605 "nor_c", 606 "nor_cs"; 607 function = "nor"; 608 bias-disable; 609 }; 610 }; 611 612 pdm_din0_a_pins: pdm-din0-a { 613 mux { 614 groups = "pdm_din0_a"; 615 function = "pdm"; 616 bias-disable; 617 }; 618 }; 619 620 pdm_din0_c_pins: pdm-din0-c { 621 mux { 622 groups = "pdm_din0_c"; 623 function = "pdm"; 624 bias-disable; 625 }; 626 }; 627 628 pdm_din0_x_pins: pdm-din0-x { 629 mux { 630 groups = "pdm_din0_x"; 631 function = "pdm"; 632 bias-disable; 633 }; 634 }; 635 636 pdm_din0_z_pins: pdm-din0-z { 637 mux { 638 groups = "pdm_din0_z"; 639 function = "pdm"; 640 bias-disable; 641 }; 642 }; 643 644 pdm_din1_a_pins: pdm-din1-a { 645 mux { 646 groups = "pdm_din1_a"; 647 function = "pdm"; 648 bias-disable; 649 }; 650 }; 651 652 pdm_din1_c_pins: pdm-din1-c { 653 mux { 654 groups = "pdm_din1_c"; 655 function = "pdm"; 656 bias-disable; 657 }; 658 }; 659 660 pdm_din1_x_pins: pdm-din1-x { 661 mux { 662 groups = "pdm_din1_x"; 663 function = "pdm"; 664 bias-disable; 665 }; 666 }; 667 668 pdm_din1_z_pins: pdm-din1-z { 669 mux { 670 groups = "pdm_din1_z"; 671 function = "pdm"; 672 bias-disable; 673 }; 674 }; 675 676 pdm_din2_a_pins: pdm-din2-a { 677 mux { 678 groups = "pdm_din2_a"; 679 function = "pdm"; 680 bias-disable; 681 }; 682 }; 683 684 pdm_din2_c_pins: pdm-din2-c { 685 mux { 686 groups = "pdm_din2_c"; 687 function = "pdm"; 688 bias-disable; 689 }; 690 }; 691 692 pdm_din2_x_pins: pdm-din2-x { 693 mux { 694 groups = "pdm_din2_x"; 695 function = "pdm"; 696 bias-disable; 697 }; 698 }; 699 700 pdm_din2_z_pins: pdm-din2-z { 701 mux { 702 groups = "pdm_din2_z"; 703 function = "pdm"; 704 bias-disable; 705 }; 706 }; 707 708 pdm_din3_a_pins: pdm-din3-a { 709 mux { 710 groups = "pdm_din3_a"; 711 function = "pdm"; 712 bias-disable; 713 }; 714 }; 715 716 pdm_din3_c_pins: pdm-din3-c { 717 mux { 718 groups = "pdm_din3_c"; 719 function = "pdm"; 720 bias-disable; 721 }; 722 }; 723 724 pdm_din3_x_pins: pdm-din3-x { 725 mux { 726 groups = "pdm_din3_x"; 727 function = "pdm"; 728 bias-disable; 729 }; 730 }; 731 732 pdm_din3_z_pins: pdm-din3-z { 733 mux { 734 groups = "pdm_din3_z"; 735 function = "pdm"; 736 bias-disable; 737 }; 738 }; 739 740 pdm_dclk_a_pins: pdm-dclk-a { 741 mux { 742 groups = "pdm_dclk_a"; 743 function = "pdm"; 744 bias-disable; 745 drive-strength-microamp = <500>; 746 }; 747 }; 748 749 pdm_dclk_c_pins: pdm-dclk-c { 750 mux { 751 groups = "pdm_dclk_c"; 752 function = "pdm"; 753 bias-disable; 754 drive-strength-microamp = <500>; 755 }; 756 }; 757 758 pdm_dclk_x_pins: pdm-dclk-x { 759 mux { 760 groups = "pdm_dclk_x"; 761 function = "pdm"; 762 bias-disable; 763 drive-strength-microamp = <500>; 764 }; 765 }; 766 767 pdm_dclk_z_pins: pdm-dclk-z { 768 mux { 769 groups = "pdm_dclk_z"; 770 function = "pdm"; 771 bias-disable; 772 drive-strength-microamp = <500>; 773 }; 774 }; 775 776 pwm_a_pins: pwm-a { 777 mux { 778 groups = "pwm_a"; 779 function = "pwm_a"; 780 bias-disable; 781 }; 782 }; 783 784 pwm_b_x7_pins: pwm-b-x7 { 785 mux { 786 groups = "pwm_b_x7"; 787 function = "pwm_b"; 788 bias-disable; 789 }; 790 }; 791 792 pwm_b_x19_pins: pwm-b-x19 { 793 mux { 794 groups = "pwm_b_x19"; 795 function = "pwm_b"; 796 bias-disable; 797 }; 798 }; 799 800 pwm_c_c_pins: pwm-c-c { 801 mux { 802 groups = "pwm_c_c"; 803 function = "pwm_c"; 804 bias-disable; 805 }; 806 }; 807 808 pwm_c_x5_pins: pwm-c-x5 { 809 mux { 810 groups = "pwm_c_x5"; 811 function = "pwm_c"; 812 bias-disable; 813 }; 814 }; 815 816 pwm_c_x8_pins: pwm-c-x8 { 817 mux { 818 groups = "pwm_c_x8"; 819 function = "pwm_c"; 820 bias-disable; 821 }; 822 }; 823 824 pwm_d_x3_pins: pwm-d-x3 { 825 mux { 826 groups = "pwm_d_x3"; 827 function = "pwm_d"; 828 bias-disable; 829 }; 830 }; 831 832 pwm_d_x6_pins: pwm-d-x6 { 833 mux { 834 groups = "pwm_d_x6"; 835 function = "pwm_d"; 836 bias-disable; 837 }; 838 }; 839 840 pwm_e_pins: pwm-e { 841 mux { 842 groups = "pwm_e"; 843 function = "pwm_e"; 844 bias-disable; 845 }; 846 }; 847 848 pwm_f_x_pins: pwm-f-x { 849 mux { 850 groups = "pwm_f_x"; 851 function = "pwm_f"; 852 bias-disable; 853 }; 854 }; 855 856 pwm_f_h_pins: pwm-f-h { 857 mux { 858 groups = "pwm_f_h"; 859 function = "pwm_f"; 860 bias-disable; 861 }; 862 }; 863 864 sdcard_c_pins: sdcard_c { 865 mux-0 { 866 groups = "sdcard_d0_c", 867 "sdcard_d1_c", 868 "sdcard_d2_c", 869 "sdcard_d3_c", 870 "sdcard_cmd_c"; 871 function = "sdcard"; 872 bias-pull-up; 873 drive-strength-microamp = <4000>; 874 }; 875 876 mux-1 { 877 groups = "sdcard_clk_c"; 878 function = "sdcard"; 879 bias-disable; 880 drive-strength-microamp = <4000>; 881 }; 882 }; 883 884 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 885 mux { 886 groups = "GPIOC_4"; 887 function = "gpio_periphs"; 888 bias-pull-down; 889 drive-strength-microamp = <4000>; 890 }; 891 }; 892 893 sdcard_z_pins: sdcard_z { 894 mux-0 { 895 groups = "sdcard_d0_z", 896 "sdcard_d1_z", 897 "sdcard_d2_z", 898 "sdcard_d3_z", 899 "sdcard_cmd_z"; 900 function = "sdcard"; 901 bias-pull-up; 902 drive-strength-microamp = <4000>; 903 }; 904 905 mux-1 { 906 groups = "sdcard_clk_z"; 907 function = "sdcard"; 908 bias-disable; 909 drive-strength-microamp = <4000>; 910 }; 911 }; 912 913 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 914 mux { 915 groups = "GPIOZ_6"; 916 function = "gpio_periphs"; 917 bias-pull-down; 918 drive-strength-microamp = <4000>; 919 }; 920 }; 921 922 sdio_pins: sdio { 923 mux { 924 groups = "sdio_d0", 925 "sdio_d1", 926 "sdio_d2", 927 "sdio_d3", 928 "sdio_clk", 929 "sdio_cmd"; 930 function = "sdio"; 931 bias-disable; 932 drive-strength-microamp = <4000>; 933 }; 934 }; 935 936 sdio_clk_gate_pins: sdio_clk_gate { 937 mux { 938 groups = "GPIOX_4"; 939 function = "gpio_periphs"; 940 bias-pull-down; 941 drive-strength-microamp = <4000>; 942 }; 943 }; 944 945 spdif_in_a10_pins: spdif-in-a10 { 946 mux { 947 groups = "spdif_in_a10"; 948 function = "spdif_in"; 949 bias-disable; 950 }; 951 }; 952 953 spdif_in_a12_pins: spdif-in-a12 { 954 mux { 955 groups = "spdif_in_a12"; 956 function = "spdif_in"; 957 bias-disable; 958 }; 959 }; 960 961 spdif_in_h_pins: spdif-in-h { 962 mux { 963 groups = "spdif_in_h"; 964 function = "spdif_in"; 965 bias-disable; 966 }; 967 }; 968 969 spdif_out_h_pins: spdif-out-h { 970 mux { 971 groups = "spdif_out_h"; 972 function = "spdif_out"; 973 drive-strength-microamp = <500>; 974 bias-disable; 975 }; 976 }; 977 978 spdif_out_a11_pins: spdif-out-a11 { 979 mux { 980 groups = "spdif_out_a11"; 981 function = "spdif_out"; 982 drive-strength-microamp = <500>; 983 bias-disable; 984 }; 985 }; 986 987 spdif_out_a13_pins: spdif-out-a13 { 988 mux { 989 groups = "spdif_out_a13"; 990 function = "spdif_out"; 991 drive-strength-microamp = <500>; 992 bias-disable; 993 }; 994 }; 995 996 spicc0_x_pins: spicc0-x { 997 mux { 998 groups = "spi0_mosi_x", 999 "spi0_miso_x", 1000 "spi0_clk_x"; 1001 function = "spi0"; 1002 drive-strength-microamp = <4000>; 1003 bias-disable; 1004 }; 1005 }; 1006 1007 spicc0_ss0_x_pins: spicc0-ss0-x { 1008 mux { 1009 groups = "spi0_ss0_x"; 1010 function = "spi0"; 1011 drive-strength-microamp = <4000>; 1012 bias-disable; 1013 }; 1014 }; 1015 1016 spicc0_c_pins: spicc0-c { 1017 mux { 1018 groups = "spi0_mosi_c", 1019 "spi0_miso_c", 1020 "spi0_ss0_c", 1021 "spi0_clk_c"; 1022 function = "spi0"; 1023 drive-strength-microamp = <4000>; 1024 bias-disable; 1025 }; 1026 }; 1027 1028 spicc1_pins: spicc1 { 1029 mux { 1030 groups = "spi1_mosi", 1031 "spi1_miso", 1032 "spi1_clk"; 1033 function = "spi1"; 1034 drive-strength-microamp = <4000>; 1035 }; 1036 }; 1037 1038 spicc1_ss0_pins: spicc1-ss0 { 1039 mux { 1040 groups = "spi1_ss0"; 1041 function = "spi1"; 1042 drive-strength-microamp = <4000>; 1043 bias-disable; 1044 }; 1045 }; 1046 1047 tdm_a_din0_pins: tdm-a-din0 { 1048 mux { 1049 groups = "tdm_a_din0"; 1050 function = "tdm_a"; 1051 bias-disable; 1052 }; 1053 }; 1054 1055 1056 tdm_a_din1_pins: tdm-a-din1 { 1057 mux { 1058 groups = "tdm_a_din1"; 1059 function = "tdm_a"; 1060 bias-disable; 1061 }; 1062 }; 1063 1064 tdm_a_dout0_pins: tdm-a-dout0 { 1065 mux { 1066 groups = "tdm_a_dout0"; 1067 function = "tdm_a"; 1068 bias-disable; 1069 drive-strength-microamp = <3000>; 1070 }; 1071 }; 1072 1073 tdm_a_dout1_pins: tdm-a-dout1 { 1074 mux { 1075 groups = "tdm_a_dout1"; 1076 function = "tdm_a"; 1077 bias-disable; 1078 drive-strength-microamp = <3000>; 1079 }; 1080 }; 1081 1082 tdm_a_fs_pins: tdm-a-fs { 1083 mux { 1084 groups = "tdm_a_fs"; 1085 function = "tdm_a"; 1086 bias-disable; 1087 drive-strength-microamp = <3000>; 1088 }; 1089 }; 1090 1091 tdm_a_sclk_pins: tdm-a-sclk { 1092 mux { 1093 groups = "tdm_a_sclk"; 1094 function = "tdm_a"; 1095 bias-disable; 1096 drive-strength-microamp = <3000>; 1097 }; 1098 }; 1099 1100 tdm_a_slv_fs_pins: tdm-a-slv-fs { 1101 mux { 1102 groups = "tdm_a_slv_fs"; 1103 function = "tdm_a"; 1104 bias-disable; 1105 }; 1106 }; 1107 1108 1109 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 1110 mux { 1111 groups = "tdm_a_slv_sclk"; 1112 function = "tdm_a"; 1113 bias-disable; 1114 }; 1115 }; 1116 1117 tdm_b_din0_pins: tdm-b-din0 { 1118 mux { 1119 groups = "tdm_b_din0"; 1120 function = "tdm_b"; 1121 bias-disable; 1122 }; 1123 }; 1124 1125 tdm_b_din1_pins: tdm-b-din1 { 1126 mux { 1127 groups = "tdm_b_din1"; 1128 function = "tdm_b"; 1129 bias-disable; 1130 }; 1131 }; 1132 1133 tdm_b_din2_pins: tdm-b-din2 { 1134 mux { 1135 groups = "tdm_b_din2"; 1136 function = "tdm_b"; 1137 bias-disable; 1138 }; 1139 }; 1140 1141 tdm_b_din3_a_pins: tdm-b-din3-a { 1142 mux { 1143 groups = "tdm_b_din3_a"; 1144 function = "tdm_b"; 1145 bias-disable; 1146 }; 1147 }; 1148 1149 tdm_b_din3_h_pins: tdm-b-din3-h { 1150 mux { 1151 groups = "tdm_b_din3_h"; 1152 function = "tdm_b"; 1153 bias-disable; 1154 }; 1155 }; 1156 1157 tdm_b_dout0_pins: tdm-b-dout0 { 1158 mux { 1159 groups = "tdm_b_dout0"; 1160 function = "tdm_b"; 1161 bias-disable; 1162 drive-strength-microamp = <3000>; 1163 }; 1164 }; 1165 1166 tdm_b_dout1_pins: tdm-b-dout1 { 1167 mux { 1168 groups = "tdm_b_dout1"; 1169 function = "tdm_b"; 1170 bias-disable; 1171 drive-strength-microamp = <3000>; 1172 }; 1173 }; 1174 1175 tdm_b_dout2_pins: tdm-b-dout2 { 1176 mux { 1177 groups = "tdm_b_dout2"; 1178 function = "tdm_b"; 1179 bias-disable; 1180 drive-strength-microamp = <3000>; 1181 }; 1182 }; 1183 1184 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1185 mux { 1186 groups = "tdm_b_dout3_a"; 1187 function = "tdm_b"; 1188 bias-disable; 1189 drive-strength-microamp = <3000>; 1190 }; 1191 }; 1192 1193 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1194 mux { 1195 groups = "tdm_b_dout3_h"; 1196 function = "tdm_b"; 1197 bias-disable; 1198 drive-strength-microamp = <3000>; 1199 }; 1200 }; 1201 1202 tdm_b_fs_pins: tdm-b-fs { 1203 mux { 1204 groups = "tdm_b_fs"; 1205 function = "tdm_b"; 1206 bias-disable; 1207 drive-strength-microamp = <3000>; 1208 }; 1209 }; 1210 1211 tdm_b_sclk_pins: tdm-b-sclk { 1212 mux { 1213 groups = "tdm_b_sclk"; 1214 function = "tdm_b"; 1215 bias-disable; 1216 drive-strength-microamp = <3000>; 1217 }; 1218 }; 1219 1220 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1221 mux { 1222 groups = "tdm_b_slv_fs"; 1223 function = "tdm_b"; 1224 bias-disable; 1225 }; 1226 }; 1227 1228 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1229 mux { 1230 groups = "tdm_b_slv_sclk"; 1231 function = "tdm_b"; 1232 bias-disable; 1233 }; 1234 }; 1235 1236 tdm_c_din0_a_pins: tdm-c-din0-a { 1237 mux { 1238 groups = "tdm_c_din0_a"; 1239 function = "tdm_c"; 1240 bias-disable; 1241 }; 1242 }; 1243 1244 tdm_c_din0_z_pins: tdm-c-din0-z { 1245 mux { 1246 groups = "tdm_c_din0_z"; 1247 function = "tdm_c"; 1248 bias-disable; 1249 }; 1250 }; 1251 1252 tdm_c_din1_a_pins: tdm-c-din1-a { 1253 mux { 1254 groups = "tdm_c_din1_a"; 1255 function = "tdm_c"; 1256 bias-disable; 1257 }; 1258 }; 1259 1260 tdm_c_din1_z_pins: tdm-c-din1-z { 1261 mux { 1262 groups = "tdm_c_din1_z"; 1263 function = "tdm_c"; 1264 bias-disable; 1265 }; 1266 }; 1267 1268 tdm_c_din2_a_pins: tdm-c-din2-a { 1269 mux { 1270 groups = "tdm_c_din2_a"; 1271 function = "tdm_c"; 1272 bias-disable; 1273 }; 1274 }; 1275 1276 eth_leds_pins: eth-leds { 1277 mux { 1278 groups = "eth_link_led", 1279 "eth_act_led"; 1280 function = "eth"; 1281 bias-disable; 1282 }; 1283 }; 1284 1285 eth_pins: eth { 1286 mux { 1287 groups = "eth_mdio", 1288 "eth_mdc", 1289 "eth_rgmii_rx_clk", 1290 "eth_rx_dv", 1291 "eth_rxd0", 1292 "eth_rxd1", 1293 "eth_txen", 1294 "eth_txd0", 1295 "eth_txd1"; 1296 function = "eth"; 1297 drive-strength-microamp = <4000>; 1298 bias-disable; 1299 }; 1300 }; 1301 1302 eth_rgmii_pins: eth-rgmii { 1303 mux { 1304 groups = "eth_rxd2_rgmii", 1305 "eth_rxd3_rgmii", 1306 "eth_rgmii_tx_clk", 1307 "eth_txd2_rgmii", 1308 "eth_txd3_rgmii"; 1309 function = "eth"; 1310 drive-strength-microamp = <4000>; 1311 bias-disable; 1312 }; 1313 }; 1314 1315 tdm_c_din2_z_pins: tdm-c-din2-z { 1316 mux { 1317 groups = "tdm_c_din2_z"; 1318 function = "tdm_c"; 1319 bias-disable; 1320 }; 1321 }; 1322 1323 tdm_c_din3_a_pins: tdm-c-din3-a { 1324 mux { 1325 groups = "tdm_c_din3_a"; 1326 function = "tdm_c"; 1327 bias-disable; 1328 }; 1329 }; 1330 1331 tdm_c_din3_z_pins: tdm-c-din3-z { 1332 mux { 1333 groups = "tdm_c_din3_z"; 1334 function = "tdm_c"; 1335 bias-disable; 1336 }; 1337 }; 1338 1339 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1340 mux { 1341 groups = "tdm_c_dout0_a"; 1342 function = "tdm_c"; 1343 bias-disable; 1344 drive-strength-microamp = <3000>; 1345 }; 1346 }; 1347 1348 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1349 mux { 1350 groups = "tdm_c_dout0_z"; 1351 function = "tdm_c"; 1352 bias-disable; 1353 drive-strength-microamp = <3000>; 1354 }; 1355 }; 1356 1357 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1358 mux { 1359 groups = "tdm_c_dout1_a"; 1360 function = "tdm_c"; 1361 bias-disable; 1362 drive-strength-microamp = <3000>; 1363 }; 1364 }; 1365 1366 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1367 mux { 1368 groups = "tdm_c_dout1_z"; 1369 function = "tdm_c"; 1370 bias-disable; 1371 drive-strength-microamp = <3000>; 1372 }; 1373 }; 1374 1375 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1376 mux { 1377 groups = "tdm_c_dout2_a"; 1378 function = "tdm_c"; 1379 bias-disable; 1380 drive-strength-microamp = <3000>; 1381 }; 1382 }; 1383 1384 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1385 mux { 1386 groups = "tdm_c_dout2_z"; 1387 function = "tdm_c"; 1388 bias-disable; 1389 drive-strength-microamp = <3000>; 1390 }; 1391 }; 1392 1393 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1394 mux { 1395 groups = "tdm_c_dout3_a"; 1396 function = "tdm_c"; 1397 bias-disable; 1398 drive-strength-microamp = <3000>; 1399 }; 1400 }; 1401 1402 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1403 mux { 1404 groups = "tdm_c_dout3_z"; 1405 function = "tdm_c"; 1406 bias-disable; 1407 drive-strength-microamp = <3000>; 1408 }; 1409 }; 1410 1411 tdm_c_fs_a_pins: tdm-c-fs-a { 1412 mux { 1413 groups = "tdm_c_fs_a"; 1414 function = "tdm_c"; 1415 bias-disable; 1416 drive-strength-microamp = <3000>; 1417 }; 1418 }; 1419 1420 tdm_c_fs_z_pins: tdm-c-fs-z { 1421 mux { 1422 groups = "tdm_c_fs_z"; 1423 function = "tdm_c"; 1424 bias-disable; 1425 drive-strength-microamp = <3000>; 1426 }; 1427 }; 1428 1429 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1430 mux { 1431 groups = "tdm_c_sclk_a"; 1432 function = "tdm_c"; 1433 bias-disable; 1434 drive-strength-microamp = <3000>; 1435 }; 1436 }; 1437 1438 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1439 mux { 1440 groups = "tdm_c_sclk_z"; 1441 function = "tdm_c"; 1442 bias-disable; 1443 drive-strength-microamp = <3000>; 1444 }; 1445 }; 1446 1447 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1448 mux { 1449 groups = "tdm_c_slv_fs_a"; 1450 function = "tdm_c"; 1451 bias-disable; 1452 }; 1453 }; 1454 1455 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1456 mux { 1457 groups = "tdm_c_slv_fs_z"; 1458 function = "tdm_c"; 1459 bias-disable; 1460 }; 1461 }; 1462 1463 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1464 mux { 1465 groups = "tdm_c_slv_sclk_a"; 1466 function = "tdm_c"; 1467 bias-disable; 1468 }; 1469 }; 1470 1471 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1472 mux { 1473 groups = "tdm_c_slv_sclk_z"; 1474 function = "tdm_c"; 1475 bias-disable; 1476 }; 1477 }; 1478 1479 uart_a_pins: uart-a { 1480 mux { 1481 groups = "uart_a_tx", 1482 "uart_a_rx"; 1483 function = "uart_a"; 1484 bias-disable; 1485 }; 1486 }; 1487 1488 uart_a_cts_rts_pins: uart-a-cts-rts { 1489 mux { 1490 groups = "uart_a_cts", 1491 "uart_a_rts"; 1492 function = "uart_a"; 1493 bias-disable; 1494 }; 1495 }; 1496 1497 uart_b_pins: uart-b { 1498 mux { 1499 groups = "uart_b_tx", 1500 "uart_b_rx"; 1501 function = "uart_b"; 1502 bias-disable; 1503 }; 1504 }; 1505 1506 uart_c_pins: uart-c { 1507 mux { 1508 groups = "uart_c_tx", 1509 "uart_c_rx"; 1510 function = "uart_c"; 1511 bias-disable; 1512 }; 1513 }; 1514 1515 uart_c_cts_rts_pins: uart-c-cts-rts { 1516 mux { 1517 groups = "uart_c_cts", 1518 "uart_c_rts"; 1519 function = "uart_c"; 1520 bias-disable; 1521 }; 1522 }; 1523 }; 1524 }; 1525 1526 cpu_temp: temperature-sensor@34800 { 1527 compatible = "amlogic,g12a-cpu-thermal", 1528 "amlogic,g12a-thermal"; 1529 reg = <0x0 0x34800 0x0 0x50>; 1530 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; 1531 clocks = <&clkc CLKID_TS>; 1532 #thermal-sensor-cells = <0>; 1533 amlogic,ao-secure = <&sec_AO>; 1534 }; 1535 1536 ddr_temp: temperature-sensor@34c00 { 1537 compatible = "amlogic,g12a-ddr-thermal", 1538 "amlogic,g12a-thermal"; 1539 reg = <0x0 0x34c00 0x0 0x50>; 1540 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; 1541 clocks = <&clkc CLKID_TS>; 1542 #thermal-sensor-cells = <0>; 1543 amlogic,ao-secure = <&sec_AO>; 1544 }; 1545 1546 usb2_phy0: phy@36000 { 1547 compatible = "amlogic,g12a-usb2-phy"; 1548 reg = <0x0 0x36000 0x0 0x2000>; 1549 clocks = <&xtal>; 1550 clock-names = "xtal"; 1551 resets = <&reset RESET_USB_PHY20>; 1552 reset-names = "phy"; 1553 #phy-cells = <0>; 1554 }; 1555 1556 dmc: bus@38000 { 1557 compatible = "simple-bus"; 1558 reg = <0x0 0x38000 0x0 0x400>; 1559 #address-cells = <2>; 1560 #size-cells = <2>; 1561 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1562 1563 canvas: video-lut@48 { 1564 compatible = "amlogic,canvas"; 1565 reg = <0x0 0x48 0x0 0x14>; 1566 }; 1567 }; 1568 1569 usb2_phy1: phy@3a000 { 1570 compatible = "amlogic,g12a-usb2-phy"; 1571 reg = <0x0 0x3a000 0x0 0x2000>; 1572 clocks = <&xtal>; 1573 clock-names = "xtal"; 1574 resets = <&reset RESET_USB_PHY21>; 1575 reset-names = "phy"; 1576 #phy-cells = <0>; 1577 }; 1578 1579 hiu: bus@3c000 { 1580 compatible = "simple-bus"; 1581 reg = <0x0 0x3c000 0x0 0x1400>; 1582 #address-cells = <2>; 1583 #size-cells = <2>; 1584 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1585 1586 hhi: system-controller@0 { 1587 compatible = "amlogic,meson-gx-hhi-sysctrl", 1588 "simple-mfd", "syscon"; 1589 reg = <0 0 0 0x400>; 1590 1591 clkc: clock-controller { 1592 compatible = "amlogic,g12a-clkc"; 1593 #clock-cells = <1>; 1594 clocks = <&xtal>; 1595 clock-names = "xtal"; 1596 }; 1597 1598 pwrc: power-controller { 1599 compatible = "amlogic,meson-g12a-pwrc"; 1600 #power-domain-cells = <1>; 1601 amlogic,ao-sysctrl = <&rti>; 1602 resets = <&reset RESET_VIU>, 1603 <&reset RESET_VENC>, 1604 <&reset RESET_VCBUS>, 1605 <&reset RESET_BT656>, 1606 <&reset RESET_RDMA>, 1607 <&reset RESET_VENCI>, 1608 <&reset RESET_VENCP>, 1609 <&reset RESET_VDAC>, 1610 <&reset RESET_VDI6>, 1611 <&reset RESET_VENCL>, 1612 <&reset RESET_VID_LOCK>; 1613 reset-names = "viu", "venc", "vcbus", "bt656", 1614 "rdma", "venci", "vencp", "vdac", 1615 "vdi6", "vencl", "vid_lock"; 1616 clocks = <&clkc CLKID_VPU>, 1617 <&clkc CLKID_VAPB>; 1618 clock-names = "vpu", "vapb"; 1619 /* 1620 * VPU clocking is provided by two identical clock paths 1621 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1622 * free mux to safely change frequency while running. 1623 * Same for VAPB but with a final gate after the glitch free mux. 1624 */ 1625 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1626 <&clkc CLKID_VPU_0>, 1627 <&clkc CLKID_VPU>, /* Glitch free mux */ 1628 <&clkc CLKID_VAPB_0_SEL>, 1629 <&clkc CLKID_VAPB_0>, 1630 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1631 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1632 <0>, /* Do Nothing */ 1633 <&clkc CLKID_VPU_0>, 1634 <&clkc CLKID_FCLK_DIV4>, 1635 <0>, /* Do Nothing */ 1636 <&clkc CLKID_VAPB_0>; 1637 assigned-clock-rates = <0>, /* Do Nothing */ 1638 <666666666>, 1639 <0>, /* Do Nothing */ 1640 <0>, /* Do Nothing */ 1641 <250000000>, 1642 <0>; /* Do Nothing */ 1643 }; 1644 }; 1645 }; 1646 1647 usb3_pcie_phy: phy@46000 { 1648 compatible = "amlogic,g12a-usb3-pcie-phy"; 1649 reg = <0x0 0x46000 0x0 0x2000>; 1650 clocks = <&clkc CLKID_PCIE_PLL>; 1651 clock-names = "ref_clk"; 1652 resets = <&reset RESET_PCIE_PHY>; 1653 reset-names = "phy"; 1654 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1655 assigned-clock-rates = <100000000>; 1656 #phy-cells = <1>; 1657 }; 1658 1659 eth_phy: mdio-multiplexer@4c000 { 1660 compatible = "amlogic,g12a-mdio-mux"; 1661 reg = <0x0 0x4c000 0x0 0xa4>; 1662 clocks = <&clkc CLKID_ETH_PHY>, 1663 <&xtal>, 1664 <&clkc CLKID_MPLL_50M>; 1665 clock-names = "pclk", "clkin0", "clkin1"; 1666 mdio-parent-bus = <&mdio0>; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 1670 ext_mdio: mdio@0 { 1671 reg = <0>; 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 }; 1675 1676 int_mdio: mdio@1 { 1677 reg = <1>; 1678 #address-cells = <1>; 1679 #size-cells = <0>; 1680 1681 internal_ephy: ethernet_phy@8 { 1682 compatible = "ethernet-phy-id0180.3301", 1683 "ethernet-phy-ieee802.3-c22"; 1684 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1685 reg = <8>; 1686 max-speed = <100>; 1687 }; 1688 }; 1689 }; 1690 }; 1691 1692 aobus: bus@ff800000 { 1693 compatible = "simple-bus"; 1694 reg = <0x0 0xff800000 0x0 0x100000>; 1695 #address-cells = <2>; 1696 #size-cells = <2>; 1697 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1698 1699 rti: sys-ctrl@0 { 1700 compatible = "amlogic,meson-gx-ao-sysctrl", 1701 "simple-mfd", "syscon"; 1702 reg = <0x0 0x0 0x0 0x100>; 1703 #address-cells = <2>; 1704 #size-cells = <2>; 1705 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1706 1707 clkc_AO: clock-controller { 1708 compatible = "amlogic,meson-g12a-aoclkc"; 1709 #clock-cells = <1>; 1710 #reset-cells = <1>; 1711 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1712 clock-names = "xtal", "mpeg-clk"; 1713 }; 1714 1715 ao_pinctrl: pinctrl@14 { 1716 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1717 #address-cells = <2>; 1718 #size-cells = <2>; 1719 ranges; 1720 1721 gpio_ao: bank@14 { 1722 reg = <0x0 0x14 0x0 0x8>, 1723 <0x0 0x1c 0x0 0x8>, 1724 <0x0 0x24 0x0 0x14>; 1725 reg-names = "mux", 1726 "ds", 1727 "gpio"; 1728 gpio-controller; 1729 #gpio-cells = <2>; 1730 gpio-ranges = <&ao_pinctrl 0 0 15>; 1731 }; 1732 1733 i2c_ao_sck_pins: i2c_ao_sck_pins { 1734 mux { 1735 groups = "i2c_ao_sck"; 1736 function = "i2c_ao"; 1737 bias-disable; 1738 drive-strength-microamp = <3000>; 1739 }; 1740 }; 1741 1742 i2c_ao_sda_pins: i2c_ao_sda { 1743 mux { 1744 groups = "i2c_ao_sda"; 1745 function = "i2c_ao"; 1746 bias-disable; 1747 drive-strength-microamp = <3000>; 1748 }; 1749 }; 1750 1751 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1752 mux { 1753 groups = "i2c_ao_sck_e"; 1754 function = "i2c_ao"; 1755 bias-disable; 1756 drive-strength-microamp = <3000>; 1757 }; 1758 }; 1759 1760 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1761 mux { 1762 groups = "i2c_ao_sda_e"; 1763 function = "i2c_ao"; 1764 bias-disable; 1765 drive-strength-microamp = <3000>; 1766 }; 1767 }; 1768 1769 mclk0_ao_pins: mclk0-ao { 1770 mux { 1771 groups = "mclk0_ao"; 1772 function = "mclk0_ao"; 1773 bias-disable; 1774 drive-strength-microamp = <3000>; 1775 }; 1776 }; 1777 1778 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1779 mux { 1780 groups = "tdm_ao_b_din0"; 1781 function = "tdm_ao_b"; 1782 bias-disable; 1783 }; 1784 }; 1785 1786 spdif_ao_out_pins: spdif-ao-out { 1787 mux { 1788 groups = "spdif_ao_out"; 1789 function = "spdif_ao_out"; 1790 drive-strength-microamp = <500>; 1791 bias-disable; 1792 }; 1793 }; 1794 1795 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1796 mux { 1797 groups = "tdm_ao_b_din1"; 1798 function = "tdm_ao_b"; 1799 bias-disable; 1800 }; 1801 }; 1802 1803 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1804 mux { 1805 groups = "tdm_ao_b_din2"; 1806 function = "tdm_ao_b"; 1807 bias-disable; 1808 }; 1809 }; 1810 1811 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1812 mux { 1813 groups = "tdm_ao_b_dout0"; 1814 function = "tdm_ao_b"; 1815 bias-disable; 1816 drive-strength-microamp = <3000>; 1817 }; 1818 }; 1819 1820 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1821 mux { 1822 groups = "tdm_ao_b_dout1"; 1823 function = "tdm_ao_b"; 1824 bias-disable; 1825 drive-strength-microamp = <3000>; 1826 }; 1827 }; 1828 1829 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1830 mux { 1831 groups = "tdm_ao_b_dout2"; 1832 function = "tdm_ao_b"; 1833 bias-disable; 1834 drive-strength-microamp = <3000>; 1835 }; 1836 }; 1837 1838 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1839 mux { 1840 groups = "tdm_ao_b_fs"; 1841 function = "tdm_ao_b"; 1842 bias-disable; 1843 drive-strength-microamp = <3000>; 1844 }; 1845 }; 1846 1847 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1848 mux { 1849 groups = "tdm_ao_b_sclk"; 1850 function = "tdm_ao_b"; 1851 bias-disable; 1852 drive-strength-microamp = <3000>; 1853 }; 1854 }; 1855 1856 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1857 mux { 1858 groups = "tdm_ao_b_slv_fs"; 1859 function = "tdm_ao_b"; 1860 bias-disable; 1861 }; 1862 }; 1863 1864 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1865 mux { 1866 groups = "tdm_ao_b_slv_sclk"; 1867 function = "tdm_ao_b"; 1868 bias-disable; 1869 }; 1870 }; 1871 1872 uart_ao_a_pins: uart-a-ao { 1873 mux { 1874 groups = "uart_ao_a_tx", 1875 "uart_ao_a_rx"; 1876 function = "uart_ao_a"; 1877 bias-disable; 1878 }; 1879 }; 1880 1881 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1882 mux { 1883 groups = "uart_ao_a_cts", 1884 "uart_ao_a_rts"; 1885 function = "uart_ao_a"; 1886 bias-disable; 1887 }; 1888 }; 1889 1890 pwm_a_e_pins: pwm-a-e { 1891 mux { 1892 groups = "pwm_a_e"; 1893 function = "pwm_a_e"; 1894 bias-disable; 1895 }; 1896 }; 1897 1898 pwm_ao_a_pins: pwm-ao-a { 1899 mux { 1900 groups = "pwm_ao_a"; 1901 function = "pwm_ao_a"; 1902 bias-disable; 1903 }; 1904 }; 1905 1906 pwm_ao_b_pins: pwm-ao-b { 1907 mux { 1908 groups = "pwm_ao_b"; 1909 function = "pwm_ao_b"; 1910 bias-disable; 1911 }; 1912 }; 1913 1914 pwm_ao_c_4_pins: pwm-ao-c-4 { 1915 mux { 1916 groups = "pwm_ao_c_4"; 1917 function = "pwm_ao_c"; 1918 bias-disable; 1919 }; 1920 }; 1921 1922 pwm_ao_c_6_pins: pwm-ao-c-6 { 1923 mux { 1924 groups = "pwm_ao_c_6"; 1925 function = "pwm_ao_c"; 1926 bias-disable; 1927 }; 1928 }; 1929 1930 pwm_ao_d_5_pins: pwm-ao-d-5 { 1931 mux { 1932 groups = "pwm_ao_d_5"; 1933 function = "pwm_ao_d"; 1934 bias-disable; 1935 }; 1936 }; 1937 1938 pwm_ao_d_10_pins: pwm-ao-d-10 { 1939 mux { 1940 groups = "pwm_ao_d_10"; 1941 function = "pwm_ao_d"; 1942 bias-disable; 1943 }; 1944 }; 1945 1946 pwm_ao_d_e_pins: pwm-ao-d-e { 1947 mux { 1948 groups = "pwm_ao_d_e"; 1949 function = "pwm_ao_d"; 1950 }; 1951 }; 1952 1953 remote_input_ao_pins: remote-input-ao { 1954 mux { 1955 groups = "remote_ao_input"; 1956 function = "remote_ao_input"; 1957 bias-disable; 1958 }; 1959 }; 1960 }; 1961 }; 1962 1963 vrtc: rtc@a8 { 1964 compatible = "amlogic,meson-vrtc"; 1965 reg = <0x0 0x000a8 0x0 0x4>; 1966 }; 1967 1968 cec_AO: cec@100 { 1969 compatible = "amlogic,meson-gx-ao-cec"; 1970 reg = <0x0 0x00100 0x0 0x14>; 1971 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 1972 clocks = <&clkc_AO CLKID_AO_CEC>; 1973 clock-names = "core"; 1974 status = "disabled"; 1975 }; 1976 1977 sec_AO: ao-secure@140 { 1978 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1979 reg = <0x0 0x140 0x0 0x140>; 1980 amlogic,has-chip-id; 1981 }; 1982 1983 cecb_AO: cec@280 { 1984 compatible = "amlogic,meson-g12a-ao-cec"; 1985 reg = <0x0 0x00280 0x0 0x1c>; 1986 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1987 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 1988 clock-names = "oscin"; 1989 status = "disabled"; 1990 }; 1991 1992 pwm_AO_cd: pwm@2000 { 1993 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 1994 reg = <0x0 0x2000 0x0 0x20>; 1995 #pwm-cells = <3>; 1996 status = "disabled"; 1997 }; 1998 1999 uart_AO: serial@3000 { 2000 compatible = "amlogic,meson-gx-uart", 2001 "amlogic,meson-ao-uart"; 2002 reg = <0x0 0x3000 0x0 0x18>; 2003 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2004 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2005 clock-names = "xtal", "pclk", "baud"; 2006 status = "disabled"; 2007 }; 2008 2009 uart_AO_B: serial@4000 { 2010 compatible = "amlogic,meson-gx-uart", 2011 "amlogic,meson-ao-uart"; 2012 reg = <0x0 0x4000 0x0 0x18>; 2013 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2014 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2015 clock-names = "xtal", "pclk", "baud"; 2016 status = "disabled"; 2017 }; 2018 2019 i2c_AO: i2c@5000 { 2020 compatible = "amlogic,meson-axg-i2c"; 2021 status = "disabled"; 2022 reg = <0x0 0x05000 0x0 0x20>; 2023 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2024 #address-cells = <1>; 2025 #size-cells = <0>; 2026 clocks = <&clkc CLKID_I2C>; 2027 }; 2028 2029 pwm_AO_ab: pwm@7000 { 2030 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2031 reg = <0x0 0x7000 0x0 0x20>; 2032 #pwm-cells = <3>; 2033 status = "disabled"; 2034 }; 2035 2036 ir: ir@8000 { 2037 compatible = "amlogic,meson-gxbb-ir"; 2038 reg = <0x0 0x8000 0x0 0x20>; 2039 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2040 status = "disabled"; 2041 }; 2042 2043 saradc: adc@9000 { 2044 compatible = "amlogic,meson-g12a-saradc", 2045 "amlogic,meson-saradc"; 2046 reg = <0x0 0x9000 0x0 0x48>; 2047 #io-channel-cells = <1>; 2048 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2049 clocks = <&xtal>, 2050 <&clkc_AO CLKID_AO_SAR_ADC>, 2051 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2052 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2053 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2054 status = "disabled"; 2055 }; 2056 }; 2057 2058 vdec: video-decoder@ff620000 { 2059 compatible = "amlogic,g12a-vdec"; 2060 reg = <0x0 0xff620000 0x0 0x10000>, 2061 <0x0 0xffd0e180 0x0 0xe4>; 2062 reg-names = "dos", "esparser"; 2063 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 2064 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 2065 interrupt-names = "vdec", "esparser"; 2066 2067 amlogic,ao-sysctrl = <&rti>; 2068 amlogic,canvas = <&canvas>; 2069 2070 clocks = <&clkc CLKID_PARSER>, 2071 <&clkc CLKID_DOS>, 2072 <&clkc CLKID_VDEC_1>, 2073 <&clkc CLKID_VDEC_HEVC>, 2074 <&clkc CLKID_VDEC_HEVCF>; 2075 clock-names = "dos_parser", "dos", "vdec_1", 2076 "vdec_hevc", "vdec_hevcf"; 2077 resets = <&reset RESET_PARSER>; 2078 reset-names = "esparser"; 2079 }; 2080 2081 vpu: vpu@ff900000 { 2082 compatible = "amlogic,meson-g12a-vpu"; 2083 reg = <0x0 0xff900000 0x0 0x100000>, 2084 <0x0 0xff63c000 0x0 0x1000>; 2085 reg-names = "vpu", "hhi"; 2086 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2087 #address-cells = <1>; 2088 #size-cells = <0>; 2089 amlogic,canvas = <&canvas>; 2090 2091 /* CVBS VDAC output port */ 2092 cvbs_vdac_port: port@0 { 2093 reg = <0>; 2094 }; 2095 2096 /* HDMI-TX output port */ 2097 hdmi_tx_port: port@1 { 2098 reg = <1>; 2099 2100 hdmi_tx_out: endpoint { 2101 remote-endpoint = <&hdmi_tx_in>; 2102 }; 2103 }; 2104 }; 2105 2106 gic: interrupt-controller@ffc01000 { 2107 compatible = "arm,gic-400"; 2108 reg = <0x0 0xffc01000 0 0x1000>, 2109 <0x0 0xffc02000 0 0x2000>, 2110 <0x0 0xffc04000 0 0x2000>, 2111 <0x0 0xffc06000 0 0x2000>; 2112 interrupt-controller; 2113 interrupts = <GIC_PPI 9 2114 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2115 #interrupt-cells = <3>; 2116 #address-cells = <0>; 2117 }; 2118 2119 cbus: bus@ffd00000 { 2120 compatible = "simple-bus"; 2121 reg = <0x0 0xffd00000 0x0 0x100000>; 2122 #address-cells = <2>; 2123 #size-cells = <2>; 2124 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2125 2126 reset: reset-controller@1004 { 2127 compatible = "amlogic,meson-axg-reset"; 2128 reg = <0x0 0x1004 0x0 0x9c>; 2129 #reset-cells = <1>; 2130 }; 2131 2132 gpio_intc: interrupt-controller@f080 { 2133 compatible = "amlogic,meson-g12a-gpio-intc", 2134 "amlogic,meson-gpio-intc"; 2135 reg = <0x0 0xf080 0x0 0x10>; 2136 interrupt-controller; 2137 #interrupt-cells = <2>; 2138 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2139 }; 2140 2141 watchdog: watchdog@f0d0 { 2142 compatible = "amlogic,meson-gxbb-wdt"; 2143 reg = <0x0 0xf0d0 0x0 0x10>; 2144 clocks = <&xtal>; 2145 }; 2146 2147 spicc0: spi@13000 { 2148 compatible = "amlogic,meson-g12a-spicc"; 2149 reg = <0x0 0x13000 0x0 0x44>; 2150 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2151 clocks = <&clkc CLKID_SPICC0>, 2152 <&clkc CLKID_SPICC0_SCLK>; 2153 clock-names = "core", "pclk"; 2154 #address-cells = <1>; 2155 #size-cells = <0>; 2156 status = "disabled"; 2157 }; 2158 2159 spicc1: spi@15000 { 2160 compatible = "amlogic,meson-g12a-spicc"; 2161 reg = <0x0 0x15000 0x0 0x44>; 2162 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2163 clocks = <&clkc CLKID_SPICC1>, 2164 <&clkc CLKID_SPICC1_SCLK>; 2165 clock-names = "core", "pclk"; 2166 #address-cells = <1>; 2167 #size-cells = <0>; 2168 status = "disabled"; 2169 }; 2170 2171 spifc: spi@14000 { 2172 compatible = "amlogic,meson-gxbb-spifc"; 2173 status = "disabled"; 2174 reg = <0x0 0x14000 0x0 0x80>; 2175 #address-cells = <1>; 2176 #size-cells = <0>; 2177 clocks = <&clkc CLKID_CLK81>; 2178 }; 2179 2180 pwm_ef: pwm@19000 { 2181 compatible = "amlogic,meson-g12a-ee-pwm"; 2182 reg = <0x0 0x19000 0x0 0x20>; 2183 #pwm-cells = <3>; 2184 status = "disabled"; 2185 }; 2186 2187 pwm_cd: pwm@1a000 { 2188 compatible = "amlogic,meson-g12a-ee-pwm"; 2189 reg = <0x0 0x1a000 0x0 0x20>; 2190 #pwm-cells = <3>; 2191 status = "disabled"; 2192 }; 2193 2194 pwm_ab: pwm@1b000 { 2195 compatible = "amlogic,meson-g12a-ee-pwm"; 2196 reg = <0x0 0x1b000 0x0 0x20>; 2197 #pwm-cells = <3>; 2198 status = "disabled"; 2199 }; 2200 2201 i2c3: i2c@1c000 { 2202 compatible = "amlogic,meson-axg-i2c"; 2203 status = "disabled"; 2204 reg = <0x0 0x1c000 0x0 0x20>; 2205 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2206 #address-cells = <1>; 2207 #size-cells = <0>; 2208 clocks = <&clkc CLKID_I2C>; 2209 }; 2210 2211 i2c2: i2c@1d000 { 2212 compatible = "amlogic,meson-axg-i2c"; 2213 status = "disabled"; 2214 reg = <0x0 0x1d000 0x0 0x20>; 2215 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2216 #address-cells = <1>; 2217 #size-cells = <0>; 2218 clocks = <&clkc CLKID_I2C>; 2219 }; 2220 2221 i2c1: i2c@1e000 { 2222 compatible = "amlogic,meson-axg-i2c"; 2223 status = "disabled"; 2224 reg = <0x0 0x1e000 0x0 0x20>; 2225 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2226 #address-cells = <1>; 2227 #size-cells = <0>; 2228 clocks = <&clkc CLKID_I2C>; 2229 }; 2230 2231 i2c0: i2c@1f000 { 2232 compatible = "amlogic,meson-axg-i2c"; 2233 status = "disabled"; 2234 reg = <0x0 0x1f000 0x0 0x20>; 2235 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2236 #address-cells = <1>; 2237 #size-cells = <0>; 2238 clocks = <&clkc CLKID_I2C>; 2239 }; 2240 2241 clk_msr: clock-measure@18000 { 2242 compatible = "amlogic,meson-g12a-clk-measure"; 2243 reg = <0x0 0x18000 0x0 0x10>; 2244 }; 2245 2246 uart_C: serial@22000 { 2247 compatible = "amlogic,meson-gx-uart"; 2248 reg = <0x0 0x22000 0x0 0x18>; 2249 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2250 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2251 clock-names = "xtal", "pclk", "baud"; 2252 status = "disabled"; 2253 }; 2254 2255 uart_B: serial@23000 { 2256 compatible = "amlogic,meson-gx-uart"; 2257 reg = <0x0 0x23000 0x0 0x18>; 2258 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2259 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2260 clock-names = "xtal", "pclk", "baud"; 2261 status = "disabled"; 2262 }; 2263 2264 uart_A: serial@24000 { 2265 compatible = "amlogic,meson-gx-uart"; 2266 reg = <0x0 0x24000 0x0 0x18>; 2267 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2268 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2269 clock-names = "xtal", "pclk", "baud"; 2270 status = "disabled"; 2271 fifo-size = <128>; 2272 }; 2273 }; 2274 2275 sd_emmc_a: sd@ffe03000 { 2276 compatible = "amlogic,meson-axg-mmc"; 2277 reg = <0x0 0xffe03000 0x0 0x800>; 2278 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; 2279 status = "disabled"; 2280 clocks = <&clkc CLKID_SD_EMMC_A>, 2281 <&clkc CLKID_SD_EMMC_A_CLK0>, 2282 <&clkc CLKID_FCLK_DIV2>; 2283 clock-names = "core", "clkin0", "clkin1"; 2284 resets = <&reset RESET_SD_EMMC_A>; 2285 }; 2286 2287 sd_emmc_b: sd@ffe05000 { 2288 compatible = "amlogic,meson-axg-mmc"; 2289 reg = <0x0 0xffe05000 0x0 0x800>; 2290 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2291 status = "disabled"; 2292 clocks = <&clkc CLKID_SD_EMMC_B>, 2293 <&clkc CLKID_SD_EMMC_B_CLK0>, 2294 <&clkc CLKID_FCLK_DIV2>; 2295 clock-names = "core", "clkin0", "clkin1"; 2296 resets = <&reset RESET_SD_EMMC_B>; 2297 }; 2298 2299 sd_emmc_c: mmc@ffe07000 { 2300 compatible = "amlogic,meson-axg-mmc"; 2301 reg = <0x0 0xffe07000 0x0 0x800>; 2302 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2303 status = "disabled"; 2304 clocks = <&clkc CLKID_SD_EMMC_C>, 2305 <&clkc CLKID_SD_EMMC_C_CLK0>, 2306 <&clkc CLKID_FCLK_DIV2>; 2307 clock-names = "core", "clkin0", "clkin1"; 2308 resets = <&reset RESET_SD_EMMC_C>; 2309 }; 2310 2311 usb: usb@ffe09000 { 2312 status = "disabled"; 2313 compatible = "amlogic,meson-g12a-usb-ctrl"; 2314 reg = <0x0 0xffe09000 0x0 0xa0>; 2315 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2316 #address-cells = <2>; 2317 #size-cells = <2>; 2318 ranges; 2319 2320 clocks = <&clkc CLKID_USB>; 2321 resets = <&reset RESET_USB>; 2322 2323 dr_mode = "otg"; 2324 2325 phys = <&usb2_phy0>, <&usb2_phy1>, 2326 <&usb3_pcie_phy PHY_TYPE_USB3>; 2327 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2328 2329 dwc2: usb@ff400000 { 2330 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2331 reg = <0x0 0xff400000 0x0 0x40000>; 2332 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2333 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2334 clock-names = "otg"; 2335 phys = <&usb2_phy1>; 2336 phy-names = "usb2-phy"; 2337 dr_mode = "peripheral"; 2338 g-rx-fifo-size = <192>; 2339 g-np-tx-fifo-size = <128>; 2340 g-tx-fifo-size = <128 128 16 16 16>; 2341 }; 2342 2343 dwc3: usb@ff500000 { 2344 compatible = "snps,dwc3"; 2345 reg = <0x0 0xff500000 0x0 0x100000>; 2346 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2347 dr_mode = "host"; 2348 snps,dis_u2_susphy_quirk; 2349 snps,quirk-frame-length-adjustment = <0x20>; 2350 snps,parkmode-disable-ss-quirk; 2351 }; 2352 }; 2353 2354 mali: gpu@ffe40000 { 2355 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2356 reg = <0x0 0xffe40000 0x0 0x40000>; 2357 interrupt-parent = <&gic>; 2358 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2359 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2360 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2361 interrupt-names = "job", "mmu", "gpu"; 2362 clocks = <&clkc CLKID_MALI>; 2363 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2364 operating-points-v2 = <&gpu_opp_table>; 2365 #cooling-cells = <2>; 2366 }; 2367 }; 2368 2369 thermal-zones { 2370 cpu_thermal: cpu-thermal { 2371 polling-delay = <1000>; 2372 polling-delay-passive = <100>; 2373 thermal-sensors = <&cpu_temp>; 2374 2375 trips { 2376 cpu_passive: cpu-passive { 2377 temperature = <85000>; /* millicelsius */ 2378 hysteresis = <2000>; /* millicelsius */ 2379 type = "passive"; 2380 }; 2381 2382 cpu_hot: cpu-hot { 2383 temperature = <95000>; /* millicelsius */ 2384 hysteresis = <2000>; /* millicelsius */ 2385 type = "hot"; 2386 }; 2387 2388 cpu_critical: cpu-critical { 2389 temperature = <110000>; /* millicelsius */ 2390 hysteresis = <2000>; /* millicelsius */ 2391 type = "critical"; 2392 }; 2393 }; 2394 }; 2395 2396 ddr_thermal: ddr-thermal { 2397 polling-delay = <1000>; 2398 polling-delay-passive = <100>; 2399 thermal-sensors = <&ddr_temp>; 2400 2401 trips { 2402 ddr_passive: ddr-passive { 2403 temperature = <85000>; /* millicelsius */ 2404 hysteresis = <2000>; /* millicelsius */ 2405 type = "passive"; 2406 }; 2407 2408 ddr_critical: ddr-critical { 2409 temperature = <110000>; /* millicelsius */ 2410 hysteresis = <2000>; /* millicelsius */ 2411 type = "critical"; 2412 }; 2413 }; 2414 2415 cooling-maps { 2416 map { 2417 trip = <&ddr_passive>; 2418 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2419 }; 2420 }; 2421 }; 2422 }; 2423 2424 timer { 2425 compatible = "arm,armv8-timer"; 2426 interrupts = <GIC_PPI 13 2427 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2428 <GIC_PPI 14 2429 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2430 <GIC_PPI 11 2431 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2432 <GIC_PPI 10 2433 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2434 arm,no-tick-in-suspend; 2435 }; 2436 2437 xtal: xtal-clk { 2438 compatible = "fixed-clock"; 2439 clock-frequency = <24000000>; 2440 clock-output-names = "xtal"; 2441 #clock-cells = <0>; 2442 }; 2443 2444}; 2445