1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/amlogic,a1-pll-clkc.h> 7#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h> 8#include <dt-bindings/gpio/meson-a1-gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/power/meson-a1-power.h> 12#include <dt-bindings/reset/amlogic,meson-a1-reset.h> 13 14/ { 15 compatible = "amlogic,a1"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a35"; 28 reg = <0x0 0x0>; 29 enable-method = "psci"; 30 d-cache-line-size = <32>; 31 d-cache-size = <0x8000>; 32 d-cache-sets = <32>; 33 i-cache-line-size = <32>; 34 i-cache-size = <0x8000>; 35 i-cache-sets = <32>; 36 next-level-cache = <&l2>; 37 #cooling-cells = <2>; 38 }; 39 40 cpu1: cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a35"; 43 reg = <0x0 0x1>; 44 enable-method = "psci"; 45 d-cache-line-size = <32>; 46 d-cache-size = <0x8000>; 47 d-cache-sets = <32>; 48 i-cache-line-size = <32>; 49 i-cache-size = <0x8000>; 50 i-cache-sets = <32>; 51 next-level-cache = <&l2>; 52 #cooling-cells = <2>; 53 }; 54 55 l2: l2-cache0 { 56 compatible = "cache"; 57 cache-level = <2>; 58 cache-unified; 59 cache-size = <0x80000>; /* L2. 512 KB */ 60 cache-line-size = <64>; 61 cache-sets = <512>; 62 }; 63 }; 64 65 efuse: efuse { 66 compatible = "amlogic,meson-gxbb-efuse"; 67 clocks = <&clkc_periphs CLKID_OTP>; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 secure-monitor = <&sm>; 71 power-domains = <&pwrc PWRC_OTP_ID>; 72 }; 73 74 psci { 75 compatible = "arm,psci-1.0"; 76 method = "smc"; 77 }; 78 79 reserved-memory { 80 #address-cells = <2>; 81 #size-cells = <2>; 82 ranges; 83 84 linux,cma { 85 compatible = "shared-dma-pool"; 86 reusable; 87 size = <0x0 0x800000>; 88 alignment = <0x0 0x400000>; 89 linux,cma-default; 90 }; 91 }; 92 93 sm: secure-monitor { 94 compatible = "amlogic,meson-gxbb-sm"; 95 96 pwrc: power-controller { 97 compatible = "amlogic,meson-a1-pwrc"; 98 #power-domain-cells = <1>; 99 }; 100 }; 101 102 soc { 103 compatible = "simple-bus"; 104 #address-cells = <2>; 105 #size-cells = <2>; 106 ranges; 107 108 spifc: spi@fd000400 { 109 compatible = "amlogic,a1-spifc"; 110 reg = <0x0 0xfd000400 0x0 0x290>; 111 clocks = <&clkc_periphs CLKID_SPIFC>; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 power-domains = <&pwrc PWRC_SPIFC_ID>; 115 status = "disabled"; 116 }; 117 118 apb: bus@fe000000 { 119 compatible = "simple-bus"; 120 reg = <0x0 0xfe000000 0x0 0x1000000>; 121 #address-cells = <2>; 122 #size-cells = <2>; 123 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; 124 125 reset: reset-controller@0 { 126 compatible = "amlogic,meson-a1-reset"; 127 reg = <0x0 0x0 0x0 0x8c>; 128 #reset-cells = <1>; 129 }; 130 131 periphs_pinctrl: pinctrl@400 { 132 compatible = "amlogic,meson-a1-periphs-pinctrl"; 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges; 136 137 gpio: bank@400 { 138 reg = <0x0 0x0400 0x0 0x003c>, 139 <0x0 0x0480 0x0 0x0118>; 140 reg-names = "mux", "gpio"; 141 gpio-controller; 142 #gpio-cells = <2>; 143 gpio-ranges = <&periphs_pinctrl 0 0 62>; 144 }; 145 146 i2c0_f11_pins: i2c0-f11 { 147 mux { 148 groups = "i2c0_sck_f11", 149 "i2c0_sda_f12"; 150 function = "i2c0"; 151 bias-pull-up; 152 drive-strength-microamp = <3000>; 153 }; 154 }; 155 156 i2c0_f9_pins: i2c0-f9 { 157 mux { 158 groups = "i2c0_sck_f9", 159 "i2c0_sda_f10"; 160 function = "i2c0"; 161 bias-pull-up; 162 drive-strength-microamp = <3000>; 163 }; 164 }; 165 166 i2c1_x_pins: i2c1-x { 167 mux { 168 groups = "i2c1_sck_x", 169 "i2c1_sda_x"; 170 function = "i2c1"; 171 bias-pull-up; 172 drive-strength-microamp = <3000>; 173 }; 174 }; 175 176 i2c1_a_pins: i2c1-a { 177 mux { 178 groups = "i2c1_sck_a", 179 "i2c1_sda_a"; 180 function = "i2c1"; 181 bias-pull-up; 182 drive-strength-microamp = <3000>; 183 }; 184 }; 185 186 i2c2_x0_pins: i2c2-x0 { 187 mux { 188 groups = "i2c2_sck_x0", 189 "i2c2_sda_x1"; 190 function = "i2c2"; 191 bias-pull-up; 192 drive-strength-microamp = <3000>; 193 }; 194 }; 195 196 i2c2_x15_pins: i2c2-x15 { 197 mux { 198 groups = "i2c2_sck_x15", 199 "i2c2_sda_x16"; 200 function = "i2c2"; 201 bias-pull-up; 202 drive-strength-microamp = <3000>; 203 }; 204 }; 205 206 i2c2_a4_pins: i2c2-a4 { 207 mux { 208 groups = "i2c2_sck_a4", 209 "i2c2_sda_a5"; 210 function = "i2c2"; 211 bias-pull-up; 212 drive-strength-microamp = <3000>; 213 }; 214 }; 215 216 i2c2_a8_pins: i2c2-a8 { 217 mux { 218 groups = "i2c2_sck_a8", 219 "i2c2_sda_a9"; 220 function = "i2c2"; 221 bias-pull-up; 222 drive-strength-microamp = <3000>; 223 }; 224 }; 225 226 i2c3_x_pins: i2c3-x { 227 mux { 228 groups = "i2c3_sck_x", 229 "i2c3_sda_x"; 230 function = "i2c3"; 231 bias-pull-up; 232 drive-strength-microamp = <3000>; 233 }; 234 }; 235 236 i2c3_f_pins: i2c3-f { 237 mux { 238 groups = "i2c3_sck_f", 239 "i2c3_sda_f"; 240 function = "i2c3"; 241 bias-pull-up; 242 drive-strength-microamp = <3000>; 243 }; 244 }; 245 246 uart_a_pins: uart-a { 247 mux { 248 groups = "uart_a_tx", 249 "uart_a_rx"; 250 function = "uart_a"; 251 bias-pull-up; 252 }; 253 }; 254 255 uart_a_cts_rts_pins: uart-a-cts-rts { 256 mux { 257 groups = "uart_a_cts", 258 "uart_a_rts"; 259 function = "uart_a"; 260 bias-pull-down; 261 }; 262 }; 263 264 pwm_a_pins1: pwm-a-pins1 { 265 mux { 266 groups = "pwm_a_x6"; 267 function = "pwm_a"; 268 }; 269 }; 270 271 pwm_a_pins2: pwm-a-pins2 { 272 mux { 273 groups = "pwm_a_x7"; 274 function = "pwm_a"; 275 }; 276 }; 277 278 pwm_a_pins3: pwm-a-pins3 { 279 mux { 280 groups = "pwm_a_f10"; 281 function = "pwm_a"; 282 }; 283 }; 284 285 pwm_a_pins4: pwm-a-pins4 { 286 mux { 287 groups = "pwm_a_f6"; 288 function = "pwm_a"; 289 }; 290 }; 291 292 pwm_a_pins5: pwm-a-pins5 { 293 mux { 294 groups = "pwm_a_a"; 295 function = "pwm_a"; 296 }; 297 }; 298 299 pwm_b_pins1: pwm-b-pins1 { 300 mux { 301 groups = "pwm_b_x"; 302 function = "pwm_b"; 303 }; 304 }; 305 306 pwm_b_pins2: pwm-b-pins2 { 307 mux { 308 groups = "pwm_b_f"; 309 function = "pwm_b"; 310 }; 311 }; 312 313 pwm_b_pins3: pwm-b-pins3 { 314 mux { 315 groups = "pwm_b_a"; 316 function = "pwm_b"; 317 }; 318 }; 319 320 pwm_c_pins1: pwm-c-pins1 { 321 mux { 322 groups = "pwm_c_x"; 323 function = "pwm_c"; 324 }; 325 }; 326 327 pwm_c_pins2: pwm-c-pins2 { 328 mux { 329 groups = "pwm_c_f3"; 330 function = "pwm_c"; 331 }; 332 }; 333 334 pwm_c_pins3: pwm-c-pins3 { 335 mux { 336 groups = "pwm_c_f8"; 337 function = "pwm_c"; 338 }; 339 }; 340 341 pwm_c_pins4: pwm-c-pins4 { 342 mux { 343 groups = "pwm_c_a"; 344 function = "pwm_c"; 345 }; 346 }; 347 348 pwm_d_pins1: pwm-d-pins1 { 349 mux { 350 groups = "pwm_d_x15"; 351 function = "pwm_d"; 352 }; 353 }; 354 355 pwm_d_pins2: pwm-d-pins2 { 356 mux { 357 groups = "pwm_d_x13"; 358 function = "pwm_d"; 359 }; 360 }; 361 362 pwm_d_pins3: pwm-d-pins3 { 363 mux { 364 groups = "pwm_d_x10"; 365 function = "pwm_d"; 366 }; 367 }; 368 369 pwm_d_pins4: pwm-d-pins4 { 370 mux { 371 groups = "pwm_d_f"; 372 function = "pwm_d"; 373 }; 374 }; 375 376 pwm_e_pins1: pwm-e-pins1 { 377 mux { 378 groups = "pwm_e_p"; 379 function = "pwm_e"; 380 }; 381 }; 382 383 pwm_e_pins2: pwm-e-pins2 { 384 mux { 385 groups = "pwm_e_x16"; 386 function = "pwm_e"; 387 }; 388 }; 389 390 pwm_e_pins3: pwm-e-pins3 { 391 mux { 392 groups = "pwm_e_x14"; 393 function = "pwm_e"; 394 }; 395 }; 396 397 pwm_e_pins4: pwm-e-pins4 { 398 mux { 399 groups = "pwm_e_x2"; 400 function = "pwm_e"; 401 }; 402 }; 403 404 pwm_e_pins5: pwm-e-pins5 { 405 mux { 406 groups = "pwm_e_f"; 407 function = "pwm_e"; 408 }; 409 }; 410 411 pwm_e_pins6: pwm-e-pins6 { 412 mux { 413 groups = "pwm_e_a"; 414 function = "pwm_e"; 415 }; 416 }; 417 418 pwm_f_pins1: pwm-f-pins1 { 419 mux { 420 groups = "pwm_f_b"; 421 function = "pwm_f"; 422 }; 423 }; 424 425 pwm_f_pins2: pwm-f-pins2 { 426 mux { 427 groups = "pwm_f_x"; 428 function = "pwm_f"; 429 }; 430 }; 431 432 pwm_f_pins3: pwm-f-pins3 { 433 mux { 434 groups = "pwm_f_f4"; 435 function = "pwm_f"; 436 }; 437 }; 438 439 pwm_f_pins4: pwm-f-pins4 { 440 mux { 441 groups = "pwm_f_f12"; 442 function = "pwm_f"; 443 }; 444 }; 445 446 sdio_pins: sdio { 447 mux0 { 448 groups = "sdcard_d0_x", 449 "sdcard_d1_x", 450 "sdcard_d2_x", 451 "sdcard_d3_x", 452 "sdcard_cmd_x"; 453 function = "sdcard"; 454 bias-pull-up; 455 }; 456 457 mux1 { 458 groups = "sdcard_clk_x"; 459 function = "sdcard"; 460 bias-disable; 461 }; 462 }; 463 464 sdio_clk_gate_pins: sdio-clk-gate { 465 mux { 466 groups = "sdcard_clk_x"; 467 function = "sdcard"; 468 bias-pull-down; 469 }; 470 }; 471 472 spifc_pins: spifc { 473 mux { 474 groups = "spif_mo", 475 "spif_mi", 476 "spif_clk", 477 "spif_cs", 478 "spif_hold_n", 479 "spif_wp_n"; 480 function = "spif"; 481 }; 482 }; 483 }; 484 485 gpio_intc: interrupt-controller@440 { 486 compatible = "amlogic,meson-a1-gpio-intc", 487 "amlogic,meson-gpio-intc"; 488 reg = <0x0 0x0440 0x0 0x14>; 489 interrupt-controller; 490 #interrupt-cells = <2>; 491 amlogic,channel-interrupts = 492 <49 50 51 52 53 54 55 56>; 493 }; 494 495 clkc_periphs: clock-controller@800 { 496 compatible = "amlogic,a1-peripherals-clkc"; 497 reg = <0 0x800 0 0x104>; 498 #clock-cells = <1>; 499 clocks = <&clkc_pll CLKID_FCLK_DIV2>, 500 <&clkc_pll CLKID_FCLK_DIV3>, 501 <&clkc_pll CLKID_FCLK_DIV5>, 502 <&clkc_pll CLKID_FCLK_DIV7>, 503 <&clkc_pll CLKID_HIFI_PLL>, 504 <&xtal>; 505 clock-names = "fclk_div2", "fclk_div3", 506 "fclk_div5", "fclk_div7", 507 "hifi_pll", "xtal"; 508 }; 509 510 i2c0: i2c@1400 { 511 compatible = "amlogic,meson-axg-i2c"; 512 status = "disabled"; 513 reg = <0x0 0x1400 0x0 0x20>; 514 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 clocks = <&clkc_periphs CLKID_I2C_M_A>; 518 power-domains = <&pwrc PWRC_I2C_ID>; 519 }; 520 521 uart_AO: serial@1c00 { 522 compatible = "amlogic,meson-a1-uart", 523 "amlogic,meson-ao-uart"; 524 reg = <0x0 0x1c00 0x0 0x18>; 525 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 526 clocks = <&xtal>, <&xtal>, <&xtal>; 527 clock-names = "xtal", "pclk", "baud"; 528 status = "disabled"; 529 }; 530 531 uart_AO_B: serial@2000 { 532 compatible = "amlogic,meson-a1-uart", 533 "amlogic,meson-ao-uart"; 534 reg = <0x0 0x2000 0x0 0x18>; 535 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 536 clocks = <&xtal>, <&xtal>, <&xtal>; 537 clock-names = "xtal", "pclk", "baud"; 538 status = "disabled"; 539 }; 540 541 pwm_ab: pwm@2400 { 542 compatible = "amlogic,meson-a1-pwm", 543 "amlogic,meson-s4-pwm"; 544 reg = <0x0 0x2400 0x0 0x24>; 545 #pwm-cells = <3>; 546 clocks = <&clkc_periphs CLKID_PWM_A>, 547 <&clkc_periphs CLKID_PWM_B>; 548 power-domains = <&pwrc PWRC_I2C_ID>; 549 status = "disabled"; 550 }; 551 552 pwm_cd: pwm@2800 { 553 compatible = "amlogic,meson-a1-pwm", 554 "amlogic,meson-s4-pwm"; 555 reg = <0x0 0x2800 0x0 0x24>; 556 #pwm-cells = <3>; 557 clocks = <&clkc_periphs CLKID_PWM_C>, 558 <&clkc_periphs CLKID_PWM_D>; 559 power-domains = <&pwrc PWRC_I2C_ID>; 560 status = "disabled"; 561 }; 562 563 saradc: adc@2c00 { 564 compatible = "amlogic,meson-g12a-saradc", 565 "amlogic,meson-saradc"; 566 reg = <0x0 0x2c00 0x0 0x48>; 567 #io-channel-cells = <1>; 568 power-domains = <&pwrc PWRC_I2C_ID>; 569 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; 570 clocks = <&xtal>, 571 <&clkc_periphs CLKID_SARADC_EN>, 572 <&clkc_periphs CLKID_SARADC>, 573 <&clkc_periphs CLKID_SARADC_SEL>; 574 clock-names = "clkin", "core", 575 "adc_clk", "adc_sel"; 576 status = "disabled"; 577 }; 578 579 i2c1: i2c@5c00 { 580 compatible = "amlogic,meson-axg-i2c"; 581 status = "disabled"; 582 reg = <0x0 0x5c00 0x0 0x20>; 583 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 584 #address-cells = <1>; 585 #size-cells = <0>; 586 clocks = <&clkc_periphs CLKID_I2C_M_B>; 587 power-domains = <&pwrc PWRC_I2C_ID>; 588 }; 589 590 i2c2: i2c@6800 { 591 compatible = "amlogic,meson-axg-i2c"; 592 status = "disabled"; 593 reg = <0x0 0x6800 0x0 0x20>; 594 interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 clocks = <&clkc_periphs CLKID_I2C_M_C>; 598 power-domains = <&pwrc PWRC_I2C_ID>; 599 }; 600 601 i2c3: i2c@6c00 { 602 compatible = "amlogic,meson-axg-i2c"; 603 status = "disabled"; 604 reg = <0x0 0x6c00 0x0 0x20>; 605 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 clocks = <&clkc_periphs CLKID_I2C_M_D>; 609 power-domains = <&pwrc PWRC_I2C_ID>; 610 }; 611 612 usb2_phy1: phy@4000 { 613 compatible = "amlogic,a1-usb2-phy"; 614 clocks = <&clkc_periphs CLKID_USB_PHY_IN>; 615 clock-names = "xtal"; 616 reg = <0x0 0x4000 0x0 0x60>; 617 resets = <&reset RESET_USBPHY>; 618 reset-names = "phy"; 619 #phy-cells = <0>; 620 power-domains = <&pwrc PWRC_USB_ID>; 621 }; 622 623 cpu_temp: temperature-sensor@4c00 { 624 compatible = "amlogic,a1-cpu-thermal"; 625 reg = <0x0 0x4c00 0x0 0x50>; 626 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&clkc_periphs CLKID_TS>; 628 assigned-clocks = <&clkc_periphs CLKID_TS>; 629 assigned-clock-rates = <500000>; 630 #thermal-sensor-cells = <0>; 631 amlogic,ao-secure = <&sec_AO>; 632 power-domains = <&pwrc PWRC_I2C_ID>; 633 }; 634 635 hwrng: rng@5118 { 636 compatible = "amlogic,meson-rng"; 637 reg = <0x0 0x5118 0x0 0x4>; 638 power-domains = <&pwrc PWRC_OTP_ID>; 639 }; 640 641 sec_AO: ao-secure@5a20 { 642 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 643 reg = <0x0 0x5a20 0x0 0x140>; 644 amlogic,has-chip-id; 645 }; 646 647 pwm_ef: pwm@5400 { 648 compatible = "amlogic,meson-a1-pwm", 649 "amlogic,meson-s4-pwm"; 650 reg = <0x0 0x5400 0x0 0x24>; 651 #pwm-cells = <3>; 652 clocks = <&clkc_periphs CLKID_PWM_E>, 653 <&clkc_periphs CLKID_PWM_F>; 654 power-domains = <&pwrc PWRC_I2C_ID>; 655 status = "disabled"; 656 }; 657 658 clkc_pll: pll-clock-controller@7c80 { 659 compatible = "amlogic,a1-pll-clkc"; 660 reg = <0 0x7c80 0 0x18c>; 661 #clock-cells = <1>; 662 clocks = <&clkc_periphs CLKID_FIXPLL_IN>, 663 <&clkc_periphs CLKID_HIFIPLL_IN>; 664 clock-names = "fixpll_in", "hifipll_in"; 665 }; 666 667 sd_emmc: mmc@10000 { 668 compatible = "amlogic,meson-axg-mmc"; 669 reg = <0x0 0x10000 0x0 0x800>; 670 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&clkc_periphs CLKID_SD_EMMC_A>, 672 <&clkc_periphs CLKID_SD_EMMC>, 673 <&clkc_pll CLKID_FCLK_DIV2>; 674 clock-names = "core", 675 "clkin0", 676 "clkin1"; 677 assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>; 678 assigned-clock-parents = <&xtal>; 679 resets = <&reset RESET_SD_EMMC_A>; 680 power-domains = <&pwrc PWRC_SD_EMMC_ID>; 681 status = "disabled"; 682 }; 683 }; 684 685 usb: usb@fe004400 { 686 status = "disabled"; 687 compatible = "amlogic,meson-a1-usb-ctrl"; 688 reg = <0x0 0xfe004400 0x0 0xa0>; 689 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 690 #address-cells = <2>; 691 #size-cells = <2>; 692 ranges; 693 694 clocks = <&clkc_periphs CLKID_USB_CTRL>, 695 <&clkc_periphs CLKID_USB_BUS>, 696 <&clkc_periphs CLKID_USB_CTRL_IN>; 697 clock-names = "usb_ctrl", "usb_bus", "xtal_usb_ctrl"; 698 assigned-clocks = <&clkc_periphs CLKID_USB_BUS>; 699 assigned-clock-rates = <64000000>; 700 resets = <&reset RESET_USBCTRL>; 701 702 dr_mode = "otg"; 703 704 phys = <&usb2_phy1>; 705 phy-names = "usb2-phy1"; 706 707 dwc3: usb@ff400000 { 708 compatible = "snps,dwc3"; 709 reg = <0x0 0xff400000 0x0 0x100000>; 710 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 711 dr_mode = "host"; 712 snps,dis_u2_susphy_quirk; 713 snps,quirk-frame-length-adjustment = <0x20>; 714 snps,parkmode-disable-ss-quirk; 715 }; 716 717 dwc2: usb@ff500000 { 718 compatible = "amlogic,meson-a1-usb", "snps,dwc2"; 719 reg = <0x0 0xff500000 0x0 0x40000>; 720 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 721 phys = <&usb2_phy1>; 722 phy-names = "usb2-phy"; 723 clocks = <&clkc_periphs CLKID_USB_PHY>; 724 clock-names = "otg"; 725 dr_mode = "peripheral"; 726 g-rx-fifo-size = <192>; 727 g-np-tx-fifo-size = <128>; 728 g-tx-fifo-size = <128 128 16 16 16>; 729 }; 730 }; 731 732 gic: interrupt-controller@ff901000 { 733 compatible = "arm,gic-400"; 734 reg = <0x0 0xff901000 0x0 0x1000>, 735 <0x0 0xff902000 0x0 0x2000>, 736 <0x0 0xff904000 0x0 0x2000>, 737 <0x0 0xff906000 0x0 0x2000>; 738 interrupt-controller; 739 interrupts = <GIC_PPI 9 740 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 741 #interrupt-cells = <3>; 742 #address-cells = <0>; 743 }; 744 }; 745 746 timer { 747 compatible = "arm,armv8-timer"; 748 interrupts = <GIC_PPI 13 749 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 750 <GIC_PPI 14 751 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 752 <GIC_PPI 11 753 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 754 <GIC_PPI 10 755 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 756 }; 757 758 xtal: xtal-clk { 759 compatible = "fixed-clock"; 760 clock-frequency = <24000000>; 761 clock-output-names = "xtal"; 762 #clock-cells = <0>; 763 }; 764}; 765