1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/power/amlogic,t7-pwrc.h> 8#include "amlogic-t7-reset.h" 9 10/ { 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <0x2>; 17 #size-cells = <0x0>; 18 19 cpu-map { 20 cluster0 { 21 core0 { 22 cpu = <&cpu100>; 23 }; 24 core1 { 25 cpu = <&cpu101>; 26 }; 27 core2 { 28 cpu = <&cpu102>; 29 }; 30 core3 { 31 cpu = <&cpu103>; 32 }; 33 }; 34 35 cluster1 { 36 core0 { 37 cpu = <&cpu0>; 38 }; 39 core1 { 40 cpu = <&cpu1>; 41 }; 42 core2 { 43 cpu = <&cpu2>; 44 }; 45 core3 { 46 cpu = <&cpu3>; 47 }; 48 }; 49 }; 50 51 cpu100: cpu@100 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0x0 0x100>; 55 enable-method = "psci"; 56 d-cache-line-size = <32>; 57 d-cache-size = <0x8000>; 58 d-cache-sets = <32>; 59 i-cache-line-size = <32>; 60 i-cache-size = <0x8000>; 61 i-cache-sets = <32>; 62 next-level-cache = <&l2_cache_l>; 63 }; 64 65 cpu101: cpu@101 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53"; 68 reg = <0x0 0x101>; 69 enable-method = "psci"; 70 d-cache-line-size = <32>; 71 d-cache-size = <0x8000>; 72 d-cache-sets = <32>; 73 i-cache-line-size = <32>; 74 i-cache-size = <0x8000>; 75 i-cache-sets = <32>; 76 next-level-cache = <&l2_cache_l>; 77 }; 78 79 cpu102: cpu@102 { 80 device_type = "cpu"; 81 compatible = "arm,cortex-a53"; 82 reg = <0x0 0x102>; 83 enable-method = "psci"; 84 d-cache-line-size = <32>; 85 d-cache-size = <0x8000>; 86 d-cache-sets = <32>; 87 i-cache-line-size = <32>; 88 i-cache-size = <0x8000>; 89 i-cache-sets = <32>; 90 next-level-cache = <&l2_cache_l>; 91 }; 92 93 cpu103: cpu@103 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x103>; 97 enable-method = "psci"; 98 d-cache-line-size = <32>; 99 d-cache-size = <0x8000>; 100 d-cache-sets = <32>; 101 i-cache-line-size = <32>; 102 i-cache-size = <0x8000>; 103 i-cache-sets = <32>; 104 next-level-cache = <&l2_cache_l>; 105 }; 106 107 cpu0: cpu@0 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a73"; 110 reg = <0x0 0x0>; 111 enable-method = "psci"; 112 d-cache-line-size = <64>; 113 d-cache-size = <0x10000>; 114 d-cache-sets = <64>; 115 i-cache-line-size = <64>; 116 i-cache-size = <0x10000>; 117 i-cache-sets = <64>; 118 next-level-cache = <&l2_cache_b>; 119 }; 120 121 cpu1: cpu@1 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a73"; 124 reg = <0x0 0x1>; 125 enable-method = "psci"; 126 d-cache-line-size = <64>; 127 d-cache-size = <0x10000>; 128 d-cache-sets = <64>; 129 i-cache-line-size = <64>; 130 i-cache-size = <0x10000>; 131 i-cache-sets = <64>; 132 next-level-cache = <&l2_cache_b>; 133 }; 134 135 cpu2: cpu@2 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a73"; 138 reg = <0x0 0x2>; 139 enable-method = "psci"; 140 d-cache-line-size = <64>; 141 d-cache-size = <0x10000>; 142 d-cache-sets = <64>; 143 i-cache-line-size = <64>; 144 i-cache-size = <0x10000>; 145 i-cache-sets = <64>; 146 next-level-cache = <&l2_cache_b>; 147 }; 148 149 cpu3: cpu@3 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a73"; 152 reg = <0x0 0x3>; 153 enable-method = "psci"; 154 d-cache-line-size = <64>; 155 d-cache-size = <0x10000>; 156 d-cache-sets = <64>; 157 i-cache-line-size = <64>; 158 i-cache-size = <0x10000>; 159 i-cache-sets = <64>; 160 next-level-cache = <&l2_cache_b>; 161 }; 162 163 l2_cache_l: l2-cache-cluster0 { 164 compatible = "cache"; 165 cache-level = <2>; 166 cache-unified; 167 cache-size = <0x40000>; /* L2. 256 KB */ 168 cache-line-size = <64>; 169 cache-sets = <512>; 170 }; 171 172 l2_cache_b: l2-cache-cluster1 { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 cache-size = <0x100000>; /* L2. 1 Mb */ 177 cache-line-size = <64>; 178 cache-sets = <512>; 179 }; 180 }; 181 182 timer { 183 compatible = "arm,armv8-timer"; 184 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 185 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 186 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 187 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 188 }; 189 190 psci { 191 compatible = "arm,psci-1.0"; 192 method = "smc"; 193 }; 194 195 sm: secure-monitor { 196 compatible = "amlogic,meson-gxbb-sm"; 197 198 pwrc: power-controller { 199 compatible = "amlogic,t7-pwrc"; 200 #power-domain-cells = <1>; 201 }; 202 }; 203 204 soc { 205 compatible = "simple-bus"; 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges; 209 210 gic: interrupt-controller@fff01000 { 211 compatible = "arm,gic-400"; 212 #interrupt-cells = <3>; 213 #address-cells = <0>; 214 interrupt-controller; 215 reg = <0x0 0xfff01000 0 0x1000>, 216 <0x0 0xfff02000 0 0x0100>; 217 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 218 }; 219 220 apb4: bus@fe000000 { 221 compatible = "simple-bus"; 222 reg = <0x0 0xfe000000 0x0 0x480000>; 223 #address-cells = <2>; 224 #size-cells = <2>; 225 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; 226 227 reset: reset-controller@2000 { 228 compatible = "amlogic,t7-reset"; 229 reg = <0x0 0x2000 0x0 0x98>; 230 #reset-cells = <1>; 231 }; 232 233 watchdog@2100 { 234 compatible = "amlogic,t7-wdt"; 235 reg = <0x0 0x2100 0x0 0x10>; 236 clocks = <&xtal>; 237 }; 238 239 periphs_pinctrl: pinctrl@4000 { 240 compatible = "amlogic,t7-periphs-pinctrl"; 241 #address-cells = <2>; 242 #size-cells = <2>; 243 ranges; 244 245 gpio: bank@4000 { 246 reg = <0x0 0x4000 0x0 0x0064>, 247 <0x0 0x40c0 0x0 0x0220>; 248 reg-names = "mux", "gpio"; 249 gpio-controller; 250 #gpio-cells = <2>; 251 gpio-ranges = <&periphs_pinctrl 0 0 157>; 252 }; 253 }; 254 255 gpio_intc: interrupt-controller@4080 { 256 compatible = "amlogic,t7-gpio-intc", 257 "amlogic,meson-gpio-intc"; 258 reg = <0x0 0x4080 0x0 0x20>; 259 interrupt-controller; 260 #interrupt-cells = <2>; 261 amlogic,channel-interrupts = 262 <10 11 12 13 14 15 16 17 18 19 20 21>; 263 }; 264 265 uart_a: serial@78000 { 266 compatible = "amlogic,t7-uart", "amlogic,meson-s4-uart"; 267 reg = <0x0 0x78000 0x0 0x18>; 268 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 269 status = "disabled"; 270 }; 271 272 sec_ao: ao-secure@10220 { 273 compatible = "amlogic,t7-ao-secure", 274 "amlogic,meson-gx-ao-secure", 275 "syscon"; 276 reg = <0x0 0x10220 0x0 0x140>; 277 amlogic,has-chip-id; 278 }; 279 }; 280 281 }; 282}; 283