xref: /linux/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi (revision 30bbcb44707a97fcb62246bebc8b413b5ab293f8) 
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/reset/amlogic,c3-reset.h>
10#include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
11#include <dt-bindings/clock/amlogic,c3-scmi-clkc.h>
12#include <dt-bindings/clock/amlogic,c3-peripherals-clkc.h>
13#include <dt-bindings/power/amlogic,c3-pwrc.h>
14#include <dt-bindings/gpio/amlogic-c3-gpio.h>
15
16/ {
17	cpus {
18		#address-cells = <2>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a35";
24			reg = <0x0 0x0>;
25			enable-method = "psci";
26			d-cache-line-size = <32>;
27			d-cache-size = <0x8000>;
28			d-cache-sets = <32>;
29			i-cache-line-size = <32>;
30			i-cache-size = <0x8000>;
31			i-cache-sets = <32>;
32			next-level-cache = <&l2>;
33		};
34
35		cpu1: cpu@1 {
36			device_type = "cpu";
37			compatible = "arm,cortex-a35";
38			reg = <0x0 0x1>;
39			enable-method = "psci";
40			d-cache-line-size = <32>;
41			d-cache-size = <0x8000>;
42			d-cache-sets = <32>;
43			i-cache-line-size = <32>;
44			i-cache-size = <0x8000>;
45			i-cache-sets = <32>;
46			next-level-cache = <&l2>;
47		};
48
49		l2: l2-cache0 {
50			compatible = "cache";
51			cache-level = <2>;
52			cache-unified;
53			cache-size = <0x7d000>; /* L2. 512 KB */
54			cache-line-size = <64>;
55			cache-sets = <512>;
56		};
57	};
58
59	timer {
60		compatible = "arm,armv8-timer";
61		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
62			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
63			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
64			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
65	};
66
67	psci {
68		compatible = "arm,psci-1.0";
69		method = "smc";
70	};
71
72	xtal: xtal-clk {
73		compatible = "fixed-clock";
74		clock-frequency = <24000000>;
75		clock-output-names = "xtal";
76		#clock-cells = <0>;
77	};
78
79	xtal_32k: xtal-clk-32k {
80		compatible = "fixed-clock";
81		clock-frequency = <32768>;
82		clock-output-names = "xtal_32k";
83		#clock-cells = <0>;
84	};
85
86	sm: secure-monitor {
87		compatible = "amlogic,meson-gxbb-sm";
88
89		pwrc: power-controller {
90			compatible = "amlogic,c3-pwrc";
91			#power-domain-cells = <1>;
92		};
93	};
94
95	sram@7f50e00 {
96		compatible = "mmio-sram";
97		reg = <0x0 0x07f50e00 0x0 0x100>;
98		#address-cells = <1>;
99		#size-cells = <1>;
100		ranges = <0 0x0 0x07f50e00 0x100>;
101
102		scmi_shmem: sram@0 {
103			compatible = "arm,scmi-shmem";
104			reg = <0x0 0x100>;
105		};
106	};
107
108	firmware {
109		scmi: scmi {
110			compatible = "arm,scmi-smc";
111			arm,smc-id = <0x820000C1>;
112			shmem = <&scmi_shmem>;
113			#address-cells = <1>;
114			#size-cells = <0>;
115
116			scmi_clk: protocol@14 {
117				reg = <0x14>;
118				#clock-cells = <1>;
119			};
120		};
121	};
122
123	soc {
124		compatible = "simple-bus";
125		#address-cells = <2>;
126		#size-cells = <2>;
127		ranges;
128
129		gic: interrupt-controller@fff01000 {
130			compatible = "arm,gic-400";
131			#interrupt-cells = <3>;
132			#address-cells = <0>;
133			interrupt-controller;
134			reg = <0x0 0xfff01000 0 0x1000>,
135			      <0x0 0xfff02000 0 0x2000>,
136			      <0x0 0xfff04000 0 0x2000>,
137			      <0x0 0xfff06000 0 0x2000>;
138			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
139		};
140
141		apb4: bus@fe000000 {
142			compatible = "simple-bus";
143			reg = <0x0 0xfe000000 0x0 0x480000>;
144			#address-cells = <2>;
145			#size-cells = <2>;
146			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
147
148			clkc_periphs: clock-controller@0 {
149				compatible = "amlogic,c3-peripherals-clkc";
150				reg = <0x0 0x0 0x0 0x49c>;
151				#clock-cells = <1>;
152				clocks = <&xtal>,
153					 <&scmi_clk CLKID_OSC>,
154					 <&scmi_clk CLKID_FIXED_PLL_OSC>,
155					 <&clkc_pll CLKID_FCLK_DIV2>,
156					 <&clkc_pll CLKID_FCLK_DIV2P5>,
157					 <&clkc_pll CLKID_FCLK_DIV3>,
158					 <&clkc_pll CLKID_FCLK_DIV4>,
159					 <&clkc_pll CLKID_FCLK_DIV5>,
160					 <&clkc_pll CLKID_FCLK_DIV7>,
161					 <&clkc_pll CLKID_GP0_PLL>,
162					 <&scmi_clk CLKID_GP1_PLL_OSC>,
163					 <&clkc_pll CLKID_HIFI_PLL>,
164					 <&scmi_clk CLKID_SYS_CLK>,
165					 <&scmi_clk CLKID_AXI_CLK>,
166					 <&scmi_clk CLKID_SYS_PLL_DIV16>,
167					 <&scmi_clk CLKID_CPU_CLK_DIV16>;
168				clock-names = "xtal_24m",
169					      "oscin",
170					      "fix",
171					      "fdiv2",
172					      "fdiv2p5",
173					      "fdiv3",
174					      "fdiv4",
175					      "fdiv5",
176					      "fdiv7",
177					      "gp0",
178					      "gp1",
179					      "hifi",
180					      "sysclk",
181					      "axiclk",
182					      "sysplldiv16",
183					      "cpudiv16";
184			};
185
186			reset: reset-controller@2000 {
187				compatible = "amlogic,c3-reset";
188				reg = <0x0 0x2000 0x0 0x98>;
189				#reset-cells = <1>;
190			};
191
192			watchdog@2100 {
193				compatible = "amlogic,c3-wdt", "amlogic,t7-wdt";
194				reg = <0x0 0x2100 0x0 0x10>;
195				clocks = <&xtal>;
196			};
197
198			periphs_pinctrl: pinctrl@4000 {
199				compatible = "amlogic,c3-periphs-pinctrl";
200				#address-cells = <2>;
201				#size-cells = <2>;
202				ranges = <0x0 0x0 0x0 0x4000 0x0 0x02de>;
203
204				gpio: bank@0 {
205					reg = <0x0 0x0 0x0 0x004c>,
206					      <0x0 0x100 0x0 0x01de>;
207					reg-names = "mux", "gpio";
208					gpio-controller;
209					#gpio-cells = <2>;
210					gpio-ranges = <&periphs_pinctrl 0 0 55>;
211				};
212
213				i2c0_pins1: i2c0-pins1 {
214					mux {
215						groups = "i2c0_sda_e",
216							 "i2c0_scl_e";
217						function = "i2c0";
218						bias-disable;
219						drive-strength-microamp = <3000>;
220					};
221				};
222
223				i2c0_pins2: i2c0-pins2 {
224					mux {
225						groups = "i2c0_sda_d",
226							 "i2c0_scl_d";
227						function = "i2c0";
228						bias-disable;
229						drive-strength-microamp = <3000>;
230					};
231				};
232
233				i2c1_pins1: i2c1-pins1 {
234					mux {
235						groups = "i2c1_sda_x",
236							 "i2c1_scl_x";
237						function = "i2c1";
238						bias-disable;
239						drive-strength-microamp = <3000>;
240					};
241				};
242
243				i2c1_pins2: i2c1-pins2 {
244					mux {
245						groups = "i2c1_sda_d",
246							 "i2c1_scl_d";
247						function = "i2c1";
248						bias-disable;
249						drive-strength-microamp = <3000>;
250					};
251				};
252
253				i2c1_pins3: i2c1-pins3 {
254					mux {
255						groups = "i2c1_sda_a",
256							 "i2c1_scl_a";
257						function = "i2c1";
258						bias-disable;
259						drive-strength-microamp = <3000>;
260					};
261				};
262
263				i2c1_pins4: i2c1-pins4 {
264					mux {
265						groups = "i2c1_sda_b",
266							 "i2c1_scl_b";
267						function = "i2c1";
268						bias-disable;
269						drive-strength-microamp = <3000>;
270					};
271				};
272
273				i2c2_pins1: i2c2-pins1 {
274					mux {
275						groups = "i2c2_sda",
276							 "i2c2_scl";
277						function = "i2c2";
278						bias-disable;
279						drive-strength-microamp = <3000>;
280					};
281				};
282
283				i2c3_pins1: i2c3-pins1 {
284					mux {
285						groups = "i2c3_sda_c",
286							 "i2c3_scl_c";
287						function = "i2c3";
288						bias-disable;
289						drive-strength-microamp = <3000>;
290					};
291				};
292
293				i2c3_pins2: i2c3-pins2 {
294					mux {
295						groups = "i2c3_sda_x",
296							 "i2c3_scl_x";
297						function = "i2c3";
298						bias-disable;
299						drive-strength-microamp = <3000>;
300					};
301				};
302
303				i2c3_pins3: i2c3-pins3 {
304					mux {
305						groups = "i2c3_sda_d",
306							 "i2c3_scl_d";
307						function = "i2c3";
308						bias-disable;
309						drive-strength-microamp = <3000>;
310					};
311				};
312
313				nand_pins: nand-pins {
314					mux {
315						groups = "emmc_nand_d0",
316							 "emmc_nand_d1",
317							 "emmc_nand_d2",
318							 "emmc_nand_d3",
319							 "emmc_nand_d4",
320							 "emmc_nand_d5",
321							 "emmc_nand_d6",
322							 "emmc_nand_d7",
323							 "nand_ce0",
324							 "nand_ale",
325							 "nand_cle",
326							 "nand_wen_clk",
327							 "nand_ren_wr";
328						function = "nand";
329						input-enable;
330					};
331				};
332
333				sdcard_pins: sdcard-pins {
334					mux {
335						groups = "sdcard_d0",
336							 "sdcard_d1",
337							 "sdcard_d2",
338							 "sdcard_d3",
339							 "sdcard_clk",
340							 "sdcard_cmd";
341						function = "sdcard";
342						bias-pull-up;
343						drive-strength-microamp = <4000>;
344					};
345				};
346
347				sdcard_clk_gate_pins: sdcard-clk-cmd-pins {
348					mux {
349						groups = "GPIOC_4";
350						function = "gpio_periphs";
351						bias-pull-down;
352						drive-strength-microamp = <4000>;
353					};
354				};
355
356				sdio_m_clk_gate_pins: sdio-m-clk-cmd-pins {
357					mux {
358						groups = "sdio_clk";
359						function = "sdio";
360						bias-pull-down;
361						drive-strength-microamp = <4000>;
362					};
363				};
364
365				sdio_m_pins: sdio-m-all-pins {
366					mux {
367						groups = "sdio_d0",
368							 "sdio_d1",
369							 "sdio_d2",
370							 "sdio_d3",
371							 "sdio_clk",
372							 "sdio_cmd";
373						function = "sdio";
374						input-enable;
375						bias-pull-up;
376						drive-strength-microamp = <4000>;
377					};
378				};
379
380				spicc0_pins1: spicc0-pins1 {
381					mux {
382						groups = "spi_a_mosi_b",
383							 "spi_a_miso_b",
384							 "spi_a_clk_b";
385						function = "spi_a";
386						drive-strength-microamp = <3000>;
387					};
388				};
389
390				spicc0_pins2: spicc0-pins2 {
391					mux {
392						groups = "spi_a_mosi_c",
393							 "spi_a_miso_c",
394							 "spi_a_clk_c";
395						function = "spi_a";
396						drive-strength-microamp = <3000>;
397					};
398				};
399
400				spicc0_pins3: spicc0-pins3 {
401					mux {
402						groups = "spi_a_mosi_x",
403							 "spi_a_miso_x",
404							 "spi_a_clk_x";
405						function = "spi_a";
406						drive-strength-microamp = <3000>;
407					};
408				};
409
410				spicc1_pins1: spicc1-pins1 {
411					mux {
412						groups = "spi_b_mosi_d",
413							 "spi_b_miso_d",
414							 "spi_b_clk_d";
415						function = "spi_b";
416						drive-strength-microamp = <3000>;
417					};
418				};
419
420				spicc1_pins2: spicc1-pins2 {
421					mux {
422						groups = "spi_b_mosi_x",
423							 "spi_b_miso_x",
424							 "spi_b_clk_x";
425						function = "spi_b";
426						drive-strength-microamp = <3000>;
427					};
428				};
429
430				spifc_pins: spifc-pins {
431					mux {
432						groups = "spif_mo",
433							 "spif_mi",
434							 "spif_clk",
435							 "spif_cs",
436							 "spif_hold",
437							 "spif_wp",
438							 "spif_clk_loop";
439						function = "spif";
440						drive-strength-microamp = <4000>;
441					};
442				};
443
444				pwm_a_pins1: pwm-a-pins1 {
445					mux {
446						groups = "pwm_a";
447						function = "pwm_a";
448					};
449				};
450
451				pwm_b_pins1: pwm-b-pins1 {
452					mux {
453						groups = "pwm_b";
454						function = "pwm_b";
455					};
456				};
457
458				pwm_c_pins1: pwm-c-pins1 {
459					mux {
460						groups = "pwm_c";
461						function = "pwm_c";
462					};
463				};
464
465				pwm_d_pins1: pwm-d-pins1 {
466					mux {
467						groups = "pwm_d";
468						function = "pwm_d";
469					};
470				};
471
472				pwm_e_pins1: pwm-e-pins1 {
473					mux {
474						groups = "pwm_e";
475						function = "pwm_e";
476					};
477				};
478
479				pwm_f_pins1: pwm-f-pins1 {
480					mux {
481						groups = "pwm_f";
482						function = "pwm_f";
483					};
484				};
485
486				pwm_g_pins1: pwm-g-pins1 {
487					mux {
488						groups = "pwm_g_b";
489						function = "pwm_g";
490					};
491				};
492
493				pwm_g_pins2: pwm-g-pins2 {
494					mux {
495						groups = "pwm_g_c";
496						function = "pwm_g";
497					};
498				};
499
500				pwm_g_pins3: pwm-g-pins3 {
501					mux {
502						groups = "pwm_g_d";
503						function = "pwm_g";
504					};
505				};
506
507				pwm_g_pins4: pwm-g-pins4 {
508					mux {
509						groups = "pwm_g_x0";
510						function = "pwm_g";
511					};
512				};
513
514				pwm_g_pins5: pwm-g-pins5 {
515					mux {
516						groups = "pwm_g_x8";
517						function = "pwm_g";
518					};
519				};
520
521				pwm_h_pins1: pwm-h-pins1 {
522					mux {
523						groups = "pwm_h_b";
524						function = "pwm_h";
525					};
526				};
527
528				pwm_h_pins2: pwm-h-pins2 {
529					mux {
530						groups = "pwm_h_c";
531						function = "pwm_h";
532					};
533				};
534
535				pwm_h_pins3: pwm-h-pins3 {
536					mux {
537						groups = "pwm_h_d";
538						function = "pwm_h";
539					};
540				};
541
542				pwm_h_pins4: pwm-h-pins4 {
543					mux {
544						groups = "pwm_h_x1";
545						function = "pwm_h";
546					};
547				};
548
549				pwm_h_pins5: pwm-h-pins5 {
550					mux {
551						groups = "pwm_h_x9";
552						function = "pwm_h";
553					};
554				};
555
556				pwm_i_pins1: pwm-i-pins1 {
557					mux {
558						groups = "pwm_i_b";
559						function = "pwm_i";
560					};
561				};
562
563				pwm_i_pins2: pwm-i-pins2 {
564					mux {
565						groups = "pwm_i_c";
566						function = "pwm_i";
567					};
568				};
569
570				pwm_i_pins3: pwm-i-pins3 {
571					mux {
572						groups = "pwm_i_d";
573						function = "pwm_i";
574					};
575				};
576
577				pwm_i_pins4: pwm-i-pins4 {
578					mux {
579						groups = "pwm_i_x2";
580						function = "pwm_i";
581					};
582				};
583
584				pwm_i_pins5: pwm-i-pins5 {
585					mux {
586						groups = "pwm_i_x10";
587						function = "pwm_i";
588					};
589				};
590
591				pwm_j_pins1: pwm-j-pins1 {
592					mux {
593						groups = "pwm_j_c";
594						function = "pwm_j";
595					};
596				};
597
598				pwm_j_pins2: pwm-j-pins2 {
599					mux {
600						groups = "pwm_j_d";
601						function = "pwm_j";
602					};
603				};
604
605				pwm_j_pins3: pwm-j-pins3 {
606					mux {
607						groups = "pwm_j_b";
608						function = "pwm_j";
609					};
610				};
611
612				pwm_j_pins4: pwm-j-pins4 {
613					mux {
614						groups = "pwm_j_x3";
615						function = "pwm_j";
616					};
617				};
618
619				pwm_j_pins5: pwm-j-pins5 {
620					mux {
621						groups = "pwm_j_x12";
622						function = "pwm_j";
623					};
624				};
625
626				pwm_k_pins1: pwm-k-pins1 {
627					mux {
628						groups = "pwm_k_c";
629						function = "pwm_k";
630					};
631				};
632
633				pwm_k_pins2: pwm-k-pins2 {
634					mux {
635						groups = "pwm_k_d";
636						function = "pwm_k";
637					};
638				};
639
640				pwm_k_pins3: pwm-k-pins3 {
641					mux {
642						groups = "pwm_k_b";
643						function = "pwm_k";
644					};
645				};
646
647				pwm_k_pins4: pwm-k-pins4 {
648					mux {
649						groups = "pwm_k_x4";
650						function = "pwm_k";
651					};
652				};
653
654				pwm_k_pins5: pwm-k-pins5 {
655					mux {
656						groups = "pwm_k_x13";
657						function = "pwm_k";
658					};
659				};
660
661				pwm_l_pins1: pwm-l-pins1 {
662					mux {
663						groups = "pwm_l_c";
664						function = "pwm_l";
665					};
666				};
667
668				pwm_l_pins2: pwm-l-pins2 {
669					mux {
670						groups = "pwm_l_x";
671						function = "pwm_l";
672					};
673				};
674
675				pwm_l_pins3: pwm-l-pins3 {
676					mux {
677						groups = "pwm_l_b";
678						function = "pwm_l";
679					};
680				};
681
682				pwm_l_pins4: pwm-l-pins4 {
683					mux {
684						groups = "pwm_l_a";
685						function = "pwm_l";
686					};
687				};
688
689				pwm_m_pins1: pwm-m-pins1 {
690					mux {
691						groups = "pwm_m_c";
692						function = "pwm_m";
693					};
694				};
695
696				pwm_m_pins2: pwm-m-pins2 {
697					mux {
698						groups = "pwm_m_x";
699						function = "pwm_m";
700					};
701				};
702
703				pwm_m_pins3: pwm-m-pins3 {
704					mux {
705						groups = "pwm_m_a";
706						function = "pwm_m";
707					};
708				};
709
710				pwm_m_pins4: pwm-m-pins4 {
711					mux {
712						groups = "pwm_m_b";
713						function = "pwm_m";
714					};
715				};
716
717				pwm_n_pins1: pwm-n-pins1 {
718					mux {
719						groups = "pwm_n_x";
720						function = "pwm_n";
721					};
722				};
723
724				pwm_n_pins2: pwm-n-pins2 {
725					mux {
726						groups = "pwm_n_a";
727						function = "pwm_n";
728					};
729				};
730
731				pwm_n_pins3: pwm-n-pins3 {
732					mux {
733						groups = "pwm_n_b";
734						function = "pwm_n";
735					};
736				};
737			};
738
739			gpio_intc: interrupt-controller@4080 {
740				compatible = "amlogic,c3-gpio-intc", "amlogic,meson-gpio-intc";
741				reg = <0x0 0x4080 0x0 0x0020>;
742				interrupt-controller;
743				#interrupt-cells = <2>;
744				amlogic,channel-interrupts =
745					<10 11 12 13 14 15 16 17 18 19 20 21>;
746			};
747
748			clkc_pll: clock-controller@8000 {
749				compatible = "amlogic,c3-pll-clkc";
750				reg = <0x0 0x8000 0x0 0x1a4>;
751				#clock-cells = <1>;
752				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>,
753					 <&scmi_clk CLKID_MCLK_PLL_OSC>,
754					 <&scmi_clk CLKID_FIXED_PLL_OSC>;
755				clock-names = "top",
756					      "mclk",
757					      "fix";
758			};
759
760			eth_phy: mdio-multiplexer@28000 {
761				compatible = "amlogic,g12a-mdio-mux";
762				reg = <0x0 0x28000 0x0 0xa4>;
763
764				clocks = <&clkc_periphs CLKID_SYS_ETH_PHY>,
765					 <&xtal>,
766					 <&clkc_pll CLKID_FCLK_50M>;
767				clock-names = "pclk", "clkin0", "clkin1";
768				mdio-parent-bus = <&mdio0>;
769				#address-cells = <1>;
770				#size-cells = <0>;
771
772				ext_mdio: mdio@0 {
773					reg = <0>;
774					#address-cells = <1>;
775					#size-cells = <0>;
776				};
777
778				int_mdio: mdio@1 {
779					reg = <1>;
780					#address-cells = <1>;
781					#size-cells = <0>;
782
783					internal_ephy: ethernet_phy@8 {
784						compatible = "ethernet-phy-id0180.3301",
785							     "ethernet-phy-ieee802.3-c22";
786						interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
787						reg = <8>;
788						max-speed = <100>;
789					};
790				};
791			};
792
793			clk_msr: clock-measure@48000 {
794				compatible = "amlogic,c3-clk-measure";
795				reg = <0x0 0x48000 0x0 0x1c>;
796			};
797
798			spicc0: spi@50000 {
799				compatible = "amlogic,meson-g12a-spicc";
800				reg = <0x0 0x50000 0x0 0x44>;
801				interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
802				clocks = <&clkc_periphs CLKID_SYS_SPICC_0>,
803					 <&clkc_periphs CLKID_SPICC_A>;
804				clock-names = "core", "pclk";
805				#address-cells = <1>;
806				#size-cells = <0>;
807				status = "disabled";
808			};
809
810			spicc1: spi@52000 {
811				compatible = "amlogic,meson-g12a-spicc";
812				reg = <0x0 0x52000 0x0 0x44>;
813				interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
814				clocks = <&clkc_periphs CLKID_SYS_SPICC_1>,
815					 <&clkc_periphs CLKID_SPICC_B>;
816				clock-names = "core", "pclk";
817				#address-cells = <1>;
818				#size-cells = <0>;
819				status = "disabled";
820			};
821
822			pwm_mn: pwm@54000 {
823				compatible = "amlogic,c3-pwm",
824					     "amlogic,meson-s4-pwm";
825				reg = <0x0 0x54000 0x0 0x24>;
826				clocks = <&clkc_periphs CLKID_PWM_M>,
827					 <&clkc_periphs CLKID_PWM_N>;
828				#pwm-cells = <3>;
829				status = "disabled";
830			};
831
832			spifc: spi@56000 {
833				compatible = "amlogic,a1-spifc";
834				reg = <0x0 0x56000 0x0 0x290>;
835				interrupts = <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>;
836				clocks = <&clkc_periphs CLKID_SPIFC>;
837				clock-names = "core";
838				status = "disabled";
839			};
840
841			pwm_ab: pwm@58000 {
842				compatible = "amlogic,c3-pwm",
843					     "amlogic,meson-s4-pwm";
844				reg = <0x0 0x58000 0x0 0x24>;
845				clocks = <&clkc_periphs CLKID_PWM_A>,
846					 <&clkc_periphs CLKID_PWM_B>;
847				#pwm-cells = <3>;
848				status = "disabled";
849			};
850
851			pwm_cd: pwm@5a000 {
852				compatible = "amlogic,c3-pwm",
853					     "amlogic,meson-s4-pwm";
854				reg = <0x0 0x5a000 0x0 0x24>;
855				clocks = <&clkc_periphs CLKID_PWM_C>,
856					 <&clkc_periphs CLKID_PWM_D>;
857				#pwm-cells = <3>;
858				status = "disabled";
859			};
860
861			pwm_ef: pwm@5c000 {
862				compatible = "amlogic,c3-pwm",
863					     "amlogic,meson-s4-pwm";
864				reg = <0x0 0x5c000 0x0 0x24>;
865				clocks = <&clkc_periphs CLKID_PWM_E>,
866					 <&clkc_periphs CLKID_PWM_F>;
867				#pwm-cells = <3>;
868				status = "disabled";
869			};
870
871			pwm_gh: pwm@5e000 {
872				compatible = "amlogic,c3-pwm",
873					     "amlogic,meson-s4-pwm";
874				reg = <0x0 0x5e000 0x0 0x24>;
875				clocks = <&clkc_periphs CLKID_PWM_G>,
876					 <&clkc_periphs CLKID_PWM_H>;
877				#pwm-cells = <3>;
878				status = "disabled";
879			};
880
881			pwm_ij: pwm@60000 {
882				compatible = "amlogic,c3-pwm",
883					     "amlogic,meson-s4-pwm";
884				reg = <0x0 0x60000 0x0 0x24>;
885				clocks = <&clkc_periphs CLKID_PWM_I>,
886					 <&clkc_periphs CLKID_PWM_J>;
887				#pwm-cells = <3>;
888				status = "disabled";
889			};
890
891			pwm_kl: pwm@62000 {
892				compatible = "amlogic,c3-pwm",
893					     "amlogic,meson-s4-pwm";
894				reg = <0x0 0x62000 0x0 0x24>;
895				clocks = <&clkc_periphs CLKID_PWM_K>,
896					 <&clkc_periphs CLKID_PWM_L>;
897				#pwm-cells = <3>;
898				status = "disabled";
899			};
900
901			i2c0: i2c@66000 {
902				compatible = "amlogic,meson-axg-i2c";
903				reg = <0x0 0x66000 0x0 0x24>;
904				interrupts = <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>;
905				#address-cells = <1>;
906				#size-cells = <0>;
907				clocks = <&clkc_periphs CLKID_SYS_I2C_M_A>;
908				status = "disabled";
909			};
910
911			i2c1: i2c@68000 {
912				compatible = "amlogic,meson-axg-i2c";
913				reg = <0x0 0x68000 0x0 0x24>;
914				interrupts = <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>;
915				#address-cells = <1>;
916				#size-cells = <0>;
917				clocks = <&clkc_periphs CLKID_SYS_I2C_M_B>;
918				status = "disabled";
919			};
920
921			i2c2: i2c@6a000 {
922				compatible = "amlogic,meson-axg-i2c";
923				reg = <0x0 0x6a000 0x0 0x24>;
924				interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
925				#address-cells = <1>;
926				#size-cells = <0>;
927				clocks = <&clkc_periphs CLKID_SYS_I2C_M_C>;
928				status = "disabled";
929			};
930
931			i2c3: i2c@6c000 {
932				compatible = "amlogic,meson-axg-i2c";
933				reg = <0x0 0x6c000 0x0 0x24>;
934				interrupts = <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>;
935				#address-cells = <1>;
936				#size-cells = <0>;
937				clocks = <&clkc_periphs CLKID_SYS_I2C_M_D>;
938				status = "disabled";
939			};
940
941			uart_b: serial@7a000 {
942				compatible = "amlogic,meson-s4-uart",
943					   "amlogic,meson-ao-uart";
944				reg = <0x0 0x7a000 0x0 0x18>;
945				interrupts = <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
946				status = "disabled";
947				clocks = <&xtal>, <&clkc_periphs CLKID_SYS_UART_B>, <&xtal>;
948				clock-names = "xtal", "pclk", "baud";
949			};
950
951			sec_ao: ao-secure@10220 {
952				compatible = "amlogic,c3-ao-secure",
953					     "amlogic,meson-gx-ao-secure",
954					     "syscon";
955				reg = <0x0 0x10220 0x0 0x140>;
956				amlogic,has-chip-id;
957			};
958
959			sdio: mmc@88000 {
960				compatible = "amlogic,meson-axg-mmc";
961				reg = <0x0 0x88000 0x0 0x800>;
962				interrupts = <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>;
963				power-domains = <&pwrc PWRC_C3_SDIOA_ID>;
964				clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_A>,
965					  <&clkc_periphs CLKID_SD_EMMC_A>,
966					  <&clkc_pll CLKID_FCLK_DIV2>;
967				clock-names = "core","clkin0", "clkin1";
968				no-mmc;
969				no-sd;
970				resets = <&reset RESET_SD_EMMC_A>;
971				status = "disabled";
972			};
973
974			sd: mmc@8a000 {
975				compatible = "amlogic,meson-axg-mmc";
976				reg = <0x0 0x8a000 0x0 0x800>;
977				interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
978				power-domains = <&pwrc PWRC_C3_SDCARD_ID>;
979				clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>,
980					<&clkc_periphs CLKID_SD_EMMC_B>,
981					<&clkc_pll CLKID_FCLK_DIV2>;
982				clock-names = "core", "clkin0", "clkin1";
983				no-mmc;
984				no-sdio;
985				resets = <&reset RESET_SD_EMMC_B>;
986				status = "disabled";
987			};
988
989			nand: nand-controller@8d000 {
990				compatible = "amlogic,meson-axg-nfc";
991				reg = <0x0 0x8d000 0x0 0x200>,
992					<0x0 0x8C000 0x0 0x4>;
993				reg-names = "nfc", "emmc";
994				interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
995				clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>,
996					<&clkc_pll CLKID_FCLK_DIV2>;
997				clock-names = "core", "device";
998				status = "disabled";
999			};
1000
1001			rtc@9a000 {
1002				compatible = "amlogic,c3-rtc",
1003					     "amlogic,a5-rtc";
1004				reg = <0x0 0x9a000 0x0 0x38>;
1005				interrupts = <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>;
1006				clocks = <&xtal_32k>, <&clkc_periphs CLKID_SYS_RTC>;
1007				clock-names = "osc", "sys";
1008			};
1009		};
1010
1011		ethmac: ethernet@fdc00000 {
1012			compatible = "amlogic,meson-g12a-dwmac",
1013				     "snps,dwmac-3.70a",
1014				     "snps,dwmac";
1015			reg = <0x0 0xfdc00000 0x0 0x10000>,
1016			      <0x0 0xfe024000 0x0 0x8>;
1017			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1018			interrupt-names = "macirq";
1019			power-domains = <&pwrc PWRC_C3_ETH_ID>;
1020			clocks = <&clkc_periphs CLKID_SYS_ETH_MAC>,
1021				 <&clkc_pll CLKID_FCLK_DIV2>,
1022				 <&clkc_pll CLKID_FCLK_50M>;
1023			clock-names = "stmmaceth", "clkin0", "clkin1";
1024			rx-fifo-depth = <4096>;
1025			tx-fifo-depth = <2048>;
1026			status = "disabled";
1027
1028			mdio0: mdio {
1029				compatible = "snps,dwmac-mdio";
1030				#address-cells = <1>;
1031				#size-cells = <0>;
1032			};
1033		};
1034	};
1035};
1036