1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2024 Amlogic, Inc. All rights reserved. 4 */ 5 6#include "amlogic-a4-common.dtsi" 7#include "amlogic-a4-reset.h" 8#include <dt-bindings/power/amlogic,a4-pwrc.h> 9#include <dt-bindings/pinctrl/amlogic,pinctrl.h> 10/ { 11 cpus { 12 #address-cells = <2>; 13 #size-cells = <0>; 14 15 cpu0: cpu@0 { 16 device_type = "cpu"; 17 compatible = "arm,cortex-a53"; 18 reg = <0x0 0x0>; 19 enable-method = "psci"; 20 d-cache-line-size = <32>; 21 d-cache-size = <0x8000>; 22 d-cache-sets = <32>; 23 i-cache-line-size = <32>; 24 i-cache-size = <0x8000>; 25 i-cache-sets = <32>; 26 next-level-cache = <&l2>; 27 }; 28 29 cpu1: cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a53"; 32 reg = <0x0 0x1>; 33 enable-method = "psci"; 34 d-cache-line-size = <32>; 35 d-cache-size = <0x8000>; 36 d-cache-sets = <32>; 37 i-cache-line-size = <32>; 38 i-cache-size = <0x8000>; 39 i-cache-sets = <32>; 40 next-level-cache = <&l2>; 41 }; 42 43 cpu2: cpu@2 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a53"; 46 reg = <0x0 0x2>; 47 enable-method = "psci"; 48 d-cache-line-size = <32>; 49 d-cache-size = <0x8000>; 50 d-cache-sets = <32>; 51 i-cache-line-size = <32>; 52 i-cache-size = <0x8000>; 53 i-cache-sets = <32>; 54 next-level-cache = <&l2>; 55 }; 56 57 cpu3: cpu@3 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53"; 60 reg = <0x0 0x3>; 61 enable-method = "psci"; 62 d-cache-line-size = <32>; 63 d-cache-size = <0x8000>; 64 d-cache-sets = <32>; 65 i-cache-line-size = <32>; 66 i-cache-size = <0x8000>; 67 i-cache-sets = <32>; 68 next-level-cache = <&l2>; 69 }; 70 71 l2: l2-cache0 { 72 compatible = "cache"; 73 cache-level = <2>; 74 cache-unified; 75 cache-size = <0x80000>; /* L2. 512 KB */ 76 cache-line-size = <64>; 77 cache-sets = <512>; 78 }; 79 }; 80 81 sm: secure-monitor { 82 compatible = "amlogic,meson-gxbb-sm"; 83 84 pwrc: power-controller { 85 compatible = "amlogic,a4-pwrc"; 86 #power-domain-cells = <1>; 87 }; 88 }; 89}; 90 91&apb { 92 reset: reset-controller@2000 { 93 compatible = "amlogic,a4-reset", 94 "amlogic,meson-s4-reset"; 95 reg = <0x0 0x2000 0x0 0x98>; 96 #reset-cells = <1>; 97 }; 98 99 periphs_pinctrl: pinctrl@4000 { 100 compatible = "amlogic,pinctrl-a4"; 101 #address-cells = <2>; 102 #size-cells = <2>; 103 ranges = <0x0 0x0 0x0 0x4000 0x0 0x280>; 104 105 gpiox: gpio@100 { 106 reg = <0 0x100 0 0x40>, <0 0xc 0 0xc>; 107 reg-names = "gpio", "mux"; 108 gpio-controller; 109 #gpio-cells = <2>; 110 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 18>; 111 }; 112 113 gpiot: gpio@140 { 114 reg = <0 0x140 0 0x40>, <0 0x2c 0 0xc>; 115 reg-names = "gpio", "mux"; 116 gpio-controller; 117 #gpio-cells = <2>; 118 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_T<<8) 23>; 119 }; 120 121 gpiod: gpio@180 { 122 reg = <0 0x180 0 0x40>, <0 0x40 0 0x8>; 123 reg-names = "gpio", "mux"; 124 gpio-controller; 125 #gpio-cells = <2>; 126 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 16>; 127 }; 128 129 gpioe: gpio@1c0 { 130 reg = <0 0x1c0 0 0x40>, <0 0x48 0 0x4>; 131 reg-names = "gpio", "mux"; 132 gpio-controller; 133 #gpio-cells = <2>; 134 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>; 135 }; 136 137 gpiob: gpio@240 { 138 reg = <0 0x240 0 0x40>, <0 0 0 0x8>; 139 reg-names = "gpio", "mux"; 140 gpio-controller; 141 #gpio-cells = <2>; 142 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>; 143 }; 144 145 func-uart-a { 146 uart_a_default: group-uart-a-pins1 { 147 pinmux = <AML_PINMUX(AMLOGIC_GPIO_X, 11, 1)>, 148 <AML_PINMUX(AMLOGIC_GPIO_X, 12, 1)>, 149 <AML_PINMUX(AMLOGIC_GPIO_X, 13, 1)>, 150 <AML_PINMUX(AMLOGIC_GPIO_X, 14, 1)>; 151 }; 152 153 group-uart-a-pins2 { 154 pinmux = <AML_PINMUX(AMLOGIC_GPIO_D, 2, 3)>, 155 <AML_PINMUX(AMLOGIC_GPIO_D, 3, 3)>; 156 bias-pull-up; 157 drive-strength-microamp = <4000>; 158 }; 159 }; 160 161 func-uart-b { 162 uart_b_default: group-uart-b-pins { 163 pinmux = <AML_PINMUX(AMLOGIC_GPIO_E, 0, 3)>, 164 <AML_PINMUX(AMLOGIC_GPIO_E, 1, 3)>; 165 bias-pull-up; 166 drive-strength-microamp = <4000>; 167 }; 168 }; 169 170 func-uart-d { 171 uart_d_default: group-uart-d-pins1 { 172 pinmux = <AML_PINMUX(AMLOGIC_GPIO_T, 18, 4)>, 173 <AML_PINMUX(AMLOGIC_GPIO_T, 19, 4)>; 174 bias-pull-up; 175 drive-strength-microamp = <4000>; 176 }; 177 178 group-uart-d-pins2 { 179 pinmux = <AML_PINMUX(AMLOGIC_GPIO_T, 7, 2)>, 180 <AML_PINMUX(AMLOGIC_GPIO_T, 8, 2)>, 181 <AML_PINMUX(AMLOGIC_GPIO_T, 9, 2)>, 182 <AML_PINMUX(AMLOGIC_GPIO_T, 10, 2)>; 183 bias-pull-up; 184 drive-strength-microamp = <4000>; 185 }; 186 }; 187 188 func-uart-e { 189 uart_e_default: group-uart-e-pins { 190 pinmux = <AML_PINMUX(AMLOGIC_GPIO_T, 14, 3)>, 191 <AML_PINMUX(AMLOGIC_GPIO_T, 15, 3)>, 192 <AML_PINMUX(AMLOGIC_GPIO_T, 16, 3)>, 193 <AML_PINMUX(AMLOGIC_GPIO_T, 17, 3)>; 194 bias-pull-up; 195 drive-strength-microamp = <4000>; 196 }; 197 }; 198 }; 199 200 gpio_intc: interrupt-controller@4080 { 201 compatible = "amlogic,a4-gpio-intc", 202 "amlogic,meson-gpio-intc"; 203 reg = <0x0 0x4080 0x0 0x20>; 204 interrupt-controller; 205 #interrupt-cells = <2>; 206 amlogic,channel-interrupts = 207 <10 11 12 13 14 15 16 17 18 19 20 21>; 208 }; 209 210 ao_pinctrl: pinctrl@8e700 { 211 compatible = "amlogic,pinctrl-a4"; 212 #address-cells = <2>; 213 #size-cells = <2>; 214 ranges = <0x0 0x0 0x0 0x8e700 0x0 0x80>; 215 216 gpioao: gpio@4 { 217 reg = <0 0x4 0 0x16>, <0 0 0 0x4>; 218 reg-names = "gpio", "mux"; 219 gpio-controller; 220 #gpio-cells = <2>; 221 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_AO<<8) 7>; 222 }; 223 224 test_n: gpio@44 { 225 reg = <0 0x44 0 0x20>; 226 reg-names = "gpio"; 227 gpio-controller; 228 #gpio-cells = <2>; 229 gpio-ranges = <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>; 230 }; 231 }; 232 233 gpio_ao_intc: interrupt-controller@8e72c { 234 compatible = "amlogic,a4-gpio-ao-intc", 235 "amlogic,meson-gpio-intc"; 236 reg = <0x0 0x8e72c 0x0 0x0c>; 237 interrupt-controller; 238 #interrupt-cells = <2>; 239 amlogic,channel-interrupts = <140 141>; 240 }; 241}; 242