xref: /linux/arch/arm64/boot/dts/amlogic/amlogic-a4-reset.h (revision ec71f661a572a770d7c861cd52a50cbbb0e1a8d1)
1*946b5188SZelong Dong /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2*946b5188SZelong Dong /*
3*946b5188SZelong Dong  * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
4*946b5188SZelong Dong  */
5*946b5188SZelong Dong 
6*946b5188SZelong Dong #ifndef __DTS_AMLOGIC_A4_RESET_H
7*946b5188SZelong Dong #define __DTS_AMLOGIC_A4_RESET_H
8*946b5188SZelong Dong 
9*946b5188SZelong Dong /* RESET0 */
10*946b5188SZelong Dong /*						0-3 */
11*946b5188SZelong Dong #define RESET_USB				4
12*946b5188SZelong Dong /*						5-6*/
13*946b5188SZelong Dong #define RESET_U2PHY22				7
14*946b5188SZelong Dong #define RESET_USBPHY20				8
15*946b5188SZelong Dong #define RESET_U2PHY21				9
16*946b5188SZelong Dong #define RESET_USB2DRD				10
17*946b5188SZelong Dong #define RESET_U2H				11
18*946b5188SZelong Dong #define RESET_LED_CTRL				12
19*946b5188SZelong Dong /*						13-31 */
20*946b5188SZelong Dong 
21*946b5188SZelong Dong /* RESET1 */
22*946b5188SZelong Dong #define RESET_AUDIO				32
23*946b5188SZelong Dong #define RESET_AUDIO_VAD				33
24*946b5188SZelong Dong /*						34*/
25*946b5188SZelong Dong #define RESET_DDR_APB				35
26*946b5188SZelong Dong #define RESET_DDR				36
27*946b5188SZelong Dong #define RESET_VOUT_VENC				37
28*946b5188SZelong Dong #define RESET_VOUT				38
29*946b5188SZelong Dong /*						39-47 */
30*946b5188SZelong Dong #define RESET_ETHERNET				48
31*946b5188SZelong Dong /*						49-63 */
32*946b5188SZelong Dong 
33*946b5188SZelong Dong /* RESET2 */
34*946b5188SZelong Dong #define RESET_DEVICE_MMC_ARB			64
35*946b5188SZelong Dong #define RESET_IRCTRL				65
36*946b5188SZelong Dong /*						66*/
37*946b5188SZelong Dong #define RESET_TS_PLL				67
38*946b5188SZelong Dong /*						68-72*/
39*946b5188SZelong Dong #define RESET_SPICC_0				73
40*946b5188SZelong Dong #define RESET_SPICC_1				74
41*946b5188SZelong Dong /*						75-79*/
42*946b5188SZelong Dong #define RESET_MSR_CLK				80
43*946b5188SZelong Dong /*						81*/
44*946b5188SZelong Dong #define RESET_SAR_ADC				82
45*946b5188SZelong Dong /*						83-87*/
46*946b5188SZelong Dong #define RESET_ACODEC				88
47*946b5188SZelong Dong /*						89-90*/
48*946b5188SZelong Dong #define RESET_WATCHDOG				91
49*946b5188SZelong Dong /*						92-95*/
50*946b5188SZelong Dong 
51*946b5188SZelong Dong /* RESET3 */
52*946b5188SZelong Dong /*						96-127 */
53*946b5188SZelong Dong 
54*946b5188SZelong Dong /* RESET4 */
55*946b5188SZelong Dong /*						128-131 */
56*946b5188SZelong Dong #define RESET_PWM_AB				132
57*946b5188SZelong Dong #define RESET_PWM_CD				133
58*946b5188SZelong Dong #define RESET_PWM_EF				134
59*946b5188SZelong Dong #define RESET_PWM_GH				135
60*946b5188SZelong Dong /*						136-137*/
61*946b5188SZelong Dong #define RESET_UART_A				138
62*946b5188SZelong Dong #define RESET_UART_B				139
63*946b5188SZelong Dong /*						140*/
64*946b5188SZelong Dong #define RESET_UART_D				141
65*946b5188SZelong Dong #define RESET_UART_E				142
66*946b5188SZelong Dong /*						143-144*/
67*946b5188SZelong Dong #define RESET_I2C_M_A				145
68*946b5188SZelong Dong #define RESET_I2C_M_B				146
69*946b5188SZelong Dong #define RESET_I2C_M_C				147
70*946b5188SZelong Dong #define RESET_I2C_M_D				148
71*946b5188SZelong Dong /*						149-151*/
72*946b5188SZelong Dong #define RESET_SDEMMC_A				152
73*946b5188SZelong Dong /*						153*/
74*946b5188SZelong Dong #define RESET_SDEMMC_C				154
75*946b5188SZelong Dong /*						155-159*/
76*946b5188SZelong Dong 
77*946b5188SZelong Dong /* RESET5 */
78*946b5188SZelong Dong /*						160-175*/
79*946b5188SZelong Dong #define RESET_BRG_AO_NIC_SYS			176
80*946b5188SZelong Dong /*						177*/
81*946b5188SZelong Dong #define RESET_BRG_AO_NIC_MAIN			178
82*946b5188SZelong Dong #define RESET_BRG_AO_NIC_AUDIO			179
83*946b5188SZelong Dong /*						180-183*/
84*946b5188SZelong Dong #define RESET_BRG_AO_NIC_ALL			184
85*946b5188SZelong Dong /*						185*/
86*946b5188SZelong Dong #define RESET_BRG_NIC_SDIO			186
87*946b5188SZelong Dong #define RESET_BRG_NIC_EMMC			187
88*946b5188SZelong Dong #define RESET_BRG_NIC_DSU			188
89*946b5188SZelong Dong #define RESET_BRG_NIC_CLK81			189
90*946b5188SZelong Dong #define RESET_BRG_NIC_MAIN			190
91*946b5188SZelong Dong #define RESET_BRG_NIC_ALL			191
92*946b5188SZelong Dong 
93*946b5188SZelong Dong #endif
94