1/* 2 * DTS file for AMD Seattle XGBE (RevB) 3 * 4 * Copyright (C) 2015 Advanced Micro Devices, Inc. 5 */ 6 7 xgmacclk0_dma_250mhz: clk250mhz_0 { 8 compatible = "fixed-clock"; 9 #clock-cells = <0>; 10 clock-frequency = <250000000>; 11 clock-output-names = "xgmacclk0_dma_250mhz"; 12 }; 13 14 xgmacclk0_ptp_250mhz: clk250mhz_1 { 15 compatible = "fixed-clock"; 16 #clock-cells = <0>; 17 clock-frequency = <250000000>; 18 clock-output-names = "xgmacclk0_ptp_250mhz"; 19 }; 20 21 xgmacclk1_dma_250mhz: clk250mhz_2 { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <250000000>; 25 clock-output-names = "xgmacclk1_dma_250mhz"; 26 }; 27 28 xgmacclk1_ptp_250mhz: clk250mhz_3 { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <250000000>; 32 clock-output-names = "xgmacclk1_ptp_250mhz"; 33 }; 34 35 xgmac0: xgmac@e0700000 { 36 compatible = "amd,xgbe-seattle-v1a"; 37 reg = <0 0xe0700000 0 0x80000>, 38 <0 0xe0780000 0 0x80000>, 39 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */ 40 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */ 41 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */ 42 interrupts = <0 325 4>, 43 <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>, 44 <0 323 4>; 45 amd,per-channel-interrupt; 46 amd,speed-set = <0>; 47 amd,serdes-blwc = <1>, <1>, <0>; 48 amd,serdes-cdr-rate = <2>, <2>, <7>; 49 amd,serdes-pq-skew = <10>, <10>, <18>; 50 amd,serdes-tx-amp = <0>, <0>, <0>; 51 amd,serdes-dfe-tap-config = <3>, <3>, <3>; 52 amd,serdes-dfe-tap-enable = <0>, <0>, <7>; 53 mac-address = [ 02 A1 A2 A3 A4 A5 ]; 54 clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>; 55 clock-names = "dma_clk", "ptp_clk"; 56 phy-mode = "xgmii"; 57 #stream-id-cells = <16>; 58 dma-coherent; 59 }; 60 61 xgmac1: xgmac@e0900000 { 62 compatible = "amd,xgbe-seattle-v1a"; 63 reg = <0 0xe0900000 0 0x80000>, 64 <0 0xe0980000 0 0x80000>, 65 <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */ 66 <0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */ 67 <0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */ 68 interrupts = <0 324 4>, 69 <0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>, 70 <0 322 4>; 71 amd,per-channel-interrupt; 72 amd,speed-set = <0>; 73 amd,serdes-blwc = <1>, <1>, <0>; 74 amd,serdes-cdr-rate = <2>, <2>, <7>; 75 amd,serdes-pq-skew = <10>, <10>, <18>; 76 amd,serdes-tx-amp = <0>, <0>, <0>; 77 amd,serdes-dfe-tap-config = <3>, <3>, <3>; 78 amd,serdes-dfe-tap-enable = <0>, <0>, <7>; 79 mac-address = [ 02 B1 B2 B3 B4 B5 ]; 80 clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>; 81 clock-names = "dma_clk", "ptp_clk"; 82 phy-mode = "xgmii"; 83 #stream-id-cells = <16>; 84 dma-coherent; 85 }; 86 87 xgmac0_smmu: smmu@e0600000 { 88 compatible = "arm,mmu-401"; 89 reg = <0 0xe0600000 0 0x10000>; 90 #global-interrupts = <1>; 91 interrupts = /* Uses combined intr for both 92 * global and context 93 */ 94 <0 336 4>, 95 <0 336 4>; 96 97 mmu-masters = <&xgmac0 98 0 1 2 3 4 5 6 7 99 16 17 18 19 20 21 22 23 100 >; 101 }; 102 103 xgmac1_smmu: smmu@e0800000 { 104 compatible = "arm,mmu-401"; 105 reg = <0 0xe0800000 0 0x10000>; 106 #global-interrupts = <1>; 107 interrupts = /* Uses combined intr for both 108 * global and context 109 */ 110 <0 335 4>, 111 <0 335 4>; 112 113 mmu-masters = <&xgmac1 114 0 1 2 3 4 5 6 7 115 16 17 18 19 20 21 22 23 116 >; 117 }; 118