1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright Altera Corporation (C) 2015. All rights reserved. 4 */ 5 6#include "socfpga_stratix10.dtsi" 7 8/ { 9 model = "SoCFPGA Stratix 10 SoCDK"; 10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10"; 11 12 aliases { 13 serial0 = &uart0; 14 ethernet0 = &gmac0; 15 ethernet1 = &gmac1; 16 ethernet2 = &gmac2; 17 }; 18 19 chosen { 20 stdout-path = "serial0:115200n8"; 21 }; 22 23 leds { 24 compatible = "gpio-leds"; 25 led-hps0 { 26 label = "hps_led0"; 27 gpios = <&portb 20 GPIO_ACTIVE_HIGH>; 28 }; 29 30 led-hps1 { 31 label = "hps_led1"; 32 gpios = <&portb 19 GPIO_ACTIVE_HIGH>; 33 }; 34 35 led-hps2 { 36 label = "hps_led2"; 37 gpios = <&portb 21 GPIO_ACTIVE_HIGH>; 38 }; 39 }; 40 41 memory@80000000 { 42 device_type = "memory"; 43 /* We expect the bootloader to fill in the reg */ 44 reg = <0 0x80000000 0 0>; 45 }; 46 47 ref_033v: regulator-v-ref { 48 compatible = "regulator-fixed"; 49 regulator-name = "0.33V"; 50 regulator-min-microvolt = <330000>; 51 regulator-max-microvolt = <330000>; 52 }; 53 54 soc@0 { 55 eccmgr { 56 sdmmca-ecc@ff8c8c00 { 57 compatible = "altr,socfpga-s10-sdmmc-ecc", 58 "altr,socfpga-sdmmc-ecc"; 59 reg = <0xff8c8c00 0x100>; 60 altr,ecc-parent = <&mmc>; 61 interrupts = <14 4>, 62 <15 4>; 63 }; 64 }; 65 }; 66}; 67 68&gpio1 { 69 status = "okay"; 70}; 71 72&gmac2 { 73 status = "okay"; 74 phy-mode = "rgmii"; 75 phy-handle = <&phy0>; 76 77 max-frame-size = <9000>; 78 79 mdio0 { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 compatible = "snps,dwmac-mdio"; 83 phy0: ethernet-phy@0 { 84 reg = <4>; 85 86 txd0-skew-ps = <0>; /* -420ps */ 87 txd1-skew-ps = <0>; /* -420ps */ 88 txd2-skew-ps = <0>; /* -420ps */ 89 txd3-skew-ps = <0>; /* -420ps */ 90 rxd0-skew-ps = <420>; /* 0ps */ 91 rxd1-skew-ps = <420>; /* 0ps */ 92 rxd2-skew-ps = <420>; /* 0ps */ 93 rxd3-skew-ps = <420>; /* 0ps */ 94 txen-skew-ps = <0>; /* -420ps */ 95 txc-skew-ps = <900>; /* 0ps */ 96 rxdv-skew-ps = <420>; /* 0ps */ 97 rxc-skew-ps = <1680>; /* 780ps */ 98 }; 99 }; 100}; 101 102&nand { 103 status = "okay"; 104 105 nand@0 { 106 reg = <0>; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 nand-bus-width = <16>; 110 111 partition@0 { 112 label = "u-boot"; 113 reg = <0 0x200000>; 114 }; 115 116 partition@200000 { 117 label = "root"; 118 reg = <0x200000 0x3fe00000>; 119 }; 120 }; 121}; 122 123&osc1 { 124 clock-frequency = <25000000>; 125}; 126 127&uart0 { 128 status = "okay"; 129}; 130 131&usb0 { 132 status = "okay"; 133 disable-over-current; 134}; 135 136&watchdog0 { 137 status = "okay"; 138}; 139 140&i2c2 { 141 status = "okay"; 142 clock-frequency = <100000>; 143 i2c-sda-falling-time-ns = <890>; /* hcnt */ 144 i2c-scl-falling-time-ns = <890>; /* lcnt */ 145 146 adc@14 { 147 compatible = "lltc,ltc2497"; 148 reg = <0x14>; 149 vref-supply = <&ref_033v>; 150 }; 151 152 temp@4c { 153 compatible = "maxim,max1619"; 154 reg = <0x4c>; 155 }; 156 157 eeprom@51 { 158 compatible = "atmel,24c32"; 159 reg = <0x51>; 160 pagesize = <32>; 161 }; 162 163 rtc@68 { 164 compatible = "dallas,ds1339"; 165 reg = <0x68>; 166 }; 167}; 168 169&qspi { 170 status = "okay"; 171 flash@0 { 172 compatible = "micron,mt25qu02g", "jedec,spi-nor"; 173 reg = <0>; 174 spi-max-frequency = <100000000>; 175 176 m25p,fast-read; 177 cdns,read-delay = <1>; 178 cdns,tshsl-ns = <50>; 179 cdns,tsd2d-ns = <50>; 180 cdns,tchsh-ns = <4>; 181 cdns,tslch-ns = <4>; 182 183 partitions { 184 compatible = "fixed-partitions"; 185 #address-cells = <1>; 186 #size-cells = <1>; 187 188 qspi_boot: partition@0 { 189 label = "Boot and fpga data"; 190 reg = <0x0 0x03FE0000>; 191 }; 192 193 qspi_rootfs: partition@3fe0000 { 194 label = "Root Filesystem - JFFS2"; 195 reg = <0x03FE0000 0x0C020000>; 196 }; 197 }; 198 }; 199}; 200