1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright Altera Corporation (C) 2015. All rights reserved. 4 */ 5 6#include "socfpga_stratix10.dtsi" 7 8/ { 9 model = "SoCFPGA Stratix 10 SoCDK"; 10 compatible = "altr,socfpga-stratix10-socdk", "altr,socfpga-stratix10"; 11 12 aliases { 13 serial0 = &uart0; 14 ethernet0 = &gmac0; 15 ethernet1 = &gmac1; 16 ethernet2 = &gmac2; 17 }; 18 19 chosen { 20 stdout-path = "serial0:115200n8"; 21 }; 22 23 leds { 24 compatible = "gpio-leds"; 25 hps0 { 26 label = "hps_led0"; 27 gpios = <&portb 20 GPIO_ACTIVE_HIGH>; 28 }; 29 30 hps1 { 31 label = "hps_led1"; 32 gpios = <&portb 19 GPIO_ACTIVE_HIGH>; 33 }; 34 35 hps2 { 36 label = "hps_led2"; 37 gpios = <&portb 21 GPIO_ACTIVE_HIGH>; 38 }; 39 }; 40 41 memory { 42 device_type = "memory"; 43 /* We expect the bootloader to fill in the reg */ 44 reg = <0 0 0 0>; 45 }; 46 47 ref_033v: regulator-v-ref { 48 compatible = "regulator-fixed"; 49 regulator-name = "0.33V"; 50 regulator-min-microvolt = <330000>; 51 regulator-max-microvolt = <330000>; 52 }; 53 54 soc { 55 clocks { 56 osc1 { 57 clock-frequency = <25000000>; 58 }; 59 }; 60 61 eccmgr { 62 sdmmca-ecc@ff8c8c00 { 63 compatible = "altr,socfpga-s10-sdmmc-ecc", 64 "altr,socfpga-sdmmc-ecc"; 65 reg = <0xff8c8c00 0x100>; 66 altr,ecc-parent = <&mmc>; 67 interrupts = <14 4>, 68 <15 4>; 69 }; 70 }; 71 }; 72}; 73 74&gpio1 { 75 status = "okay"; 76}; 77 78&gmac0 { 79 status = "okay"; 80 phy-mode = "rgmii"; 81 phy-handle = <&phy0>; 82 83 max-frame-size = <9000>; 84 85 mdio0 { 86 #address-cells = <1>; 87 #size-cells = <0>; 88 compatible = "snps,dwmac-mdio"; 89 phy0: ethernet-phy@0 { 90 reg = <4>; 91 92 txd0-skew-ps = <0>; /* -420ps */ 93 txd1-skew-ps = <0>; /* -420ps */ 94 txd2-skew-ps = <0>; /* -420ps */ 95 txd3-skew-ps = <0>; /* -420ps */ 96 rxd0-skew-ps = <420>; /* 0ps */ 97 rxd1-skew-ps = <420>; /* 0ps */ 98 rxd2-skew-ps = <420>; /* 0ps */ 99 rxd3-skew-ps = <420>; /* 0ps */ 100 txen-skew-ps = <0>; /* -420ps */ 101 txc-skew-ps = <900>; /* 0ps */ 102 rxdv-skew-ps = <420>; /* 0ps */ 103 rxc-skew-ps = <1680>; /* 780ps */ 104 }; 105 }; 106}; 107 108&mmc { 109 status = "okay"; 110 cap-sd-highspeed; 111 cap-mmc-highspeed; 112 broken-cd; 113 bus-width = <4>; 114}; 115 116&uart0 { 117 status = "okay"; 118}; 119 120&usb0 { 121 status = "okay"; 122 disable-over-current; 123}; 124 125&watchdog0 { 126 status = "okay"; 127}; 128 129&i2c1 { 130 status = "okay"; 131 clock-frequency = <100000>; 132 i2c-sda-falling-time-ns = <890>; /* hcnt */ 133 i2c-sdl-falling-time-ns = <890>; /* lcnt */ 134 135 adc@14 { 136 compatible = "lltc,ltc2497"; 137 reg = <0x14>; 138 vref-supply = <&ref_033v>; 139 }; 140 141 temp@4c { 142 compatible = "maxim,max1619"; 143 reg = <0x4c>; 144 }; 145 146 eeprom@51 { 147 compatible = "atmel,24c32"; 148 reg = <0x51>; 149 pagesize = <32>; 150 }; 151 152 rtc@68 { 153 compatible = "dallas,ds1339"; 154 reg = <0x68>; 155 }; 156}; 157 158&qspi { 159 status = "okay"; 160 flash@0 { 161 #address-cells = <1>; 162 #size-cells = <1>; 163 compatible = "micron,mt25qu02g", "jedec,spi-nor"; 164 reg = <0>; 165 spi-max-frequency = <100000000>; 166 167 m25p,fast-read; 168 cdns,page-size = <256>; 169 cdns,block-size = <16>; 170 cdns,read-delay = <1>; 171 cdns,tshsl-ns = <50>; 172 cdns,tsd2d-ns = <50>; 173 cdns,tchsh-ns = <4>; 174 cdns,tslch-ns = <4>; 175 176 partitions { 177 compatible = "fixed-partitions"; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 181 qspi_boot: partition@0 { 182 label = "Boot and fpga data"; 183 reg = <0x0 0x03FE0000>; 184 }; 185 186 qspi_rootfs: partition@3FE0000 { 187 label = "Root Filesystem - JFFS2"; 188 reg = <0x03FE0000 0x0C020000>; 189 }; 190 }; 191 }; 192}; 193