1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright Altera Corporation (C) 2015. All rights reserved. 4 */ 5 6/dts-v1/; 7#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/clock/stratix10-clock.h> 10 11/ { 12 compatible = "altr,socfpga-stratix10"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 reserved-memory { 17 #address-cells = <2>; 18 #size-cells = <2>; 19 ranges; 20 21 service_reserved: svcbuffer@0 { 22 compatible = "shared-dma-pool"; 23 reg = <0x0 0x0 0x0 0x1000000>; 24 alignment = <0x1000>; 25 no-map; 26 }; 27 }; 28 29 cpus { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 cpu0: cpu@0 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 next-level-cache = <&l2_shared>; 38 reg = <0x0>; 39 }; 40 41 cpu1: cpu@1 { 42 compatible = "arm,cortex-a53"; 43 device_type = "cpu"; 44 enable-method = "psci"; 45 next-level-cache = <&l2_shared>; 46 reg = <0x1>; 47 }; 48 49 cpu2: cpu@2 { 50 compatible = "arm,cortex-a53"; 51 device_type = "cpu"; 52 enable-method = "psci"; 53 next-level-cache = <&l2_shared>; 54 reg = <0x2>; 55 }; 56 57 cpu3: cpu@3 { 58 compatible = "arm,cortex-a53"; 59 device_type = "cpu"; 60 enable-method = "psci"; 61 next-level-cache = <&l2_shared>; 62 reg = <0x3>; 63 }; 64 65 l2_shared: cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 }; 70 }; 71 72 firmware { 73 svc { 74 compatible = "intel,stratix10-svc"; 75 method = "smc"; 76 memory-region = <&service_reserved>; 77 78 fpga_mgr: fpga-mgr { 79 compatible = "intel,stratix10-soc-fpga-mgr"; 80 }; 81 }; 82 }; 83 84 fpga-region { 85 compatible = "fpga-region"; 86 #address-cells = <0x2>; 87 #size-cells = <0x2>; 88 fpga-mgr = <&fpga_mgr>; 89 }; 90 91 pmu { 92 compatible = "arm,cortex-a53-pmu"; 93 interrupts = <0 170 4>, 94 <0 171 4>, 95 <0 172 4>, 96 <0 173 4>; 97 interrupt-affinity = <&cpu0>, 98 <&cpu1>, 99 <&cpu2>, 100 <&cpu3>; 101 interrupt-parent = <&intc>; 102 }; 103 104 psci { 105 compatible = "arm,psci-0.2"; 106 method = "smc"; 107 }; 108 109 /* Local timer */ 110 timer { 111 compatible = "arm,armv8-timer"; 112 interrupts = <1 13 0xf08>, 113 <1 14 0xf08>, 114 <1 11 0xf08>, 115 <1 10 0xf08>; 116 interrupt-parent = <&intc>; 117 }; 118 119 intc: interrupt-controller@fffc1000 { 120 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 121 #interrupt-cells = <3>; 122 interrupt-controller; 123 reg = <0x0 0xfffc1000 0x0 0x1000>, 124 <0x0 0xfffc2000 0x0 0x2000>, 125 <0x0 0xfffc4000 0x0 0x2000>, 126 <0x0 0xfffc6000 0x0 0x2000>; 127 }; 128 129 clocks { 130 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 131 #clock-cells = <0>; 132 compatible = "fixed-clock"; 133 clock-frequency = <150000000>; 134 }; 135 136 cb_intosc_ls_clk: cb-intosc-ls-clk { 137 #clock-cells = <0>; 138 compatible = "fixed-clock"; 139 clock-frequency = <300000000>; 140 }; 141 142 f2s_free_clk: f2s-free-clk { 143 #clock-cells = <0>; 144 compatible = "fixed-clock"; 145 status = "disabled"; 146 }; 147 148 osc1: osc1 { 149 #clock-cells = <0>; 150 compatible = "fixed-clock"; 151 }; 152 153 qspi_clk: qspi-clk { 154 #clock-cells = <0>; 155 compatible = "fixed-clock"; 156 clock-frequency = <200000000>; 157 }; 158 }; 159 160 soc@0 { 161 #address-cells = <1>; 162 #size-cells = <1>; 163 compatible = "simple-bus"; 164 device_type = "soc"; 165 interrupt-parent = <&intc>; 166 ranges = <0 0 0 0xffffffff>; 167 168 clkmgr: clock-controller@ffd10000 { 169 compatible = "intel,stratix10-clkmgr"; 170 reg = <0xffd10000 0x1000>; 171 #clock-cells = <1>; 172 }; 173 174 gmac0: ethernet@ff800000 { 175 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 176 reg = <0xff800000 0x2000>; 177 interrupts = <0 90 4>; 178 interrupt-names = "macirq"; 179 mac-address = [00 00 00 00 00 00]; 180 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 181 reset-names = "stmmaceth", "ahb"; 182 clocks = <&clkmgr STRATIX10_EMAC0_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; 183 clock-names = "stmmaceth", "ptp_ref"; 184 tx-fifo-depth = <16384>; 185 rx-fifo-depth = <16384>; 186 snps,multicast-filter-bins = <256>; 187 iommus = <&smmu 1>; 188 altr,sysmgr-syscon = <&sysmgr 0x44 0>; 189 status = "disabled"; 190 }; 191 192 gmac1: ethernet@ff802000 { 193 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 194 reg = <0xff802000 0x2000>; 195 interrupts = <0 91 4>; 196 interrupt-names = "macirq"; 197 mac-address = [00 00 00 00 00 00]; 198 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 199 reset-names = "stmmaceth", "ahb"; 200 clocks = <&clkmgr STRATIX10_EMAC1_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; 201 clock-names = "stmmaceth", "ptp_ref"; 202 tx-fifo-depth = <16384>; 203 rx-fifo-depth = <16384>; 204 snps,multicast-filter-bins = <256>; 205 iommus = <&smmu 2>; 206 altr,sysmgr-syscon = <&sysmgr 0x48 8>; 207 status = "disabled"; 208 }; 209 210 gmac2: ethernet@ff804000 { 211 compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac"; 212 reg = <0xff804000 0x2000>; 213 interrupts = <0 92 4>; 214 interrupt-names = "macirq"; 215 mac-address = [00 00 00 00 00 00]; 216 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 217 reset-names = "stmmaceth", "ahb"; 218 clocks = <&clkmgr STRATIX10_EMAC2_CLK>, <&clkmgr STRATIX10_EMAC_PTP_CLK>; 219 clock-names = "stmmaceth", "ptp_ref"; 220 tx-fifo-depth = <16384>; 221 rx-fifo-depth = <16384>; 222 snps,multicast-filter-bins = <256>; 223 iommus = <&smmu 3>; 224 altr,sysmgr-syscon = <&sysmgr 0x4c 16>; 225 status = "disabled"; 226 }; 227 228 gpio0: gpio@ffc03200 { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 compatible = "snps,dw-apb-gpio"; 232 reg = <0xffc03200 0x100>; 233 resets = <&rst GPIO0_RESET>; 234 status = "disabled"; 235 236 porta: gpio-controller@0 { 237 compatible = "snps,dw-apb-gpio-port"; 238 gpio-controller; 239 #gpio-cells = <2>; 240 ngpios = <24>; 241 reg = <0>; 242 interrupt-controller; 243 #interrupt-cells = <2>; 244 interrupts = <0 110 4>; 245 }; 246 }; 247 248 gpio1: gpio@ffc03300 { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 compatible = "snps,dw-apb-gpio"; 252 reg = <0xffc03300 0x100>; 253 resets = <&rst GPIO1_RESET>; 254 status = "disabled"; 255 256 portb: gpio-controller@0 { 257 compatible = "snps,dw-apb-gpio-port"; 258 gpio-controller; 259 #gpio-cells = <2>; 260 ngpios = <24>; 261 reg = <0>; 262 interrupt-controller; 263 #interrupt-cells = <2>; 264 interrupts = <0 111 4>; 265 }; 266 }; 267 268 i2c0: i2c@ffc02800 { 269 #address-cells = <1>; 270 #size-cells = <0>; 271 compatible = "snps,designware-i2c"; 272 reg = <0xffc02800 0x100>; 273 interrupts = <0 103 4>; 274 resets = <&rst I2C0_RESET>; 275 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 276 status = "disabled"; 277 }; 278 279 i2c1: i2c@ffc02900 { 280 #address-cells = <1>; 281 #size-cells = <0>; 282 compatible = "snps,designware-i2c"; 283 reg = <0xffc02900 0x100>; 284 interrupts = <0 104 4>; 285 resets = <&rst I2C1_RESET>; 286 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 287 status = "disabled"; 288 }; 289 290 i2c2: i2c@ffc02a00 { 291 #address-cells = <1>; 292 #size-cells = <0>; 293 compatible = "snps,designware-i2c"; 294 reg = <0xffc02a00 0x100>; 295 interrupts = <0 105 4>; 296 resets = <&rst I2C2_RESET>; 297 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 298 status = "disabled"; 299 }; 300 301 i2c3: i2c@ffc02b00 { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 compatible = "snps,designware-i2c"; 305 reg = <0xffc02b00 0x100>; 306 interrupts = <0 106 4>; 307 resets = <&rst I2C3_RESET>; 308 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 309 status = "disabled"; 310 }; 311 312 i2c4: i2c@ffc02c00 { 313 #address-cells = <1>; 314 #size-cells = <0>; 315 compatible = "snps,designware-i2c"; 316 reg = <0xffc02c00 0x100>; 317 interrupts = <0 107 4>; 318 resets = <&rst I2C4_RESET>; 319 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 320 status = "disabled"; 321 }; 322 323 mmc: mmc@ff808000 { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 compatible = "altr,socfpga-dw-mshc"; 327 reg = <0xff808000 0x1000>; 328 interrupts = <0 96 4>; 329 fifo-depth = <0x400>; 330 resets = <&rst SDMMC_RESET>; 331 reset-names = "reset"; 332 clocks = <&clkmgr STRATIX10_L4_MP_CLK>, 333 <&clkmgr STRATIX10_SDMMC_CLK>; 334 clock-names = "biu", "ciu"; 335 iommus = <&smmu 5>; 336 altr,sysmgr-syscon = <&sysmgr 0x28 4>; 337 status = "disabled"; 338 }; 339 340 nand: nand-controller@ffb90000 { 341 #address-cells = <1>; 342 #size-cells = <0>; 343 compatible = "altr,socfpga-denali-nand"; 344 reg = <0xffb90000 0x10000>, 345 <0xffb80000 0x1000>; 346 reg-names = "nand_data", "denali_reg"; 347 interrupts = <0 97 4>; 348 clocks = <&clkmgr STRATIX10_NAND_CLK>, 349 <&clkmgr STRATIX10_NAND_X_CLK>, 350 <&clkmgr STRATIX10_NAND_ECC_CLK>; 351 clock-names = "nand", "nand_x", "ecc"; 352 resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; 353 status = "disabled"; 354 }; 355 356 ocram: sram@ffe00000 { 357 compatible = "mmio-sram"; 358 reg = <0xffe00000 0x100000>; 359 #address-cells = <1>; 360 #size-cells = <1>; 361 ranges = <0 0xffe00000 0x100000>; 362 }; 363 364 pdma: dma-controller@ffda0000 { 365 compatible = "arm,pl330", "arm,primecell"; 366 reg = <0xffda0000 0x1000>; 367 interrupts = <0 81 4>, 368 <0 82 4>, 369 <0 83 4>, 370 <0 84 4>, 371 <0 85 4>, 372 <0 86 4>, 373 <0 87 4>, 374 <0 88 4>, 375 <0 89 4>; 376 #dma-cells = <1>; 377 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 378 clock-names = "apb_pclk"; 379 resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; 380 reset-names = "dma", "dma-ocp"; 381 }; 382 383 pinctrl0: pinctrl@ffd13000 { 384 compatible = "pinctrl-single"; 385 reg = <0xffd13000 0xA0>; 386 #pinctrl-cells = <1>; 387 pinctrl-single,register-width = <32>; 388 pinctrl-single,function-mask = <0x0000000f>; 389 }; 390 391 pinctrl1: pinctrl@ffd13100 { 392 compatible = "pinctrl-single"; 393 reg = <0xffd13100 0x20>; 394 #pinctrl-cells = <1>; 395 pinctrl-single,register-width = <32>; 396 pinctrl-single,function-mask = <0x0000000f>; 397 }; 398 399 rst: rstmgr@ffd11000 { 400 #reset-cells = <1>; 401 compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; 402 reg = <0xffd11000 0x1000>; 403 }; 404 405 smmu: iommu@fa000000 { 406 compatible = "arm,mmu-500", "arm,smmu-v2"; 407 reg = <0xfa000000 0x40000>; 408 #global-interrupts = <2>; 409 #iommu-cells = <1>; 410 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 411 clock-names = "iommu"; 412 interrupt-parent = <&intc>; 413 interrupts = <0 128 4>, /* Global Secure Fault */ 414 <0 129 4>, /* Global Non-secure Fault */ 415 /* Non-secure Context Interrupts (32) */ 416 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, 417 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, 418 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, 419 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, 420 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, 421 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, 422 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, 423 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; 424 stream-match-mask = <0x7ff0>; 425 status = "disabled"; 426 }; 427 428 spi0: spi@ffda4000 { 429 compatible = "snps,dw-apb-ssi"; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 reg = <0xffda4000 0x1000>; 433 interrupts = <0 99 4>; 434 resets = <&rst SPIM0_RESET>; 435 reset-names = "spi"; 436 reg-io-width = <4>; 437 num-cs = <4>; 438 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 439 status = "disabled"; 440 }; 441 442 spi1: spi@ffda5000 { 443 compatible = "snps,dw-apb-ssi"; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 reg = <0xffda5000 0x1000>; 447 interrupts = <0 100 4>; 448 resets = <&rst SPIM1_RESET>; 449 reset-names = "spi"; 450 reg-io-width = <4>; 451 num-cs = <4>; 452 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 453 status = "disabled"; 454 }; 455 456 sysmgr: sysmgr@ffd12000 { 457 compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 458 reg = <0xffd12000 0x228>; 459 }; 460 461 timer0: timer0@ffc03000 { 462 compatible = "snps,dw-apb-timer"; 463 interrupts = <0 113 4>; 464 reg = <0xffc03000 0x100>; 465 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 466 clock-names = "timer"; 467 }; 468 469 timer1: timer1@ffc03100 { 470 compatible = "snps,dw-apb-timer"; 471 interrupts = <0 114 4>; 472 reg = <0xffc03100 0x100>; 473 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 474 clock-names = "timer"; 475 }; 476 477 timer2: timer2@ffd00000 { 478 compatible = "snps,dw-apb-timer"; 479 interrupts = <0 115 4>; 480 reg = <0xffd00000 0x100>; 481 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 482 clock-names = "timer"; 483 }; 484 485 timer3: timer3@ffd00100 { 486 compatible = "snps,dw-apb-timer"; 487 interrupts = <0 116 4>; 488 reg = <0xffd00100 0x100>; 489 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 490 clock-names = "timer"; 491 }; 492 493 uart0: serial@ffc02000 { 494 compatible = "snps,dw-apb-uart"; 495 reg = <0xffc02000 0x100>; 496 interrupts = <0 108 4>; 497 reg-shift = <2>; 498 reg-io-width = <4>; 499 resets = <&rst UART0_RESET>; 500 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 501 status = "disabled"; 502 }; 503 504 uart1: serial@ffc02100 { 505 compatible = "snps,dw-apb-uart"; 506 reg = <0xffc02100 0x100>; 507 interrupts = <0 109 4>; 508 reg-shift = <2>; 509 reg-io-width = <4>; 510 resets = <&rst UART1_RESET>; 511 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 512 status = "disabled"; 513 }; 514 515 usb0: usb@ffb00000 { 516 compatible = "snps,dwc2"; 517 reg = <0xffb00000 0x40000>; 518 interrupts = <0 93 4>; 519 phys = <&usbphy0>; 520 phy-names = "usb2-phy"; 521 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 522 reset-names = "dwc2", "dwc2-ecc"; 523 clocks = <&clkmgr STRATIX10_USB_CLK>; 524 clock-names = "otg"; 525 iommus = <&smmu 6>; 526 status = "disabled"; 527 }; 528 529 usb1: usb@ffb40000 { 530 compatible = "snps,dwc2"; 531 reg = <0xffb40000 0x40000>; 532 interrupts = <0 94 4>; 533 phys = <&usbphy0>; 534 phy-names = "usb2-phy"; 535 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 536 reset-names = "dwc2", "dwc2-ecc"; 537 clocks = <&clkmgr STRATIX10_USB_CLK>; 538 clock-names = "otg"; 539 iommus = <&smmu 7>; 540 status = "disabled"; 541 }; 542 543 watchdog0: watchdog@ffd00200 { 544 compatible = "snps,dw-wdt"; 545 reg = <0xffd00200 0x100>; 546 interrupts = <0 117 4>; 547 resets = <&rst WATCHDOG0_RESET>; 548 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 549 status = "disabled"; 550 }; 551 552 watchdog1: watchdog@ffd00300 { 553 compatible = "snps,dw-wdt"; 554 reg = <0xffd00300 0x100>; 555 interrupts = <0 118 4>; 556 resets = <&rst WATCHDOG1_RESET>; 557 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 558 status = "disabled"; 559 }; 560 561 watchdog2: watchdog@ffd00400 { 562 compatible = "snps,dw-wdt"; 563 reg = <0xffd00400 0x100>; 564 interrupts = <0 125 4>; 565 resets = <&rst WATCHDOG2_RESET>; 566 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 567 status = "disabled"; 568 }; 569 570 watchdog3: watchdog@ffd00500 { 571 compatible = "snps,dw-wdt"; 572 reg = <0xffd00500 0x100>; 573 interrupts = <0 126 4>; 574 resets = <&rst WATCHDOG3_RESET>; 575 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 576 status = "disabled"; 577 }; 578 579 sdr: sdr@f8011100 { 580 compatible = "altr,sdr-ctl", "syscon"; 581 reg = <0xf8011100 0xc0>; 582 }; 583 584 eccmgr { 585 compatible = "altr,socfpga-s10-ecc-manager", 586 "altr,socfpga-a10-ecc-manager"; 587 altr,sysmgr-syscon = <&sysmgr>; 588 #address-cells = <1>; 589 #size-cells = <1>; 590 interrupts = <0 15 4>; 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 ranges; 594 595 sdramedac { 596 compatible = "altr,sdram-edac-s10"; 597 altr,sdr-syscon = <&sdr>; 598 interrupts = <16 4>; 599 }; 600 601 ocram-ecc@ff8cc000 { 602 compatible = "altr,socfpga-s10-ocram-ecc", 603 "altr,socfpga-a10-ocram-ecc"; 604 reg = <0xff8cc000 0x100>; 605 altr,ecc-parent = <&ocram>; 606 interrupts = <1 4>; 607 }; 608 609 usb0-ecc@ff8c4000 { 610 compatible = "altr,socfpga-s10-usb-ecc", 611 "altr,socfpga-usb-ecc"; 612 reg = <0xff8c4000 0x100>; 613 altr,ecc-parent = <&usb0>; 614 interrupts = <2 4>; 615 }; 616 617 emac0-rx-ecc@ff8c0000 { 618 compatible = "altr,socfpga-s10-eth-mac-ecc", 619 "altr,socfpga-eth-mac-ecc"; 620 reg = <0xff8c0000 0x100>; 621 altr,ecc-parent = <&gmac0>; 622 interrupts = <4 4>; 623 }; 624 625 emac0-tx-ecc@ff8c0400 { 626 compatible = "altr,socfpga-s10-eth-mac-ecc", 627 "altr,socfpga-eth-mac-ecc"; 628 reg = <0xff8c0400 0x100>; 629 altr,ecc-parent = <&gmac0>; 630 interrupts = <5 4>; 631 }; 632 633 }; 634 635 qspi: spi@ff8d2000 { 636 compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 reg = <0xff8d2000 0x100>, 640 <0xff900000 0x100000>; 641 interrupts = <0 3 4>; 642 cdns,fifo-depth = <128>; 643 cdns,fifo-width = <4>; 644 cdns,trigger-address = <0x00000000>; 645 clocks = <&qspi_clk>; 646 647 status = "disabled"; 648 }; 649 }; 650 651 usbphy0: usbphy0 { 652 compatible = "usb-nop-xceiv"; 653 #phy-cells = <0>; 654 }; 655}; 656