xref: /linux/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi (revision f057b57270c2a17d3f45c177e9434fa5745caa48)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2// Copyright (C) 2020 Arm Ltd.
3// based on the H6 dtsi, which is:
4//   Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
5
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/sun50i-h616-ccu.h>
8#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9#include <dt-bindings/clock/sun6i-rtc.h>
10#include <dt-bindings/reset/sun50i-h616-ccu.h>
11#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
12#include <dt-bindings/thermal/thermal.h>
13
14/ {
15	interrupt-parent = <&gic>;
16	#address-cells = <2>;
17	#size-cells = <2>;
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu0: cpu@0 {
24			compatible = "arm,cortex-a53";
25			device_type = "cpu";
26			reg = <0>;
27			enable-method = "psci";
28			clocks = <&ccu CLK_CPUX>;
29			#cooling-cells = <2>;
30			i-cache-size = <0x8000>;
31			i-cache-line-size = <64>;
32			i-cache-sets = <256>;
33			d-cache-size = <0x8000>;
34			d-cache-line-size = <64>;
35			d-cache-sets = <128>;
36			next-level-cache = <&l2_cache>;
37		};
38
39		cpu1: cpu@1 {
40			compatible = "arm,cortex-a53";
41			device_type = "cpu";
42			reg = <1>;
43			enable-method = "psci";
44			clocks = <&ccu CLK_CPUX>;
45			#cooling-cells = <2>;
46			i-cache-size = <0x8000>;
47			i-cache-line-size = <64>;
48			i-cache-sets = <256>;
49			d-cache-size = <0x8000>;
50			d-cache-line-size = <64>;
51			d-cache-sets = <128>;
52			next-level-cache = <&l2_cache>;
53		};
54
55		cpu2: cpu@2 {
56			compatible = "arm,cortex-a53";
57			device_type = "cpu";
58			reg = <2>;
59			enable-method = "psci";
60			clocks = <&ccu CLK_CPUX>;
61			#cooling-cells = <2>;
62			i-cache-size = <0x8000>;
63			i-cache-line-size = <64>;
64			i-cache-sets = <256>;
65			d-cache-size = <0x8000>;
66			d-cache-line-size = <64>;
67			d-cache-sets = <128>;
68			next-level-cache = <&l2_cache>;
69		};
70
71		cpu3: cpu@3 {
72			compatible = "arm,cortex-a53";
73			device_type = "cpu";
74			reg = <3>;
75			enable-method = "psci";
76			clocks = <&ccu CLK_CPUX>;
77			#cooling-cells = <2>;
78			i-cache-size = <0x8000>;
79			i-cache-line-size = <64>;
80			i-cache-sets = <256>;
81			d-cache-size = <0x8000>;
82			d-cache-line-size = <64>;
83			d-cache-sets = <128>;
84			next-level-cache = <&l2_cache>;
85		};
86
87		l2_cache: l2-cache {
88			compatible = "cache";
89			cache-level = <2>;
90			cache-unified;
91			cache-size = <0x40000>;
92			cache-line-size = <64>;
93			cache-sets = <256>;
94		};
95	};
96
97	reserved-memory {
98		#address-cells = <2>;
99		#size-cells = <2>;
100		ranges;
101
102		/*
103		 * 256 KiB reserved for Trusted Firmware-A (BL31).
104		 * This is added by BL31 itself, but some bootloaders fail
105		 * to propagate this into the DTB handed to kernels.
106		 */
107		secmon@40000000 {
108			reg = <0x0 0x40000000 0x0 0x40000>;
109			no-map;
110		};
111	};
112
113	osc24M: osc24M-clk {
114		#clock-cells = <0>;
115		compatible = "fixed-clock";
116		clock-frequency = <24000000>;
117		clock-output-names = "osc24M";
118	};
119
120	pmu {
121		compatible = "arm,cortex-a53-pmu";
122		interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
123			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
124			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
125			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
126		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
127	};
128
129	psci {
130		compatible = "arm,psci-0.2";
131		method = "smc";
132	};
133
134	timer {
135		compatible = "arm,armv8-timer";
136		arm,no-tick-in-suspend;
137		interrupts = <GIC_PPI 13
138			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
139			     <GIC_PPI 14
140			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
141			     <GIC_PPI 11
142			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
143			     <GIC_PPI 10
144			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
145	};
146
147	soc {
148		compatible = "simple-bus";
149		#address-cells = <1>;
150		#size-cells = <1>;
151		ranges = <0x0 0x0 0x0 0x40000000>;
152
153		crypto: crypto@1904000 {
154			compatible = "allwinner,sun50i-h616-crypto";
155			reg = <0x01904000 0x800>;
156			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
157			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>,
158				 <&ccu CLK_MBUS_CE>, <&rtc CLK_IOSC>;
159			clock-names = "bus", "mod", "ram", "trng";
160			resets = <&ccu RST_BUS_CE>;
161		};
162
163		syscon: syscon@3000000 {
164			compatible = "allwinner,sun50i-h616-system-control";
165			reg = <0x03000000 0x1000>;
166			#address-cells = <1>;
167			#size-cells = <1>;
168			ranges;
169
170			sram_c: sram@28000 {
171				compatible = "mmio-sram";
172				reg = <0x00028000 0x30000>;
173				#address-cells = <1>;
174				#size-cells = <1>;
175				ranges = <0 0x00028000 0x30000>;
176			};
177		};
178
179		ccu: clock@3001000 {
180			compatible = "allwinner,sun50i-h616-ccu";
181			reg = <0x03001000 0x1000>;
182			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>;
183			clock-names = "hosc", "losc", "iosc";
184			#clock-cells = <1>;
185			#reset-cells = <1>;
186		};
187
188		dma: dma-controller@3002000 {
189			compatible = "allwinner,sun50i-h616-dma",
190				     "allwinner,sun50i-a100-dma";
191			reg = <0x03002000 0x1000>;
192			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
193			clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
194			clock-names = "bus", "mbus";
195			dma-channels = <16>;
196			dma-requests = <49>;
197			resets = <&ccu RST_BUS_DMA>;
198			#dma-cells = <1>;
199		};
200
201		sid: efuse@3006000 {
202			compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid";
203			reg = <0x03006000 0x1000>;
204			#address-cells = <1>;
205			#size-cells = <1>;
206
207			ths_calibration: thermal-sensor-calibration@14 {
208				reg = <0x14 0x8>;
209			};
210
211			cpu_speed_grade: cpu-speed-grade@0 {
212				reg = <0x0 2>;
213			};
214		};
215
216		watchdog: watchdog@30090a0 {
217			compatible = "allwinner,sun50i-h616-wdt",
218				     "allwinner,sun6i-a31-wdt";
219			reg = <0x030090a0 0x20>;
220			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
221			clocks = <&osc24M>;
222		};
223
224		pio: pinctrl@300b000 {
225			compatible = "allwinner,sun50i-h616-pinctrl";
226			reg = <0x0300b000 0x400>;
227			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
228				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
229				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
230				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
231				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
232				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
233				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
234				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
235			clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>;
236			clock-names = "apb", "hosc", "losc";
237			gpio-controller;
238			#gpio-cells = <3>;
239			interrupt-controller;
240			#interrupt-cells = <3>;
241
242			ext_rgmii_pins: rgmii-pins {
243				pins = "PI0", "PI1", "PI2", "PI3", "PI4",
244				       "PI5", "PI7", "PI8", "PI9", "PI10",
245				       "PI11", "PI12", "PI13", "PI14", "PI15",
246				       "PI16";
247				function = "emac0";
248				drive-strength = <40>;
249			};
250
251			i2c0_pins: i2c0-pins {
252				pins = "PI5", "PI6";
253				function = "i2c0";
254			};
255
256			i2c3_ph_pins: i2c3-ph-pins {
257				pins = "PH4", "PH5";
258				function = "i2c3";
259			};
260
261			ir_rx_pin: ir-rx-pin {
262				pins = "PH10";
263				function = "ir_rx";
264			};
265
266			mmc0_pins: mmc0-pins {
267				pins = "PF0", "PF1", "PF2", "PF3",
268				       "PF4", "PF5";
269				function = "mmc0";
270				drive-strength = <30>;
271				bias-pull-up;
272			};
273
274			/omit-if-no-ref/
275			mmc1_pins: mmc1-pins {
276				pins = "PG0", "PG1", "PG2", "PG3",
277				       "PG4", "PG5";
278				function = "mmc1";
279				drive-strength = <30>;
280				bias-pull-up;
281			};
282
283			mmc2_pins: mmc2-pins {
284				pins = "PC0", "PC1", "PC5", "PC6",
285				       "PC8", "PC9", "PC10", "PC11",
286				       "PC13", "PC14", "PC15", "PC16";
287				function = "mmc2";
288				drive-strength = <30>;
289				bias-pull-up;
290			};
291
292			/omit-if-no-ref/
293			spi0_pins: spi0-pins {
294				pins = "PC0", "PC2", "PC4";
295				function = "spi0";
296			};
297
298			/omit-if-no-ref/
299			spi0_cs0_pin: spi0-cs0-pin {
300				pins = "PC3";
301				function = "spi0";
302			};
303
304			/omit-if-no-ref/
305			spi1_pins: spi1-pins {
306				pins = "PH6", "PH7", "PH8";
307				function = "spi1";
308			};
309
310			/omit-if-no-ref/
311			spi1_cs0_pin: spi1-cs0-pin {
312				pins = "PH5";
313				function = "spi1";
314			};
315
316			spdif_tx_pin: spdif-tx-pin {
317				pins = "PH4";
318				function = "spdif";
319			};
320
321			uart0_ph_pins: uart0-ph-pins {
322				pins = "PH0", "PH1";
323				function = "uart0";
324			};
325
326			/omit-if-no-ref/
327			uart1_pins: uart1-pins {
328				pins = "PG6", "PG7";
329				function = "uart1";
330			};
331
332			/omit-if-no-ref/
333			uart1_rts_cts_pins: uart1-rts-cts-pins {
334				pins = "PG8", "PG9";
335				function = "uart1";
336			};
337
338			/omit-if-no-ref/
339			x32clk_fanout_pin: x32clk-fanout-pin {
340				pins = "PG10";
341				function = "clock";
342			};
343		};
344
345		gic: interrupt-controller@3021000 {
346			compatible = "arm,gic-400";
347			reg = <0x03021000 0x1000>,
348			      <0x03022000 0x2000>,
349			      <0x03024000 0x2000>,
350			      <0x03026000 0x2000>;
351			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
352			interrupt-controller;
353			#interrupt-cells = <3>;
354		};
355
356		iommu: iommu@30f0000 {
357			compatible = "allwinner,sun50i-h616-iommu";
358			reg = <0x030f0000 0x10000>;
359			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
360			clocks = <&ccu CLK_BUS_IOMMU>;
361			resets = <&ccu RST_BUS_IOMMU>;
362			#iommu-cells = <1>;
363		};
364
365		mmc0: mmc@4020000 {
366			compatible = "allwinner,sun50i-h616-mmc",
367				     "allwinner,sun50i-a100-mmc";
368			reg = <0x04020000 0x1000>;
369			clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
370			clock-names = "ahb", "mmc";
371			resets = <&ccu RST_BUS_MMC0>;
372			reset-names = "ahb";
373			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
374			pinctrl-names = "default";
375			pinctrl-0 = <&mmc0_pins>;
376			status = "disabled";
377			max-frequency = <150000000>;
378			cap-sd-highspeed;
379			cap-mmc-highspeed;
380			mmc-ddr-3_3v;
381			cap-sdio-irq;
382			#address-cells = <1>;
383			#size-cells = <0>;
384		};
385
386		mmc1: mmc@4021000 {
387			compatible = "allwinner,sun50i-h616-mmc",
388				     "allwinner,sun50i-a100-mmc";
389			reg = <0x04021000 0x1000>;
390			clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
391			clock-names = "ahb", "mmc";
392			resets = <&ccu RST_BUS_MMC1>;
393			reset-names = "ahb";
394			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
395			pinctrl-names = "default";
396			pinctrl-0 = <&mmc1_pins>;
397			status = "disabled";
398			max-frequency = <150000000>;
399			cap-sd-highspeed;
400			cap-mmc-highspeed;
401			mmc-ddr-3_3v;
402			cap-sdio-irq;
403			#address-cells = <1>;
404			#size-cells = <0>;
405		};
406
407		mmc2: mmc@4022000 {
408			compatible = "allwinner,sun50i-h616-emmc",
409				     "allwinner,sun50i-a100-emmc";
410			reg = <0x04022000 0x1000>;
411			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
412			clock-names = "ahb", "mmc";
413			resets = <&ccu RST_BUS_MMC2>;
414			reset-names = "ahb";
415			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
416			pinctrl-names = "default";
417			pinctrl-0 = <&mmc2_pins>;
418			status = "disabled";
419			max-frequency = <150000000>;
420			cap-sd-highspeed;
421			cap-mmc-highspeed;
422			mmc-ddr-3_3v;
423			cap-sdio-irq;
424			#address-cells = <1>;
425			#size-cells = <0>;
426		};
427
428		uart0: serial@5000000 {
429			compatible = "snps,dw-apb-uart";
430			reg = <0x05000000 0x400>;
431			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
432			reg-shift = <2>;
433			reg-io-width = <4>;
434			clocks = <&ccu CLK_BUS_UART0>;
435			dmas = <&dma 14>, <&dma 14>;
436			dma-names = "tx", "rx";
437			resets = <&ccu RST_BUS_UART0>;
438			status = "disabled";
439		};
440
441		uart1: serial@5000400 {
442			compatible = "snps,dw-apb-uart";
443			reg = <0x05000400 0x400>;
444			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
445			reg-shift = <2>;
446			reg-io-width = <4>;
447			clocks = <&ccu CLK_BUS_UART1>;
448			dmas = <&dma 15>, <&dma 15>;
449			dma-names = "tx", "rx";
450			resets = <&ccu RST_BUS_UART1>;
451			status = "disabled";
452		};
453
454		uart2: serial@5000800 {
455			compatible = "snps,dw-apb-uart";
456			reg = <0x05000800 0x400>;
457			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
458			reg-shift = <2>;
459			reg-io-width = <4>;
460			clocks = <&ccu CLK_BUS_UART2>;
461			dmas = <&dma 16>, <&dma 16>;
462			dma-names = "tx", "rx";
463			resets = <&ccu RST_BUS_UART2>;
464			status = "disabled";
465		};
466
467		uart3: serial@5000c00 {
468			compatible = "snps,dw-apb-uart";
469			reg = <0x05000c00 0x400>;
470			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
471			reg-shift = <2>;
472			reg-io-width = <4>;
473			clocks = <&ccu CLK_BUS_UART3>;
474			dmas = <&dma 17>, <&dma 17>;
475			dma-names = "tx", "rx";
476			resets = <&ccu RST_BUS_UART3>;
477			status = "disabled";
478		};
479
480		uart4: serial@5001000 {
481			compatible = "snps,dw-apb-uart";
482			reg = <0x05001000 0x400>;
483			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
484			reg-shift = <2>;
485			reg-io-width = <4>;
486			clocks = <&ccu CLK_BUS_UART4>;
487			dmas = <&dma 18>, <&dma 18>;
488			dma-names = "tx", "rx";
489			resets = <&ccu RST_BUS_UART4>;
490			status = "disabled";
491		};
492
493		uart5: serial@5001400 {
494			compatible = "snps,dw-apb-uart";
495			reg = <0x05001400 0x400>;
496			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
497			reg-shift = <2>;
498			reg-io-width = <4>;
499			clocks = <&ccu CLK_BUS_UART5>;
500			dmas = <&dma 19>, <&dma 19>;
501			dma-names = "tx", "rx";
502			resets = <&ccu RST_BUS_UART5>;
503			status = "disabled";
504		};
505
506		i2c0: i2c@5002000 {
507			compatible = "allwinner,sun50i-h616-i2c",
508				     "allwinner,sun8i-v536-i2c",
509				     "allwinner,sun6i-a31-i2c";
510			reg = <0x05002000 0x400>;
511			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
512			clocks = <&ccu CLK_BUS_I2C0>;
513			dmas = <&dma 43>, <&dma 43>;
514			dma-names = "rx", "tx";
515			resets = <&ccu RST_BUS_I2C0>;
516			pinctrl-names = "default";
517			pinctrl-0 = <&i2c0_pins>;
518			status = "disabled";
519			#address-cells = <1>;
520			#size-cells = <0>;
521		};
522
523		i2c1: i2c@5002400 {
524			compatible = "allwinner,sun50i-h616-i2c",
525				     "allwinner,sun8i-v536-i2c",
526				     "allwinner,sun6i-a31-i2c";
527			reg = <0x05002400 0x400>;
528			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
529			clocks = <&ccu CLK_BUS_I2C1>;
530			dmas = <&dma 44>, <&dma 44>;
531			dma-names = "rx", "tx";
532			resets = <&ccu RST_BUS_I2C1>;
533			status = "disabled";
534			#address-cells = <1>;
535			#size-cells = <0>;
536		};
537
538		i2c2: i2c@5002800 {
539			compatible = "allwinner,sun50i-h616-i2c",
540				     "allwinner,sun8i-v536-i2c",
541				     "allwinner,sun6i-a31-i2c";
542			reg = <0x05002800 0x400>;
543			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
544			clocks = <&ccu CLK_BUS_I2C2>;
545			dmas = <&dma 45>, <&dma 45>;
546			dma-names = "rx", "tx";
547			resets = <&ccu RST_BUS_I2C2>;
548			status = "disabled";
549			#address-cells = <1>;
550			#size-cells = <0>;
551		};
552
553		i2c3: i2c@5002c00 {
554			compatible = "allwinner,sun50i-h616-i2c",
555				     "allwinner,sun8i-v536-i2c",
556				     "allwinner,sun6i-a31-i2c";
557			reg = <0x05002c00 0x400>;
558			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
559			clocks = <&ccu CLK_BUS_I2C3>;
560			dmas = <&dma 46>, <&dma 46>;
561			dma-names = "rx", "tx";
562			resets = <&ccu RST_BUS_I2C3>;
563			status = "disabled";
564			#address-cells = <1>;
565			#size-cells = <0>;
566		};
567
568		i2c4: i2c@5003000 {
569			compatible = "allwinner,sun50i-h616-i2c",
570				     "allwinner,sun8i-v536-i2c",
571				     "allwinner,sun6i-a31-i2c";
572			reg = <0x05003000 0x400>;
573			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
574			clocks = <&ccu CLK_BUS_I2C4>;
575			dmas = <&dma 47>, <&dma 47>;
576			dma-names = "rx", "tx";
577			resets = <&ccu RST_BUS_I2C4>;
578			status = "disabled";
579			#address-cells = <1>;
580			#size-cells = <0>;
581		};
582
583		spi0: spi@5010000 {
584			compatible = "allwinner,sun50i-h616-spi",
585				     "allwinner,sun8i-h3-spi";
586			reg = <0x05010000 0x1000>;
587			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
588			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
589			clock-names = "ahb", "mod";
590			dmas = <&dma 22>, <&dma 22>;
591			dma-names = "rx", "tx";
592			resets = <&ccu RST_BUS_SPI0>;
593			status = "disabled";
594			#address-cells = <1>;
595			#size-cells = <0>;
596		};
597
598		spi1: spi@5011000 {
599			compatible = "allwinner,sun50i-h616-spi",
600				     "allwinner,sun8i-h3-spi";
601			reg = <0x05011000 0x1000>;
602			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
603			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
604			clock-names = "ahb", "mod";
605			dmas = <&dma 23>, <&dma 23>;
606			dma-names = "rx", "tx";
607			resets = <&ccu RST_BUS_SPI1>;
608			status = "disabled";
609			#address-cells = <1>;
610			#size-cells = <0>;
611		};
612
613		emac0: ethernet@5020000 {
614			compatible = "allwinner,sun50i-h616-emac0",
615				     "allwinner,sun50i-a64-emac";
616			reg = <0x05020000 0x10000>;
617			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
618			interrupt-names = "macirq";
619			clocks = <&ccu CLK_BUS_EMAC0>;
620			clock-names = "stmmaceth";
621			resets = <&ccu RST_BUS_EMAC0>;
622			reset-names = "stmmaceth";
623			syscon = <&syscon>;
624			status = "disabled";
625
626			mdio0: mdio {
627				compatible = "snps,dwmac-mdio";
628				#address-cells = <1>;
629				#size-cells = <0>;
630			};
631		};
632
633		spdif: spdif@5093000 {
634			compatible = "allwinner,sun50i-h616-spdif";
635			reg = <0x05093000 0x400>;
636			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
637			clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
638			clock-names = "apb", "spdif";
639			resets = <&ccu RST_BUS_SPDIF>;
640			dmas = <&dma 2>;
641			dma-names = "tx";
642			pinctrl-names = "default";
643			pinctrl-0 = <&spdif_tx_pin>;
644			#sound-dai-cells = <0>;
645			status = "disabled";
646		};
647
648		gpadc: adc@5070000 {
649			compatible = "allwinner,sun50i-h616-gpadc",
650				     "allwinner,sun20i-d1-gpadc";
651			reg = <0x05070000 0x400>;
652			clocks = <&ccu CLK_BUS_GPADC>;
653			resets = <&ccu RST_BUS_GPADC>;
654			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
655			status = "disabled";
656			#io-channel-cells = <1>;
657		};
658
659		ths: thermal-sensor@5070400 {
660			compatible = "allwinner,sun50i-h616-ths";
661			reg = <0x05070400 0x400>;
662			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
663			clocks = <&ccu CLK_BUS_THS>;
664			clock-names = "bus";
665			resets = <&ccu RST_BUS_THS>;
666			nvmem-cells = <&ths_calibration>;
667			nvmem-cell-names = "calibration";
668			allwinner,sram = <&syscon>;
669			#thermal-sensor-cells = <1>;
670		};
671
672		lradc: lradc@5070800 {
673			compatible = "allwinner,sun50i-h616-lradc",
674				     "allwinner,sun50i-r329-lradc";
675			reg = <0x05070800 0x400>;
676			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
677			clocks = <&ccu CLK_BUS_KEYADC>;
678			resets = <&ccu RST_BUS_KEYADC>;
679			status = "disabled";
680		};
681
682		usbotg: usb@5100000 {
683			compatible = "allwinner,sun50i-h616-musb",
684				     "allwinner,sun8i-h3-musb";
685			reg = <0x05100000 0x0400>;
686			clocks = <&ccu CLK_BUS_OTG>;
687			resets = <&ccu RST_BUS_OTG>;
688			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
689			interrupt-names = "mc";
690			phys = <&usbphy 0>;
691			phy-names = "usb";
692			extcon = <&usbphy 0>;
693			status = "disabled";
694		};
695
696		usbphy: phy@5100400 {
697			compatible = "allwinner,sun50i-h616-usb-phy";
698			reg = <0x05100400 0x24>,
699			      <0x05101800 0x14>,
700			      <0x05200800 0x14>,
701			      <0x05310800 0x14>,
702			      <0x05311800 0x14>;
703			reg-names = "phy_ctrl",
704				    "pmu0",
705				    "pmu1",
706				    "pmu2",
707				    "pmu3";
708			clocks = <&ccu CLK_USB_PHY0>,
709				 <&ccu CLK_USB_PHY1>,
710				 <&ccu CLK_USB_PHY2>,
711				 <&ccu CLK_USB_PHY3>,
712				 <&ccu CLK_BUS_EHCI2>;
713			clock-names = "usb0_phy",
714				      "usb1_phy",
715				      "usb2_phy",
716				      "usb3_phy",
717				      "pmu2_clk";
718			resets = <&ccu RST_USB_PHY0>,
719				 <&ccu RST_USB_PHY1>,
720				 <&ccu RST_USB_PHY2>,
721				 <&ccu RST_USB_PHY3>;
722			reset-names = "usb0_reset",
723				      "usb1_reset",
724				      "usb2_reset",
725				      "usb3_reset";
726			status = "disabled";
727			#phy-cells = <1>;
728		};
729
730		ehci0: usb@5101000 {
731			compatible = "allwinner,sun50i-h616-ehci",
732				     "generic-ehci";
733			reg = <0x05101000 0x100>;
734			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
735			clocks = <&ccu CLK_BUS_OHCI0>,
736				 <&ccu CLK_BUS_EHCI0>,
737				 <&ccu CLK_USB_OHCI0>;
738			resets = <&ccu RST_BUS_OHCI0>,
739				 <&ccu RST_BUS_EHCI0>;
740			phys = <&usbphy 0>;
741			phy-names = "usb";
742			status = "disabled";
743		};
744
745		ohci0: usb@5101400 {
746			compatible = "allwinner,sun50i-h616-ohci",
747				     "generic-ohci";
748			reg = <0x05101400 0x100>;
749			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
750			clocks = <&ccu CLK_BUS_OHCI0>,
751				 <&ccu CLK_USB_OHCI0>;
752			resets = <&ccu RST_BUS_OHCI0>;
753			phys = <&usbphy 0>;
754			phy-names = "usb";
755			status = "disabled";
756		};
757
758		ehci1: usb@5200000 {
759			compatible = "allwinner,sun50i-h616-ehci",
760				     "generic-ehci";
761			reg = <0x05200000 0x100>;
762			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
763			clocks = <&ccu CLK_BUS_OHCI1>,
764				 <&ccu CLK_BUS_EHCI1>,
765				 <&ccu CLK_USB_OHCI1>;
766			resets = <&ccu RST_BUS_OHCI1>,
767				 <&ccu RST_BUS_EHCI1>;
768			phys = <&usbphy 1>;
769			phy-names = "usb";
770			status = "disabled";
771		};
772
773		ohci1: usb@5200400 {
774			compatible = "allwinner,sun50i-h616-ohci",
775				     "generic-ohci";
776			reg = <0x05200400 0x100>;
777			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
778			clocks = <&ccu CLK_BUS_OHCI1>,
779				 <&ccu CLK_USB_OHCI1>;
780			resets = <&ccu RST_BUS_OHCI1>;
781			phys = <&usbphy 1>;
782			phy-names = "usb";
783			status = "disabled";
784		};
785
786		ehci2: usb@5310000 {
787			compatible = "allwinner,sun50i-h616-ehci",
788				     "generic-ehci";
789			reg = <0x05310000 0x100>;
790			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
791			clocks = <&ccu CLK_BUS_OHCI2>,
792				 <&ccu CLK_BUS_EHCI2>,
793				 <&ccu CLK_USB_OHCI2>;
794			resets = <&ccu RST_BUS_OHCI2>,
795				 <&ccu RST_BUS_EHCI2>;
796			phys = <&usbphy 2>;
797			phy-names = "usb";
798			status = "disabled";
799		};
800
801		ohci2: usb@5310400 {
802			compatible = "allwinner,sun50i-h616-ohci",
803				     "generic-ohci";
804			reg = <0x05310400 0x100>;
805			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
806			clocks = <&ccu CLK_BUS_OHCI2>,
807				 <&ccu CLK_USB_OHCI2>;
808			resets = <&ccu RST_BUS_OHCI2>;
809			phys = <&usbphy 2>;
810			phy-names = "usb";
811			status = "disabled";
812		};
813
814		ehci3: usb@5311000 {
815			compatible = "allwinner,sun50i-h616-ehci",
816				     "generic-ehci";
817			reg = <0x05311000 0x100>;
818			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
819			clocks = <&ccu CLK_BUS_OHCI3>,
820				 <&ccu CLK_BUS_EHCI3>,
821				 <&ccu CLK_USB_OHCI3>;
822			resets = <&ccu RST_BUS_OHCI3>,
823				 <&ccu RST_BUS_EHCI3>;
824			phys = <&usbphy 3>;
825			phy-names = "usb";
826			status = "disabled";
827		};
828
829		ohci3: usb@5311400 {
830			compatible = "allwinner,sun50i-h616-ohci",
831				     "generic-ohci";
832			reg = <0x05311400 0x100>;
833			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
834			clocks = <&ccu CLK_BUS_OHCI3>,
835				 <&ccu CLK_USB_OHCI3>;
836			resets = <&ccu RST_BUS_OHCI3>;
837			phys = <&usbphy 3>;
838			phy-names = "usb";
839			status = "disabled";
840		};
841
842		rtc: rtc@7000000 {
843			compatible = "allwinner,sun50i-h616-rtc";
844			reg = <0x07000000 0x400>;
845			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
846			clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>,
847				 <&ccu CLK_PLL_SYSTEM_32K>;
848			clock-names = "bus", "hosc",
849				      "pll-32k";
850			#clock-cells = <1>;
851		};
852
853		r_ccu: clock@7010000 {
854			compatible = "allwinner,sun50i-h616-r-ccu";
855			reg = <0x07010000 0x210>;
856			clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
857				 <&ccu CLK_PLL_PERIPH0>;
858			clock-names = "hosc", "losc", "iosc", "pll-periph";
859			#clock-cells = <1>;
860			#reset-cells = <1>;
861		};
862
863		nmi_intc: interrupt-controller@7010320 {
864			compatible = "allwinner,sun50i-h616-nmi",
865				     "allwinner,sun9i-a80-nmi";
866			reg = <0x07010320 0xc>;
867			interrupt-controller;
868			#interrupt-cells = <2>;
869			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
870		};
871
872		r_pio: pinctrl@7022000 {
873			compatible = "allwinner,sun50i-h616-r-pinctrl";
874			reg = <0x07022000 0x400>;
875			clocks = <&r_ccu CLK_R_APB1>, <&osc24M>,
876				 <&rtc CLK_OSC32K>;
877			clock-names = "apb", "hosc", "losc";
878			gpio-controller;
879			#gpio-cells = <3>;
880
881			/omit-if-no-ref/
882			r_i2c_pins: r-i2c-pins {
883				pins = "PL0", "PL1";
884				function = "s_i2c";
885			};
886
887			r_rsb_pins: r-rsb-pins {
888				pins = "PL0", "PL1";
889				function = "s_rsb";
890			};
891		};
892
893		ir: ir@7040000 {
894			compatible = "allwinner,sun50i-h616-ir",
895				     "allwinner,sun6i-a31-ir";
896			reg = <0x07040000 0x400>;
897			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
898			clocks = <&r_ccu CLK_R_APB1_IR>,
899				 <&r_ccu CLK_IR>;
900			clock-names = "apb", "ir";
901			resets = <&r_ccu RST_R_APB1_IR>;
902			pinctrl-names = "default";
903			pinctrl-0 = <&ir_rx_pin>;
904			status = "disabled";
905		};
906
907		r_i2c: i2c@7081400 {
908			compatible = "allwinner,sun50i-h616-i2c",
909				     "allwinner,sun8i-v536-i2c",
910				     "allwinner,sun6i-a31-i2c";
911			reg = <0x07081400 0x400>;
912			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
913			clocks = <&r_ccu CLK_R_APB2_I2C>;
914			dmas = <&dma 48>, <&dma 48>;
915			dma-names = "rx", "tx";
916			resets = <&r_ccu RST_R_APB2_I2C>;
917			status = "disabled";
918			#address-cells = <1>;
919			#size-cells = <0>;
920		};
921
922		r_rsb: rsb@7083000 {
923			compatible = "allwinner,sun50i-h616-rsb",
924				     "allwinner,sun8i-a23-rsb";
925			reg = <0x07083000 0x400>;
926			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
927			clocks = <&r_ccu CLK_R_APB2_RSB>;
928			clock-frequency = <3000000>;
929			resets = <&r_ccu RST_R_APB2_RSB>;
930			pinctrl-names = "default";
931			pinctrl-0 = <&r_rsb_pins>;
932			status = "disabled";
933			#address-cells = <1>;
934			#size-cells = <0>;
935		};
936	};
937
938	thermal-zones {
939		cpu-thermal {
940			polling-delay-passive = <500>;
941			polling-delay = <1000>;
942			thermal-sensors = <&ths 2>;
943			sustainable-power = <1000>;
944
945			trips {
946				cpu_threshold: cpu-trip-0 {
947					temperature = <60000>;
948					type = "passive";
949					hysteresis = <0>;
950				};
951				cpu_target: cpu-trip-1 {
952					temperature = <70000>;
953					type = "passive";
954					hysteresis = <0>;
955				};
956				cpu_critical: cpu-trip-2 {
957					temperature = <110000>;
958					type = "critical";
959					hysteresis = <0>;
960				};
961			};
962		};
963
964		gpu-thermal {
965			polling-delay-passive = <500>;
966			polling-delay = <1000>;
967			thermal-sensors = <&ths 0>;
968			sustainable-power = <1100>;
969
970			trips {
971				gpu_temp_critical: gpu-trip-0 {
972					temperature = <110000>;
973					type = "critical";
974					hysteresis = <0>;
975				};
976			};
977		};
978
979		ve-thermal {
980			polling-delay-passive = <0>;
981			polling-delay = <0>;
982			thermal-sensors = <&ths 1>;
983
984			trips {
985				ve_temp_critical: ve-trip-0 {
986					temperature = <110000>;
987					type = "critical";
988					hysteresis = <0>;
989				};
990			};
991		};
992
993		ddr-thermal {
994			polling-delay-passive = <0>;
995			polling-delay = <0>;
996			thermal-sensors = <&ths 3>;
997
998			trips {
999				ddr_temp_critical: ddr-trip-0 {
1000					temperature = <110000>;
1001					type = "critical";
1002					hysteresis = <0>;
1003				};
1004			};
1005		};
1006	};
1007};
1008