1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2020 Arm Ltd. 3// based on the H6 dtsi, which is: 4// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-h616-ccu.h> 8#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 9#include <dt-bindings/clock/sun6i-rtc.h> 10#include <dt-bindings/reset/sun50i-h616-ccu.h> 11#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a53"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 clocks = <&ccu CLK_CPUX>; 29 }; 30 31 cpu1: cpu@1 { 32 compatible = "arm,cortex-a53"; 33 device_type = "cpu"; 34 reg = <1>; 35 enable-method = "psci"; 36 clocks = <&ccu CLK_CPUX>; 37 }; 38 39 cpu2: cpu@2 { 40 compatible = "arm,cortex-a53"; 41 device_type = "cpu"; 42 reg = <2>; 43 enable-method = "psci"; 44 clocks = <&ccu CLK_CPUX>; 45 }; 46 47 cpu3: cpu@3 { 48 compatible = "arm,cortex-a53"; 49 device_type = "cpu"; 50 reg = <3>; 51 enable-method = "psci"; 52 clocks = <&ccu CLK_CPUX>; 53 }; 54 }; 55 56 reserved-memory { 57 #address-cells = <2>; 58 #size-cells = <2>; 59 ranges; 60 61 /* 62 * 256 KiB reserved for Trusted Firmware-A (BL31). 63 * This is added by BL31 itself, but some bootloaders fail 64 * to propagate this into the DTB handed to kernels. 65 */ 66 secmon@40000000 { 67 reg = <0x0 0x40000000 0x0 0x40000>; 68 no-map; 69 }; 70 }; 71 72 osc24M: osc24M-clk { 73 #clock-cells = <0>; 74 compatible = "fixed-clock"; 75 clock-frequency = <24000000>; 76 clock-output-names = "osc24M"; 77 }; 78 79 pmu { 80 compatible = "arm,cortex-a53-pmu"; 81 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 85 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 86 }; 87 88 psci { 89 compatible = "arm,psci-0.2"; 90 method = "smc"; 91 }; 92 93 timer { 94 compatible = "arm,armv8-timer"; 95 arm,no-tick-in-suspend; 96 interrupts = <GIC_PPI 13 97 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 14 99 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 100 <GIC_PPI 11 101 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 102 <GIC_PPI 10 103 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 104 }; 105 106 soc { 107 compatible = "simple-bus"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 ranges = <0x0 0x0 0x0 0x40000000>; 111 112 syscon: syscon@3000000 { 113 compatible = "allwinner,sun50i-h616-system-control"; 114 reg = <0x03000000 0x1000>; 115 #address-cells = <1>; 116 #size-cells = <1>; 117 ranges; 118 119 sram_c: sram@28000 { 120 compatible = "mmio-sram"; 121 reg = <0x00028000 0x30000>; 122 #address-cells = <1>; 123 #size-cells = <1>; 124 ranges = <0 0x00028000 0x30000>; 125 }; 126 }; 127 128 ccu: clock@3001000 { 129 compatible = "allwinner,sun50i-h616-ccu"; 130 reg = <0x03001000 0x1000>; 131 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; 132 clock-names = "hosc", "losc", "iosc"; 133 #clock-cells = <1>; 134 #reset-cells = <1>; 135 }; 136 137 dma: dma-controller@3002000 { 138 compatible = "allwinner,sun50i-h616-dma", 139 "allwinner,sun50i-a100-dma"; 140 reg = <0x03002000 0x1000>; 141 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 143 clock-names = "bus", "mbus"; 144 dma-channels = <16>; 145 dma-requests = <49>; 146 resets = <&ccu RST_BUS_DMA>; 147 #dma-cells = <1>; 148 }; 149 150 sid: efuse@3006000 { 151 compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; 152 reg = <0x03006000 0x1000>; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 156 ths_calibration: thermal-sensor-calibration@14 { 157 reg = <0x14 0x8>; 158 }; 159 }; 160 161 watchdog: watchdog@30090a0 { 162 compatible = "allwinner,sun50i-h616-wdt", 163 "allwinner,sun6i-a31-wdt"; 164 reg = <0x030090a0 0x20>; 165 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&osc24M>; 167 }; 168 169 pio: pinctrl@300b000 { 170 compatible = "allwinner,sun50i-h616-pinctrl"; 171 reg = <0x0300b000 0x400>; 172 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 181 clock-names = "apb", "hosc", "losc"; 182 gpio-controller; 183 #gpio-cells = <3>; 184 interrupt-controller; 185 #interrupt-cells = <3>; 186 187 ext_rgmii_pins: rgmii-pins { 188 pins = "PI0", "PI1", "PI2", "PI3", "PI4", 189 "PI5", "PI7", "PI8", "PI9", "PI10", 190 "PI11", "PI12", "PI13", "PI14", "PI15", 191 "PI16"; 192 function = "emac0"; 193 drive-strength = <40>; 194 }; 195 196 i2c0_pins: i2c0-pins { 197 pins = "PI6", "PI7"; 198 function = "i2c0"; 199 }; 200 201 i2c3_ph_pins: i2c3-ph-pins { 202 pins = "PH4", "PH5"; 203 function = "i2c3"; 204 }; 205 206 ir_rx_pin: ir-rx-pin { 207 pins = "PH10"; 208 function = "ir_rx"; 209 }; 210 211 mmc0_pins: mmc0-pins { 212 pins = "PF0", "PF1", "PF2", "PF3", 213 "PF4", "PF5"; 214 function = "mmc0"; 215 drive-strength = <30>; 216 bias-pull-up; 217 }; 218 219 /omit-if-no-ref/ 220 mmc1_pins: mmc1-pins { 221 pins = "PG0", "PG1", "PG2", "PG3", 222 "PG4", "PG5"; 223 function = "mmc1"; 224 drive-strength = <30>; 225 bias-pull-up; 226 }; 227 228 mmc2_pins: mmc2-pins { 229 pins = "PC0", "PC1", "PC5", "PC6", 230 "PC8", "PC9", "PC10", "PC11", 231 "PC13", "PC14", "PC15", "PC16"; 232 function = "mmc2"; 233 drive-strength = <30>; 234 bias-pull-up; 235 }; 236 237 /omit-if-no-ref/ 238 spi0_pins: spi0-pins { 239 pins = "PC0", "PC2", "PC4"; 240 function = "spi0"; 241 }; 242 243 /omit-if-no-ref/ 244 spi0_cs0_pin: spi0-cs0-pin { 245 pins = "PC3"; 246 function = "spi0"; 247 }; 248 249 /omit-if-no-ref/ 250 spi1_pins: spi1-pins { 251 pins = "PH6", "PH7", "PH8"; 252 function = "spi1"; 253 }; 254 255 /omit-if-no-ref/ 256 spi1_cs0_pin: spi1-cs0-pin { 257 pins = "PH5"; 258 function = "spi1"; 259 }; 260 261 spdif_tx_pin: spdif-tx-pin { 262 pins = "PH4"; 263 function = "spdif"; 264 }; 265 266 uart0_ph_pins: uart0-ph-pins { 267 pins = "PH0", "PH1"; 268 function = "uart0"; 269 }; 270 271 /omit-if-no-ref/ 272 uart1_pins: uart1-pins { 273 pins = "PG6", "PG7"; 274 function = "uart1"; 275 }; 276 277 /omit-if-no-ref/ 278 uart1_rts_cts_pins: uart1-rts-cts-pins { 279 pins = "PG8", "PG9"; 280 function = "uart1"; 281 }; 282 283 /omit-if-no-ref/ 284 x32clk_fanout_pin: x32clk-fanout-pin { 285 pins = "PG10"; 286 function = "clock"; 287 }; 288 }; 289 290 gic: interrupt-controller@3021000 { 291 compatible = "arm,gic-400"; 292 reg = <0x03021000 0x1000>, 293 <0x03022000 0x2000>, 294 <0x03024000 0x2000>, 295 <0x03026000 0x2000>; 296 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 297 interrupt-controller; 298 #interrupt-cells = <3>; 299 }; 300 301 mmc0: mmc@4020000 { 302 compatible = "allwinner,sun50i-h616-mmc", 303 "allwinner,sun50i-a100-mmc"; 304 reg = <0x04020000 0x1000>; 305 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 306 clock-names = "ahb", "mmc"; 307 resets = <&ccu RST_BUS_MMC0>; 308 reset-names = "ahb"; 309 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 310 pinctrl-names = "default"; 311 pinctrl-0 = <&mmc0_pins>; 312 status = "disabled"; 313 max-frequency = <150000000>; 314 cap-sd-highspeed; 315 cap-mmc-highspeed; 316 mmc-ddr-3_3v; 317 cap-sdio-irq; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 }; 321 322 mmc1: mmc@4021000 { 323 compatible = "allwinner,sun50i-h616-mmc", 324 "allwinner,sun50i-a100-mmc"; 325 reg = <0x04021000 0x1000>; 326 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 327 clock-names = "ahb", "mmc"; 328 resets = <&ccu RST_BUS_MMC1>; 329 reset-names = "ahb"; 330 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 331 pinctrl-names = "default"; 332 pinctrl-0 = <&mmc1_pins>; 333 status = "disabled"; 334 max-frequency = <150000000>; 335 cap-sd-highspeed; 336 cap-mmc-highspeed; 337 mmc-ddr-3_3v; 338 cap-sdio-irq; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 }; 342 343 mmc2: mmc@4022000 { 344 compatible = "allwinner,sun50i-h616-emmc", 345 "allwinner,sun50i-a100-emmc"; 346 reg = <0x04022000 0x1000>; 347 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 348 clock-names = "ahb", "mmc"; 349 resets = <&ccu RST_BUS_MMC2>; 350 reset-names = "ahb"; 351 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 352 pinctrl-names = "default"; 353 pinctrl-0 = <&mmc2_pins>; 354 status = "disabled"; 355 max-frequency = <150000000>; 356 cap-sd-highspeed; 357 cap-mmc-highspeed; 358 mmc-ddr-3_3v; 359 cap-sdio-irq; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 }; 363 364 uart0: serial@5000000 { 365 compatible = "snps,dw-apb-uart"; 366 reg = <0x05000000 0x400>; 367 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 368 reg-shift = <2>; 369 reg-io-width = <4>; 370 clocks = <&ccu CLK_BUS_UART0>; 371 dmas = <&dma 14>, <&dma 14>; 372 dma-names = "tx", "rx"; 373 resets = <&ccu RST_BUS_UART0>; 374 status = "disabled"; 375 }; 376 377 uart1: serial@5000400 { 378 compatible = "snps,dw-apb-uart"; 379 reg = <0x05000400 0x400>; 380 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 381 reg-shift = <2>; 382 reg-io-width = <4>; 383 clocks = <&ccu CLK_BUS_UART1>; 384 dmas = <&dma 15>, <&dma 15>; 385 dma-names = "tx", "rx"; 386 resets = <&ccu RST_BUS_UART1>; 387 status = "disabled"; 388 }; 389 390 uart2: serial@5000800 { 391 compatible = "snps,dw-apb-uart"; 392 reg = <0x05000800 0x400>; 393 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 394 reg-shift = <2>; 395 reg-io-width = <4>; 396 clocks = <&ccu CLK_BUS_UART2>; 397 dmas = <&dma 16>, <&dma 16>; 398 dma-names = "tx", "rx"; 399 resets = <&ccu RST_BUS_UART2>; 400 status = "disabled"; 401 }; 402 403 uart3: serial@5000c00 { 404 compatible = "snps,dw-apb-uart"; 405 reg = <0x05000c00 0x400>; 406 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 407 reg-shift = <2>; 408 reg-io-width = <4>; 409 clocks = <&ccu CLK_BUS_UART3>; 410 dmas = <&dma 17>, <&dma 17>; 411 dma-names = "tx", "rx"; 412 resets = <&ccu RST_BUS_UART3>; 413 status = "disabled"; 414 }; 415 416 uart4: serial@5001000 { 417 compatible = "snps,dw-apb-uart"; 418 reg = <0x05001000 0x400>; 419 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 420 reg-shift = <2>; 421 reg-io-width = <4>; 422 clocks = <&ccu CLK_BUS_UART4>; 423 dmas = <&dma 18>, <&dma 18>; 424 dma-names = "tx", "rx"; 425 resets = <&ccu RST_BUS_UART4>; 426 status = "disabled"; 427 }; 428 429 uart5: serial@5001400 { 430 compatible = "snps,dw-apb-uart"; 431 reg = <0x05001400 0x400>; 432 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 433 reg-shift = <2>; 434 reg-io-width = <4>; 435 clocks = <&ccu CLK_BUS_UART5>; 436 dmas = <&dma 19>, <&dma 19>; 437 dma-names = "tx", "rx"; 438 resets = <&ccu RST_BUS_UART5>; 439 status = "disabled"; 440 }; 441 442 i2c0: i2c@5002000 { 443 compatible = "allwinner,sun50i-h616-i2c", 444 "allwinner,sun8i-v536-i2c", 445 "allwinner,sun6i-a31-i2c"; 446 reg = <0x05002000 0x400>; 447 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&ccu CLK_BUS_I2C0>; 449 dmas = <&dma 43>, <&dma 43>; 450 dma-names = "rx", "tx"; 451 resets = <&ccu RST_BUS_I2C0>; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&i2c0_pins>; 454 status = "disabled"; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 }; 458 459 i2c1: i2c@5002400 { 460 compatible = "allwinner,sun50i-h616-i2c", 461 "allwinner,sun8i-v536-i2c", 462 "allwinner,sun6i-a31-i2c"; 463 reg = <0x05002400 0x400>; 464 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 465 clocks = <&ccu CLK_BUS_I2C1>; 466 dmas = <&dma 44>, <&dma 44>; 467 dma-names = "rx", "tx"; 468 resets = <&ccu RST_BUS_I2C1>; 469 status = "disabled"; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 }; 473 474 i2c2: i2c@5002800 { 475 compatible = "allwinner,sun50i-h616-i2c", 476 "allwinner,sun8i-v536-i2c", 477 "allwinner,sun6i-a31-i2c"; 478 reg = <0x05002800 0x400>; 479 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&ccu CLK_BUS_I2C2>; 481 dmas = <&dma 45>, <&dma 45>; 482 dma-names = "rx", "tx"; 483 resets = <&ccu RST_BUS_I2C2>; 484 status = "disabled"; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 }; 488 489 i2c3: i2c@5002c00 { 490 compatible = "allwinner,sun50i-h616-i2c", 491 "allwinner,sun8i-v536-i2c", 492 "allwinner,sun6i-a31-i2c"; 493 reg = <0x05002c00 0x400>; 494 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 495 clocks = <&ccu CLK_BUS_I2C3>; 496 dmas = <&dma 46>, <&dma 46>; 497 dma-names = "rx", "tx"; 498 resets = <&ccu RST_BUS_I2C3>; 499 status = "disabled"; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 }; 503 504 i2c4: i2c@5003000 { 505 compatible = "allwinner,sun50i-h616-i2c", 506 "allwinner,sun8i-v536-i2c", 507 "allwinner,sun6i-a31-i2c"; 508 reg = <0x05003000 0x400>; 509 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&ccu CLK_BUS_I2C4>; 511 dmas = <&dma 47>, <&dma 47>; 512 dma-names = "rx", "tx"; 513 resets = <&ccu RST_BUS_I2C4>; 514 status = "disabled"; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 }; 518 519 spi0: spi@5010000 { 520 compatible = "allwinner,sun50i-h616-spi", 521 "allwinner,sun8i-h3-spi"; 522 reg = <0x05010000 0x1000>; 523 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 524 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 525 clock-names = "ahb", "mod"; 526 dmas = <&dma 22>, <&dma 22>; 527 dma-names = "rx", "tx"; 528 resets = <&ccu RST_BUS_SPI0>; 529 status = "disabled"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 }; 533 534 spi1: spi@5011000 { 535 compatible = "allwinner,sun50i-h616-spi", 536 "allwinner,sun8i-h3-spi"; 537 reg = <0x05011000 0x1000>; 538 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 540 clock-names = "ahb", "mod"; 541 dmas = <&dma 23>, <&dma 23>; 542 dma-names = "rx", "tx"; 543 resets = <&ccu RST_BUS_SPI1>; 544 status = "disabled"; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 }; 548 549 emac0: ethernet@5020000 { 550 compatible = "allwinner,sun50i-h616-emac0", 551 "allwinner,sun50i-a64-emac"; 552 reg = <0x05020000 0x10000>; 553 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 554 interrupt-names = "macirq"; 555 clocks = <&ccu CLK_BUS_EMAC0>; 556 clock-names = "stmmaceth"; 557 resets = <&ccu RST_BUS_EMAC0>; 558 reset-names = "stmmaceth"; 559 syscon = <&syscon>; 560 status = "disabled"; 561 562 mdio0: mdio { 563 compatible = "snps,dwmac-mdio"; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 }; 567 }; 568 569 spdif: spdif@5093000 { 570 compatible = "allwinner,sun50i-h616-spdif"; 571 reg = <0x05093000 0x400>; 572 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 574 clock-names = "apb", "spdif"; 575 resets = <&ccu RST_BUS_SPDIF>; 576 dmas = <&dma 2>; 577 dma-names = "tx"; 578 pinctrl-names = "default"; 579 pinctrl-0 = <&spdif_tx_pin>; 580 #sound-dai-cells = <0>; 581 status = "disabled"; 582 }; 583 584 ths: thermal-sensor@5070400 { 585 compatible = "allwinner,sun50i-h616-ths"; 586 reg = <0x05070400 0x400>; 587 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&ccu CLK_BUS_THS>; 589 clock-names = "bus"; 590 resets = <&ccu RST_BUS_THS>; 591 nvmem-cells = <&ths_calibration>; 592 nvmem-cell-names = "calibration"; 593 allwinner,sram = <&syscon>; 594 #thermal-sensor-cells = <1>; 595 }; 596 597 usbotg: usb@5100000 { 598 compatible = "allwinner,sun50i-h616-musb", 599 "allwinner,sun8i-h3-musb"; 600 reg = <0x05100000 0x0400>; 601 clocks = <&ccu CLK_BUS_OTG>; 602 resets = <&ccu RST_BUS_OTG>; 603 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 604 interrupt-names = "mc"; 605 phys = <&usbphy 0>; 606 phy-names = "usb"; 607 extcon = <&usbphy 0>; 608 status = "disabled"; 609 }; 610 611 usbphy: phy@5100400 { 612 compatible = "allwinner,sun50i-h616-usb-phy"; 613 reg = <0x05100400 0x24>, 614 <0x05101800 0x14>, 615 <0x05200800 0x14>, 616 <0x05310800 0x14>, 617 <0x05311800 0x14>; 618 reg-names = "phy_ctrl", 619 "pmu0", 620 "pmu1", 621 "pmu2", 622 "pmu3"; 623 clocks = <&ccu CLK_USB_PHY0>, 624 <&ccu CLK_USB_PHY1>, 625 <&ccu CLK_USB_PHY2>, 626 <&ccu CLK_USB_PHY3>, 627 <&ccu CLK_BUS_EHCI2>; 628 clock-names = "usb0_phy", 629 "usb1_phy", 630 "usb2_phy", 631 "usb3_phy", 632 "pmu2_clk"; 633 resets = <&ccu RST_USB_PHY0>, 634 <&ccu RST_USB_PHY1>, 635 <&ccu RST_USB_PHY2>, 636 <&ccu RST_USB_PHY3>; 637 reset-names = "usb0_reset", 638 "usb1_reset", 639 "usb2_reset", 640 "usb3_reset"; 641 status = "disabled"; 642 #phy-cells = <1>; 643 }; 644 645 ehci0: usb@5101000 { 646 compatible = "allwinner,sun50i-h616-ehci", 647 "generic-ehci"; 648 reg = <0x05101000 0x100>; 649 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&ccu CLK_BUS_OHCI0>, 651 <&ccu CLK_BUS_EHCI0>, 652 <&ccu CLK_USB_OHCI0>; 653 resets = <&ccu RST_BUS_OHCI0>, 654 <&ccu RST_BUS_EHCI0>; 655 phys = <&usbphy 0>; 656 phy-names = "usb"; 657 status = "disabled"; 658 }; 659 660 ohci0: usb@5101400 { 661 compatible = "allwinner,sun50i-h616-ohci", 662 "generic-ohci"; 663 reg = <0x05101400 0x100>; 664 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 665 clocks = <&ccu CLK_BUS_OHCI0>, 666 <&ccu CLK_USB_OHCI0>; 667 resets = <&ccu RST_BUS_OHCI0>; 668 phys = <&usbphy 0>; 669 phy-names = "usb"; 670 status = "disabled"; 671 }; 672 673 ehci1: usb@5200000 { 674 compatible = "allwinner,sun50i-h616-ehci", 675 "generic-ehci"; 676 reg = <0x05200000 0x100>; 677 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&ccu CLK_BUS_OHCI1>, 679 <&ccu CLK_BUS_EHCI1>, 680 <&ccu CLK_USB_OHCI1>; 681 resets = <&ccu RST_BUS_OHCI1>, 682 <&ccu RST_BUS_EHCI1>; 683 phys = <&usbphy 1>; 684 phy-names = "usb"; 685 status = "disabled"; 686 }; 687 688 ohci1: usb@5200400 { 689 compatible = "allwinner,sun50i-h616-ohci", 690 "generic-ohci"; 691 reg = <0x05200400 0x100>; 692 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&ccu CLK_BUS_OHCI1>, 694 <&ccu CLK_USB_OHCI1>; 695 resets = <&ccu RST_BUS_OHCI1>; 696 phys = <&usbphy 1>; 697 phy-names = "usb"; 698 status = "disabled"; 699 }; 700 701 ehci2: usb@5310000 { 702 compatible = "allwinner,sun50i-h616-ehci", 703 "generic-ehci"; 704 reg = <0x05310000 0x100>; 705 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&ccu CLK_BUS_OHCI2>, 707 <&ccu CLK_BUS_EHCI2>, 708 <&ccu CLK_USB_OHCI2>; 709 resets = <&ccu RST_BUS_OHCI2>, 710 <&ccu RST_BUS_EHCI2>; 711 phys = <&usbphy 2>; 712 phy-names = "usb"; 713 status = "disabled"; 714 }; 715 716 ohci2: usb@5310400 { 717 compatible = "allwinner,sun50i-h616-ohci", 718 "generic-ohci"; 719 reg = <0x05310400 0x100>; 720 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&ccu CLK_BUS_OHCI2>, 722 <&ccu CLK_USB_OHCI2>; 723 resets = <&ccu RST_BUS_OHCI2>; 724 phys = <&usbphy 2>; 725 phy-names = "usb"; 726 status = "disabled"; 727 }; 728 729 ehci3: usb@5311000 { 730 compatible = "allwinner,sun50i-h616-ehci", 731 "generic-ehci"; 732 reg = <0x05311000 0x100>; 733 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 734 clocks = <&ccu CLK_BUS_OHCI3>, 735 <&ccu CLK_BUS_EHCI3>, 736 <&ccu CLK_USB_OHCI3>; 737 resets = <&ccu RST_BUS_OHCI3>, 738 <&ccu RST_BUS_EHCI3>; 739 phys = <&usbphy 3>; 740 phy-names = "usb"; 741 status = "disabled"; 742 }; 743 744 ohci3: usb@5311400 { 745 compatible = "allwinner,sun50i-h616-ohci", 746 "generic-ohci"; 747 reg = <0x05311400 0x100>; 748 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 749 clocks = <&ccu CLK_BUS_OHCI3>, 750 <&ccu CLK_USB_OHCI3>; 751 resets = <&ccu RST_BUS_OHCI3>; 752 phys = <&usbphy 3>; 753 phy-names = "usb"; 754 status = "disabled"; 755 }; 756 757 rtc: rtc@7000000 { 758 compatible = "allwinner,sun50i-h616-rtc"; 759 reg = <0x07000000 0x400>; 760 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, 762 <&ccu CLK_PLL_SYSTEM_32K>; 763 clock-names = "bus", "hosc", 764 "pll-32k"; 765 #clock-cells = <1>; 766 }; 767 768 r_ccu: clock@7010000 { 769 compatible = "allwinner,sun50i-h616-r-ccu"; 770 reg = <0x07010000 0x210>; 771 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 772 <&ccu CLK_PLL_PERIPH0>; 773 clock-names = "hosc", "losc", "iosc", "pll-periph"; 774 #clock-cells = <1>; 775 #reset-cells = <1>; 776 }; 777 778 r_pio: pinctrl@7022000 { 779 compatible = "allwinner,sun50i-h616-r-pinctrl"; 780 reg = <0x07022000 0x400>; 781 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, 782 <&rtc CLK_OSC32K>; 783 clock-names = "apb", "hosc", "losc"; 784 gpio-controller; 785 #gpio-cells = <3>; 786 787 /omit-if-no-ref/ 788 r_i2c_pins: r-i2c-pins { 789 pins = "PL0", "PL1"; 790 function = "s_i2c"; 791 }; 792 793 r_rsb_pins: r-rsb-pins { 794 pins = "PL0", "PL1"; 795 function = "s_rsb"; 796 }; 797 }; 798 799 ir: ir@7040000 { 800 compatible = "allwinner,sun50i-h616-ir", 801 "allwinner,sun6i-a31-ir"; 802 reg = <0x07040000 0x400>; 803 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 804 clocks = <&r_ccu CLK_R_APB1_IR>, 805 <&r_ccu CLK_IR>; 806 clock-names = "apb", "ir"; 807 resets = <&r_ccu RST_R_APB1_IR>; 808 pinctrl-names = "default"; 809 pinctrl-0 = <&ir_rx_pin>; 810 status = "disabled"; 811 }; 812 813 r_i2c: i2c@7081400 { 814 compatible = "allwinner,sun50i-h616-i2c", 815 "allwinner,sun8i-v536-i2c", 816 "allwinner,sun6i-a31-i2c"; 817 reg = <0x07081400 0x400>; 818 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 819 clocks = <&r_ccu CLK_R_APB2_I2C>; 820 dmas = <&dma 48>, <&dma 48>; 821 dma-names = "rx", "tx"; 822 resets = <&r_ccu RST_R_APB2_I2C>; 823 status = "disabled"; 824 #address-cells = <1>; 825 #size-cells = <0>; 826 }; 827 828 r_rsb: rsb@7083000 { 829 compatible = "allwinner,sun50i-h616-rsb", 830 "allwinner,sun8i-a23-rsb"; 831 reg = <0x07083000 0x400>; 832 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&r_ccu CLK_R_APB2_RSB>; 834 clock-frequency = <3000000>; 835 resets = <&r_ccu RST_R_APB2_RSB>; 836 pinctrl-names = "default"; 837 pinctrl-0 = <&r_rsb_pins>; 838 status = "disabled"; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 }; 842 }; 843 844 thermal-zones { 845 cpu-thermal { 846 polling-delay-passive = <500>; 847 polling-delay = <1000>; 848 thermal-sensors = <&ths 2>; 849 sustainable-power = <1000>; 850 851 trips { 852 cpu_threshold: cpu-trip-0 { 853 temperature = <60000>; 854 type = "passive"; 855 hysteresis = <0>; 856 }; 857 cpu_target: cpu-trip-1 { 858 temperature = <70000>; 859 type = "passive"; 860 hysteresis = <0>; 861 }; 862 cpu_critical: cpu-trip-2 { 863 temperature = <110000>; 864 type = "critical"; 865 hysteresis = <0>; 866 }; 867 }; 868 }; 869 870 gpu-thermal { 871 polling-delay-passive = <500>; 872 polling-delay = <1000>; 873 thermal-sensors = <&ths 0>; 874 sustainable-power = <1100>; 875 876 trips { 877 gpu_temp_critical: gpu-trip-0 { 878 temperature = <110000>; 879 type = "critical"; 880 hysteresis = <0>; 881 }; 882 }; 883 }; 884 885 ve-thermal { 886 polling-delay-passive = <0>; 887 polling-delay = <0>; 888 thermal-sensors = <&ths 1>; 889 890 trips { 891 ve_temp_critical: ve-trip-0 { 892 temperature = <110000>; 893 type = "critical"; 894 hysteresis = <0>; 895 }; 896 }; 897 }; 898 899 ddr-thermal { 900 polling-delay-passive = <0>; 901 polling-delay = <0>; 902 thermal-sensors = <&ths 3>; 903 904 trips { 905 ddr_temp_critical: ddr-trip-0 { 906 temperature = <110000>; 907 type = "critical"; 908 hysteresis = <0>; 909 }; 910 }; 911 }; 912 }; 913}; 914