1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2020 Arm Ltd. 3// based on the H6 dtsi, which is: 4// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-h616-ccu.h> 8#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 9#include <dt-bindings/clock/sun6i-rtc.h> 10#include <dt-bindings/reset/sun50i-h616-ccu.h> 11#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a53"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 clocks = <&ccu CLK_CPUX>; 29 #cooling-cells = <2>; 30 }; 31 32 cpu1: cpu@1 { 33 compatible = "arm,cortex-a53"; 34 device_type = "cpu"; 35 reg = <1>; 36 enable-method = "psci"; 37 clocks = <&ccu CLK_CPUX>; 38 #cooling-cells = <2>; 39 }; 40 41 cpu2: cpu@2 { 42 compatible = "arm,cortex-a53"; 43 device_type = "cpu"; 44 reg = <2>; 45 enable-method = "psci"; 46 clocks = <&ccu CLK_CPUX>; 47 #cooling-cells = <2>; 48 }; 49 50 cpu3: cpu@3 { 51 compatible = "arm,cortex-a53"; 52 device_type = "cpu"; 53 reg = <3>; 54 enable-method = "psci"; 55 clocks = <&ccu CLK_CPUX>; 56 #cooling-cells = <2>; 57 }; 58 }; 59 60 reserved-memory { 61 #address-cells = <2>; 62 #size-cells = <2>; 63 ranges; 64 65 /* 66 * 256 KiB reserved for Trusted Firmware-A (BL31). 67 * This is added by BL31 itself, but some bootloaders fail 68 * to propagate this into the DTB handed to kernels. 69 */ 70 secmon@40000000 { 71 reg = <0x0 0x40000000 0x0 0x40000>; 72 no-map; 73 }; 74 }; 75 76 osc24M: osc24M-clk { 77 #clock-cells = <0>; 78 compatible = "fixed-clock"; 79 clock-frequency = <24000000>; 80 clock-output-names = "osc24M"; 81 }; 82 83 pmu { 84 compatible = "arm,cortex-a53-pmu"; 85 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 87 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 88 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 89 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 90 }; 91 92 psci { 93 compatible = "arm,psci-0.2"; 94 method = "smc"; 95 }; 96 97 timer { 98 compatible = "arm,armv8-timer"; 99 arm,no-tick-in-suspend; 100 interrupts = <GIC_PPI 13 101 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 102 <GIC_PPI 14 103 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 104 <GIC_PPI 11 105 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 106 <GIC_PPI 10 107 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 108 }; 109 110 soc { 111 compatible = "simple-bus"; 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges = <0x0 0x0 0x0 0x40000000>; 115 116 syscon: syscon@3000000 { 117 compatible = "allwinner,sun50i-h616-system-control"; 118 reg = <0x03000000 0x1000>; 119 #address-cells = <1>; 120 #size-cells = <1>; 121 ranges; 122 123 sram_c: sram@28000 { 124 compatible = "mmio-sram"; 125 reg = <0x00028000 0x30000>; 126 #address-cells = <1>; 127 #size-cells = <1>; 128 ranges = <0 0x00028000 0x30000>; 129 }; 130 }; 131 132 ccu: clock@3001000 { 133 compatible = "allwinner,sun50i-h616-ccu"; 134 reg = <0x03001000 0x1000>; 135 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; 136 clock-names = "hosc", "losc", "iosc"; 137 #clock-cells = <1>; 138 #reset-cells = <1>; 139 }; 140 141 dma: dma-controller@3002000 { 142 compatible = "allwinner,sun50i-h616-dma", 143 "allwinner,sun50i-a100-dma"; 144 reg = <0x03002000 0x1000>; 145 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 147 clock-names = "bus", "mbus"; 148 dma-channels = <16>; 149 dma-requests = <49>; 150 resets = <&ccu RST_BUS_DMA>; 151 #dma-cells = <1>; 152 }; 153 154 sid: efuse@3006000 { 155 compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid"; 156 reg = <0x03006000 0x1000>; 157 #address-cells = <1>; 158 #size-cells = <1>; 159 160 ths_calibration: thermal-sensor-calibration@14 { 161 reg = <0x14 0x8>; 162 }; 163 164 cpu_speed_grade: cpu-speed-grade@0 { 165 reg = <0x0 2>; 166 }; 167 }; 168 169 watchdog: watchdog@30090a0 { 170 compatible = "allwinner,sun50i-h616-wdt", 171 "allwinner,sun6i-a31-wdt"; 172 reg = <0x030090a0 0x20>; 173 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 174 clocks = <&osc24M>; 175 }; 176 177 pio: pinctrl@300b000 { 178 compatible = "allwinner,sun50i-h616-pinctrl"; 179 reg = <0x0300b000 0x400>; 180 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 189 clock-names = "apb", "hosc", "losc"; 190 gpio-controller; 191 #gpio-cells = <3>; 192 interrupt-controller; 193 #interrupt-cells = <3>; 194 195 ext_rgmii_pins: rgmii-pins { 196 pins = "PI0", "PI1", "PI2", "PI3", "PI4", 197 "PI5", "PI7", "PI8", "PI9", "PI10", 198 "PI11", "PI12", "PI13", "PI14", "PI15", 199 "PI16"; 200 function = "emac0"; 201 drive-strength = <40>; 202 }; 203 204 i2c0_pins: i2c0-pins { 205 pins = "PI5", "PI6"; 206 function = "i2c0"; 207 }; 208 209 i2c3_ph_pins: i2c3-ph-pins { 210 pins = "PH4", "PH5"; 211 function = "i2c3"; 212 }; 213 214 ir_rx_pin: ir-rx-pin { 215 pins = "PH10"; 216 function = "ir_rx"; 217 }; 218 219 mmc0_pins: mmc0-pins { 220 pins = "PF0", "PF1", "PF2", "PF3", 221 "PF4", "PF5"; 222 function = "mmc0"; 223 drive-strength = <30>; 224 bias-pull-up; 225 }; 226 227 /omit-if-no-ref/ 228 mmc1_pins: mmc1-pins { 229 pins = "PG0", "PG1", "PG2", "PG3", 230 "PG4", "PG5"; 231 function = "mmc1"; 232 drive-strength = <30>; 233 bias-pull-up; 234 }; 235 236 mmc2_pins: mmc2-pins { 237 pins = "PC0", "PC1", "PC5", "PC6", 238 "PC8", "PC9", "PC10", "PC11", 239 "PC13", "PC14", "PC15", "PC16"; 240 function = "mmc2"; 241 drive-strength = <30>; 242 bias-pull-up; 243 }; 244 245 /omit-if-no-ref/ 246 spi0_pins: spi0-pins { 247 pins = "PC0", "PC2", "PC4"; 248 function = "spi0"; 249 }; 250 251 /omit-if-no-ref/ 252 spi0_cs0_pin: spi0-cs0-pin { 253 pins = "PC3"; 254 function = "spi0"; 255 }; 256 257 /omit-if-no-ref/ 258 spi1_pins: spi1-pins { 259 pins = "PH6", "PH7", "PH8"; 260 function = "spi1"; 261 }; 262 263 /omit-if-no-ref/ 264 spi1_cs0_pin: spi1-cs0-pin { 265 pins = "PH5"; 266 function = "spi1"; 267 }; 268 269 spdif_tx_pin: spdif-tx-pin { 270 pins = "PH4"; 271 function = "spdif"; 272 }; 273 274 uart0_ph_pins: uart0-ph-pins { 275 pins = "PH0", "PH1"; 276 function = "uart0"; 277 }; 278 279 /omit-if-no-ref/ 280 uart1_pins: uart1-pins { 281 pins = "PG6", "PG7"; 282 function = "uart1"; 283 }; 284 285 /omit-if-no-ref/ 286 uart1_rts_cts_pins: uart1-rts-cts-pins { 287 pins = "PG8", "PG9"; 288 function = "uart1"; 289 }; 290 291 /omit-if-no-ref/ 292 x32clk_fanout_pin: x32clk-fanout-pin { 293 pins = "PG10"; 294 function = "clock"; 295 }; 296 }; 297 298 gic: interrupt-controller@3021000 { 299 compatible = "arm,gic-400"; 300 reg = <0x03021000 0x1000>, 301 <0x03022000 0x2000>, 302 <0x03024000 0x2000>, 303 <0x03026000 0x2000>; 304 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 305 interrupt-controller; 306 #interrupt-cells = <3>; 307 }; 308 309 mmc0: mmc@4020000 { 310 compatible = "allwinner,sun50i-h616-mmc", 311 "allwinner,sun50i-a100-mmc"; 312 reg = <0x04020000 0x1000>; 313 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 314 clock-names = "ahb", "mmc"; 315 resets = <&ccu RST_BUS_MMC0>; 316 reset-names = "ahb"; 317 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&mmc0_pins>; 320 status = "disabled"; 321 max-frequency = <150000000>; 322 cap-sd-highspeed; 323 cap-mmc-highspeed; 324 mmc-ddr-3_3v; 325 cap-sdio-irq; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 }; 329 330 mmc1: mmc@4021000 { 331 compatible = "allwinner,sun50i-h616-mmc", 332 "allwinner,sun50i-a100-mmc"; 333 reg = <0x04021000 0x1000>; 334 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 335 clock-names = "ahb", "mmc"; 336 resets = <&ccu RST_BUS_MMC1>; 337 reset-names = "ahb"; 338 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&mmc1_pins>; 341 status = "disabled"; 342 max-frequency = <150000000>; 343 cap-sd-highspeed; 344 cap-mmc-highspeed; 345 mmc-ddr-3_3v; 346 cap-sdio-irq; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 }; 350 351 mmc2: mmc@4022000 { 352 compatible = "allwinner,sun50i-h616-emmc", 353 "allwinner,sun50i-a100-emmc"; 354 reg = <0x04022000 0x1000>; 355 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 356 clock-names = "ahb", "mmc"; 357 resets = <&ccu RST_BUS_MMC2>; 358 reset-names = "ahb"; 359 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 360 pinctrl-names = "default"; 361 pinctrl-0 = <&mmc2_pins>; 362 status = "disabled"; 363 max-frequency = <150000000>; 364 cap-sd-highspeed; 365 cap-mmc-highspeed; 366 mmc-ddr-3_3v; 367 cap-sdio-irq; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 }; 371 372 uart0: serial@5000000 { 373 compatible = "snps,dw-apb-uart"; 374 reg = <0x05000000 0x400>; 375 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 376 reg-shift = <2>; 377 reg-io-width = <4>; 378 clocks = <&ccu CLK_BUS_UART0>; 379 dmas = <&dma 14>, <&dma 14>; 380 dma-names = "tx", "rx"; 381 resets = <&ccu RST_BUS_UART0>; 382 status = "disabled"; 383 }; 384 385 uart1: serial@5000400 { 386 compatible = "snps,dw-apb-uart"; 387 reg = <0x05000400 0x400>; 388 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 389 reg-shift = <2>; 390 reg-io-width = <4>; 391 clocks = <&ccu CLK_BUS_UART1>; 392 dmas = <&dma 15>, <&dma 15>; 393 dma-names = "tx", "rx"; 394 resets = <&ccu RST_BUS_UART1>; 395 status = "disabled"; 396 }; 397 398 uart2: serial@5000800 { 399 compatible = "snps,dw-apb-uart"; 400 reg = <0x05000800 0x400>; 401 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 402 reg-shift = <2>; 403 reg-io-width = <4>; 404 clocks = <&ccu CLK_BUS_UART2>; 405 dmas = <&dma 16>, <&dma 16>; 406 dma-names = "tx", "rx"; 407 resets = <&ccu RST_BUS_UART2>; 408 status = "disabled"; 409 }; 410 411 uart3: serial@5000c00 { 412 compatible = "snps,dw-apb-uart"; 413 reg = <0x05000c00 0x400>; 414 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 415 reg-shift = <2>; 416 reg-io-width = <4>; 417 clocks = <&ccu CLK_BUS_UART3>; 418 dmas = <&dma 17>, <&dma 17>; 419 dma-names = "tx", "rx"; 420 resets = <&ccu RST_BUS_UART3>; 421 status = "disabled"; 422 }; 423 424 uart4: serial@5001000 { 425 compatible = "snps,dw-apb-uart"; 426 reg = <0x05001000 0x400>; 427 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 428 reg-shift = <2>; 429 reg-io-width = <4>; 430 clocks = <&ccu CLK_BUS_UART4>; 431 dmas = <&dma 18>, <&dma 18>; 432 dma-names = "tx", "rx"; 433 resets = <&ccu RST_BUS_UART4>; 434 status = "disabled"; 435 }; 436 437 uart5: serial@5001400 { 438 compatible = "snps,dw-apb-uart"; 439 reg = <0x05001400 0x400>; 440 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 441 reg-shift = <2>; 442 reg-io-width = <4>; 443 clocks = <&ccu CLK_BUS_UART5>; 444 dmas = <&dma 19>, <&dma 19>; 445 dma-names = "tx", "rx"; 446 resets = <&ccu RST_BUS_UART5>; 447 status = "disabled"; 448 }; 449 450 i2c0: i2c@5002000 { 451 compatible = "allwinner,sun50i-h616-i2c", 452 "allwinner,sun8i-v536-i2c", 453 "allwinner,sun6i-a31-i2c"; 454 reg = <0x05002000 0x400>; 455 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&ccu CLK_BUS_I2C0>; 457 dmas = <&dma 43>, <&dma 43>; 458 dma-names = "rx", "tx"; 459 resets = <&ccu RST_BUS_I2C0>; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&i2c0_pins>; 462 status = "disabled"; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 }; 466 467 i2c1: i2c@5002400 { 468 compatible = "allwinner,sun50i-h616-i2c", 469 "allwinner,sun8i-v536-i2c", 470 "allwinner,sun6i-a31-i2c"; 471 reg = <0x05002400 0x400>; 472 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&ccu CLK_BUS_I2C1>; 474 dmas = <&dma 44>, <&dma 44>; 475 dma-names = "rx", "tx"; 476 resets = <&ccu RST_BUS_I2C1>; 477 status = "disabled"; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 }; 481 482 i2c2: i2c@5002800 { 483 compatible = "allwinner,sun50i-h616-i2c", 484 "allwinner,sun8i-v536-i2c", 485 "allwinner,sun6i-a31-i2c"; 486 reg = <0x05002800 0x400>; 487 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&ccu CLK_BUS_I2C2>; 489 dmas = <&dma 45>, <&dma 45>; 490 dma-names = "rx", "tx"; 491 resets = <&ccu RST_BUS_I2C2>; 492 status = "disabled"; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 }; 496 497 i2c3: i2c@5002c00 { 498 compatible = "allwinner,sun50i-h616-i2c", 499 "allwinner,sun8i-v536-i2c", 500 "allwinner,sun6i-a31-i2c"; 501 reg = <0x05002c00 0x400>; 502 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 503 clocks = <&ccu CLK_BUS_I2C3>; 504 dmas = <&dma 46>, <&dma 46>; 505 dma-names = "rx", "tx"; 506 resets = <&ccu RST_BUS_I2C3>; 507 status = "disabled"; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 }; 511 512 i2c4: i2c@5003000 { 513 compatible = "allwinner,sun50i-h616-i2c", 514 "allwinner,sun8i-v536-i2c", 515 "allwinner,sun6i-a31-i2c"; 516 reg = <0x05003000 0x400>; 517 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&ccu CLK_BUS_I2C4>; 519 dmas = <&dma 47>, <&dma 47>; 520 dma-names = "rx", "tx"; 521 resets = <&ccu RST_BUS_I2C4>; 522 status = "disabled"; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 }; 526 527 spi0: spi@5010000 { 528 compatible = "allwinner,sun50i-h616-spi", 529 "allwinner,sun8i-h3-spi"; 530 reg = <0x05010000 0x1000>; 531 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 533 clock-names = "ahb", "mod"; 534 dmas = <&dma 22>, <&dma 22>; 535 dma-names = "rx", "tx"; 536 resets = <&ccu RST_BUS_SPI0>; 537 status = "disabled"; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 }; 541 542 spi1: spi@5011000 { 543 compatible = "allwinner,sun50i-h616-spi", 544 "allwinner,sun8i-h3-spi"; 545 reg = <0x05011000 0x1000>; 546 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 548 clock-names = "ahb", "mod"; 549 dmas = <&dma 23>, <&dma 23>; 550 dma-names = "rx", "tx"; 551 resets = <&ccu RST_BUS_SPI1>; 552 status = "disabled"; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 }; 556 557 emac0: ethernet@5020000 { 558 compatible = "allwinner,sun50i-h616-emac0", 559 "allwinner,sun50i-a64-emac"; 560 reg = <0x05020000 0x10000>; 561 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 562 interrupt-names = "macirq"; 563 clocks = <&ccu CLK_BUS_EMAC0>; 564 clock-names = "stmmaceth"; 565 resets = <&ccu RST_BUS_EMAC0>; 566 reset-names = "stmmaceth"; 567 syscon = <&syscon>; 568 status = "disabled"; 569 570 mdio0: mdio { 571 compatible = "snps,dwmac-mdio"; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 }; 575 }; 576 577 spdif: spdif@5093000 { 578 compatible = "allwinner,sun50i-h616-spdif"; 579 reg = <0x05093000 0x400>; 580 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 582 clock-names = "apb", "spdif"; 583 resets = <&ccu RST_BUS_SPDIF>; 584 dmas = <&dma 2>; 585 dma-names = "tx"; 586 pinctrl-names = "default"; 587 pinctrl-0 = <&spdif_tx_pin>; 588 #sound-dai-cells = <0>; 589 status = "disabled"; 590 }; 591 592 ths: thermal-sensor@5070400 { 593 compatible = "allwinner,sun50i-h616-ths"; 594 reg = <0x05070400 0x400>; 595 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&ccu CLK_BUS_THS>; 597 clock-names = "bus"; 598 resets = <&ccu RST_BUS_THS>; 599 nvmem-cells = <&ths_calibration>; 600 nvmem-cell-names = "calibration"; 601 allwinner,sram = <&syscon>; 602 #thermal-sensor-cells = <1>; 603 }; 604 605 usbotg: usb@5100000 { 606 compatible = "allwinner,sun50i-h616-musb", 607 "allwinner,sun8i-h3-musb"; 608 reg = <0x05100000 0x0400>; 609 clocks = <&ccu CLK_BUS_OTG>; 610 resets = <&ccu RST_BUS_OTG>; 611 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 612 interrupt-names = "mc"; 613 phys = <&usbphy 0>; 614 phy-names = "usb"; 615 extcon = <&usbphy 0>; 616 status = "disabled"; 617 }; 618 619 usbphy: phy@5100400 { 620 compatible = "allwinner,sun50i-h616-usb-phy"; 621 reg = <0x05100400 0x24>, 622 <0x05101800 0x14>, 623 <0x05200800 0x14>, 624 <0x05310800 0x14>, 625 <0x05311800 0x14>; 626 reg-names = "phy_ctrl", 627 "pmu0", 628 "pmu1", 629 "pmu2", 630 "pmu3"; 631 clocks = <&ccu CLK_USB_PHY0>, 632 <&ccu CLK_USB_PHY1>, 633 <&ccu CLK_USB_PHY2>, 634 <&ccu CLK_USB_PHY3>, 635 <&ccu CLK_BUS_EHCI2>; 636 clock-names = "usb0_phy", 637 "usb1_phy", 638 "usb2_phy", 639 "usb3_phy", 640 "pmu2_clk"; 641 resets = <&ccu RST_USB_PHY0>, 642 <&ccu RST_USB_PHY1>, 643 <&ccu RST_USB_PHY2>, 644 <&ccu RST_USB_PHY3>; 645 reset-names = "usb0_reset", 646 "usb1_reset", 647 "usb2_reset", 648 "usb3_reset"; 649 status = "disabled"; 650 #phy-cells = <1>; 651 }; 652 653 ehci0: usb@5101000 { 654 compatible = "allwinner,sun50i-h616-ehci", 655 "generic-ehci"; 656 reg = <0x05101000 0x100>; 657 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&ccu CLK_BUS_OHCI0>, 659 <&ccu CLK_BUS_EHCI0>, 660 <&ccu CLK_USB_OHCI0>; 661 resets = <&ccu RST_BUS_OHCI0>, 662 <&ccu RST_BUS_EHCI0>; 663 phys = <&usbphy 0>; 664 phy-names = "usb"; 665 status = "disabled"; 666 }; 667 668 ohci0: usb@5101400 { 669 compatible = "allwinner,sun50i-h616-ohci", 670 "generic-ohci"; 671 reg = <0x05101400 0x100>; 672 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&ccu CLK_BUS_OHCI0>, 674 <&ccu CLK_USB_OHCI0>; 675 resets = <&ccu RST_BUS_OHCI0>; 676 phys = <&usbphy 0>; 677 phy-names = "usb"; 678 status = "disabled"; 679 }; 680 681 ehci1: usb@5200000 { 682 compatible = "allwinner,sun50i-h616-ehci", 683 "generic-ehci"; 684 reg = <0x05200000 0x100>; 685 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&ccu CLK_BUS_OHCI1>, 687 <&ccu CLK_BUS_EHCI1>, 688 <&ccu CLK_USB_OHCI1>; 689 resets = <&ccu RST_BUS_OHCI1>, 690 <&ccu RST_BUS_EHCI1>; 691 phys = <&usbphy 1>; 692 phy-names = "usb"; 693 status = "disabled"; 694 }; 695 696 ohci1: usb@5200400 { 697 compatible = "allwinner,sun50i-h616-ohci", 698 "generic-ohci"; 699 reg = <0x05200400 0x100>; 700 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 701 clocks = <&ccu CLK_BUS_OHCI1>, 702 <&ccu CLK_USB_OHCI1>; 703 resets = <&ccu RST_BUS_OHCI1>; 704 phys = <&usbphy 1>; 705 phy-names = "usb"; 706 status = "disabled"; 707 }; 708 709 ehci2: usb@5310000 { 710 compatible = "allwinner,sun50i-h616-ehci", 711 "generic-ehci"; 712 reg = <0x05310000 0x100>; 713 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&ccu CLK_BUS_OHCI2>, 715 <&ccu CLK_BUS_EHCI2>, 716 <&ccu CLK_USB_OHCI2>; 717 resets = <&ccu RST_BUS_OHCI2>, 718 <&ccu RST_BUS_EHCI2>; 719 phys = <&usbphy 2>; 720 phy-names = "usb"; 721 status = "disabled"; 722 }; 723 724 ohci2: usb@5310400 { 725 compatible = "allwinner,sun50i-h616-ohci", 726 "generic-ohci"; 727 reg = <0x05310400 0x100>; 728 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&ccu CLK_BUS_OHCI2>, 730 <&ccu CLK_USB_OHCI2>; 731 resets = <&ccu RST_BUS_OHCI2>; 732 phys = <&usbphy 2>; 733 phy-names = "usb"; 734 status = "disabled"; 735 }; 736 737 ehci3: usb@5311000 { 738 compatible = "allwinner,sun50i-h616-ehci", 739 "generic-ehci"; 740 reg = <0x05311000 0x100>; 741 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&ccu CLK_BUS_OHCI3>, 743 <&ccu CLK_BUS_EHCI3>, 744 <&ccu CLK_USB_OHCI3>; 745 resets = <&ccu RST_BUS_OHCI3>, 746 <&ccu RST_BUS_EHCI3>; 747 phys = <&usbphy 3>; 748 phy-names = "usb"; 749 status = "disabled"; 750 }; 751 752 ohci3: usb@5311400 { 753 compatible = "allwinner,sun50i-h616-ohci", 754 "generic-ohci"; 755 reg = <0x05311400 0x100>; 756 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&ccu CLK_BUS_OHCI3>, 758 <&ccu CLK_USB_OHCI3>; 759 resets = <&ccu RST_BUS_OHCI3>; 760 phys = <&usbphy 3>; 761 phy-names = "usb"; 762 status = "disabled"; 763 }; 764 765 rtc: rtc@7000000 { 766 compatible = "allwinner,sun50i-h616-rtc"; 767 reg = <0x07000000 0x400>; 768 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&r_ccu CLK_R_APB1_RTC>, <&osc24M>, 770 <&ccu CLK_PLL_SYSTEM_32K>; 771 clock-names = "bus", "hosc", 772 "pll-32k"; 773 #clock-cells = <1>; 774 }; 775 776 r_ccu: clock@7010000 { 777 compatible = "allwinner,sun50i-h616-r-ccu"; 778 reg = <0x07010000 0x210>; 779 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 780 <&ccu CLK_PLL_PERIPH0>; 781 clock-names = "hosc", "losc", "iosc", "pll-periph"; 782 #clock-cells = <1>; 783 #reset-cells = <1>; 784 }; 785 786 nmi_intc: interrupt-controller@7010320 { 787 compatible = "allwinner,sun50i-h616-nmi", 788 "allwinner,sun9i-a80-nmi"; 789 reg = <0x07010320 0xc>; 790 interrupt-controller; 791 #interrupt-cells = <2>; 792 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 793 }; 794 795 r_pio: pinctrl@7022000 { 796 compatible = "allwinner,sun50i-h616-r-pinctrl"; 797 reg = <0x07022000 0x400>; 798 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, 799 <&rtc CLK_OSC32K>; 800 clock-names = "apb", "hosc", "losc"; 801 gpio-controller; 802 #gpio-cells = <3>; 803 804 /omit-if-no-ref/ 805 r_i2c_pins: r-i2c-pins { 806 pins = "PL0", "PL1"; 807 function = "s_i2c"; 808 }; 809 810 r_rsb_pins: r-rsb-pins { 811 pins = "PL0", "PL1"; 812 function = "s_rsb"; 813 }; 814 }; 815 816 ir: ir@7040000 { 817 compatible = "allwinner,sun50i-h616-ir", 818 "allwinner,sun6i-a31-ir"; 819 reg = <0x07040000 0x400>; 820 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 821 clocks = <&r_ccu CLK_R_APB1_IR>, 822 <&r_ccu CLK_IR>; 823 clock-names = "apb", "ir"; 824 resets = <&r_ccu RST_R_APB1_IR>; 825 pinctrl-names = "default"; 826 pinctrl-0 = <&ir_rx_pin>; 827 status = "disabled"; 828 }; 829 830 r_i2c: i2c@7081400 { 831 compatible = "allwinner,sun50i-h616-i2c", 832 "allwinner,sun8i-v536-i2c", 833 "allwinner,sun6i-a31-i2c"; 834 reg = <0x07081400 0x400>; 835 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&r_ccu CLK_R_APB2_I2C>; 837 dmas = <&dma 48>, <&dma 48>; 838 dma-names = "rx", "tx"; 839 resets = <&r_ccu RST_R_APB2_I2C>; 840 status = "disabled"; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 }; 844 845 r_rsb: rsb@7083000 { 846 compatible = "allwinner,sun50i-h616-rsb", 847 "allwinner,sun8i-a23-rsb"; 848 reg = <0x07083000 0x400>; 849 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&r_ccu CLK_R_APB2_RSB>; 851 clock-frequency = <3000000>; 852 resets = <&r_ccu RST_R_APB2_RSB>; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&r_rsb_pins>; 855 status = "disabled"; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 }; 859 }; 860 861 thermal-zones { 862 cpu-thermal { 863 polling-delay-passive = <500>; 864 polling-delay = <1000>; 865 thermal-sensors = <&ths 2>; 866 sustainable-power = <1000>; 867 868 trips { 869 cpu_threshold: cpu-trip-0 { 870 temperature = <60000>; 871 type = "passive"; 872 hysteresis = <0>; 873 }; 874 cpu_target: cpu-trip-1 { 875 temperature = <70000>; 876 type = "passive"; 877 hysteresis = <0>; 878 }; 879 cpu_critical: cpu-trip-2 { 880 temperature = <110000>; 881 type = "critical"; 882 hysteresis = <0>; 883 }; 884 }; 885 }; 886 887 gpu-thermal { 888 polling-delay-passive = <500>; 889 polling-delay = <1000>; 890 thermal-sensors = <&ths 0>; 891 sustainable-power = <1100>; 892 893 trips { 894 gpu_temp_critical: gpu-trip-0 { 895 temperature = <110000>; 896 type = "critical"; 897 hysteresis = <0>; 898 }; 899 }; 900 }; 901 902 ve-thermal { 903 polling-delay-passive = <0>; 904 polling-delay = <0>; 905 thermal-sensors = <&ths 1>; 906 907 trips { 908 ve_temp_critical: ve-trip-0 { 909 temperature = <110000>; 910 type = "critical"; 911 hysteresis = <0>; 912 }; 913 }; 914 }; 915 916 ddr-thermal { 917 polling-delay-passive = <0>; 918 polling-delay = <0>; 919 thermal-sensors = <&ths 3>; 920 921 trips { 922 ddr_temp_critical: ddr-trip-0 { 923 temperature = <110000>; 924 type = "critical"; 925 hysteresis = <0>; 926 }; 927 }; 928 }; 929 }; 930}; 931