1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2016 ARM Ltd. 3// based on the Allwinner H3 dtsi: 4// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 6#include <dt-bindings/clock/sun50i-a64-ccu.h> 7#include <dt-bindings/clock/sun6i-rtc.h> 8#include <dt-bindings/clock/sun8i-de2.h> 9#include <dt-bindings/clock/sun8i-r-ccu.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/sun50i-a64-ccu.h> 12#include <dt-bindings/reset/sun8i-de2.h> 13#include <dt-bindings/reset/sun8i-r-ccu.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 chosen { 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges; 25 26 simplefb_lcd: framebuffer-lcd { 27 compatible = "allwinner,simple-framebuffer", 28 "simple-framebuffer"; 29 allwinner,pipeline = "mixer0-lcd0"; 30 clocks = <&ccu CLK_TCON0>, 31 <&display_clocks CLK_MIXER0>; 32 status = "disabled"; 33 }; 34 35 simplefb_hdmi: framebuffer-hdmi { 36 compatible = "allwinner,simple-framebuffer", 37 "simple-framebuffer"; 38 allwinner,pipeline = "mixer1-lcd1-hdmi"; 39 clocks = <&display_clocks CLK_MIXER1>, 40 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 41 status = "disabled"; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 compatible = "arm,cortex-a53"; 51 device_type = "cpu"; 52 reg = <0>; 53 enable-method = "psci"; 54 clocks = <&ccu CLK_CPUX>; 55 clock-names = "cpu"; 56 #cooling-cells = <2>; 57 i-cache-size = <0x8000>; 58 i-cache-line-size = <64>; 59 i-cache-sets = <256>; 60 d-cache-size = <0x8000>; 61 d-cache-line-size = <64>; 62 d-cache-sets = <128>; 63 next-level-cache = <&l2_cache>; 64 }; 65 66 cpu1: cpu@1 { 67 compatible = "arm,cortex-a53"; 68 device_type = "cpu"; 69 reg = <1>; 70 enable-method = "psci"; 71 clocks = <&ccu CLK_CPUX>; 72 clock-names = "cpu"; 73 #cooling-cells = <2>; 74 i-cache-size = <0x8000>; 75 i-cache-line-size = <64>; 76 i-cache-sets = <256>; 77 d-cache-size = <0x8000>; 78 d-cache-line-size = <64>; 79 d-cache-sets = <128>; 80 next-level-cache = <&l2_cache>; 81 }; 82 83 cpu2: cpu@2 { 84 compatible = "arm,cortex-a53"; 85 device_type = "cpu"; 86 reg = <2>; 87 enable-method = "psci"; 88 clocks = <&ccu CLK_CPUX>; 89 clock-names = "cpu"; 90 #cooling-cells = <2>; 91 i-cache-size = <0x8000>; 92 i-cache-line-size = <64>; 93 i-cache-sets = <256>; 94 d-cache-size = <0x8000>; 95 d-cache-line-size = <64>; 96 d-cache-sets = <128>; 97 next-level-cache = <&l2_cache>; 98 }; 99 100 cpu3: cpu@3 { 101 compatible = "arm,cortex-a53"; 102 device_type = "cpu"; 103 reg = <3>; 104 enable-method = "psci"; 105 clocks = <&ccu CLK_CPUX>; 106 clock-names = "cpu"; 107 #cooling-cells = <2>; 108 i-cache-size = <0x8000>; 109 i-cache-line-size = <64>; 110 i-cache-sets = <256>; 111 d-cache-size = <0x8000>; 112 d-cache-line-size = <64>; 113 d-cache-sets = <128>; 114 next-level-cache = <&l2_cache>; 115 }; 116 117 l2_cache: l2-cache { 118 compatible = "cache"; 119 cache-level = <2>; 120 cache-unified; 121 cache-size = <0x80000>; 122 cache-line-size = <64>; 123 cache-sets = <512>; 124 }; 125 }; 126 127 de: display-engine { 128 compatible = "allwinner,sun50i-a64-display-engine"; 129 allwinner,pipelines = <&mixer0>, 130 <&mixer1>; 131 status = "disabled"; 132 }; 133 134 gpu_opp_table: opp-table-gpu { 135 compatible = "operating-points-v2"; 136 137 opp-432000000 { 138 opp-hz = /bits/ 64 <432000000>; 139 }; 140 }; 141 142 osc24M: osc24M-clk { 143 #clock-cells = <0>; 144 compatible = "fixed-clock"; 145 clock-frequency = <24000000>; 146 clock-output-names = "osc24M"; 147 }; 148 149 osc32k: osc32k-clk { 150 #clock-cells = <0>; 151 compatible = "fixed-clock"; 152 clock-frequency = <32768>; 153 clock-output-names = "ext-osc32k"; 154 }; 155 156 pmu { 157 compatible = "arm,cortex-a53-pmu"; 158 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 162 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 163 }; 164 165 psci { 166 compatible = "arm,psci-0.2"; 167 method = "smc"; 168 }; 169 170 sound: sound { 171 #address-cells = <1>; 172 #size-cells = <0>; 173 compatible = "simple-audio-card"; 174 simple-audio-card,name = "sun50i-a64-audio"; 175 simple-audio-card,aux-devs = <&codec_analog>; 176 simple-audio-card,routing = 177 "Left DAC", "DACL", 178 "Right DAC", "DACR", 179 "ADCL", "Left ADC", 180 "ADCR", "Right ADC"; 181 status = "disabled"; 182 183 simple-audio-card,dai-link@0 { 184 format = "i2s"; 185 frame-master = <&link0_cpu>; 186 bitclock-master = <&link0_cpu>; 187 mclk-fs = <128>; 188 189 link0_cpu: cpu { 190 sound-dai = <&dai>; 191 }; 192 193 link0_codec: codec { 194 sound-dai = <&codec 0>; 195 }; 196 }; 197 }; 198 199 timer { 200 compatible = "arm,armv8-timer"; 201 allwinner,erratum-unknown1; 202 arm,no-tick-in-suspend; 203 interrupts = <GIC_PPI 13 204 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 205 <GIC_PPI 14 206 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 207 <GIC_PPI 11 208 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 209 <GIC_PPI 10 210 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 211 }; 212 213 thermal-zones { 214 cpu_thermal: cpu0-thermal { 215 /* milliseconds */ 216 polling-delay-passive = <0>; 217 polling-delay = <0>; 218 thermal-sensors = <&ths 0>; 219 220 cooling-maps { 221 map0 { 222 trip = <&cpu_alert0>; 223 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 224 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 225 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 226 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 227 }; 228 map1 { 229 trip = <&cpu_alert1>; 230 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 231 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 232 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 233 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 234 }; 235 }; 236 237 trips { 238 cpu_alert0: cpu-alert0 { 239 /* milliCelsius */ 240 temperature = <75000>; 241 hysteresis = <2000>; 242 type = "passive"; 243 }; 244 245 cpu_alert1: cpu-alert1 { 246 /* milliCelsius */ 247 temperature = <90000>; 248 hysteresis = <2000>; 249 type = "hot"; 250 }; 251 252 cpu_crit: cpu-crit { 253 /* milliCelsius */ 254 temperature = <110000>; 255 hysteresis = <2000>; 256 type = "critical"; 257 }; 258 }; 259 }; 260 261 gpu0_thermal: gpu0-thermal { 262 /* milliseconds */ 263 polling-delay-passive = <0>; 264 polling-delay = <0>; 265 thermal-sensors = <&ths 1>; 266 }; 267 268 gpu1_thermal: gpu1-thermal { 269 /* milliseconds */ 270 polling-delay-passive = <0>; 271 polling-delay = <0>; 272 thermal-sensors = <&ths 2>; 273 }; 274 }; 275 276 soc { 277 compatible = "simple-bus"; 278 #address-cells = <1>; 279 #size-cells = <1>; 280 ranges; 281 282 bus@1000000 { 283 compatible = "allwinner,sun50i-a64-de2"; 284 reg = <0x1000000 0x400000>; 285 allwinner,sram = <&de2_sram 1>; 286 #address-cells = <1>; 287 #size-cells = <1>; 288 ranges = <0 0x1000000 0x400000>; 289 290 display_clocks: clock@0 { 291 compatible = "allwinner,sun50i-a64-de2-clk"; 292 reg = <0x0 0x10000>; 293 clocks = <&ccu CLK_BUS_DE>, 294 <&ccu CLK_DE>; 295 clock-names = "bus", 296 "mod"; 297 resets = <&ccu RST_BUS_DE>; 298 #clock-cells = <1>; 299 #reset-cells = <1>; 300 }; 301 302 rotate: rotate@20000 { 303 compatible = "allwinner,sun50i-a64-de2-rotate", 304 "allwinner,sun8i-a83t-de2-rotate"; 305 reg = <0x20000 0x10000>; 306 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&display_clocks CLK_BUS_ROT>, 308 <&display_clocks CLK_ROT>; 309 clock-names = "bus", 310 "mod"; 311 resets = <&display_clocks RST_ROT>; 312 }; 313 314 mixer0: mixer@100000 { 315 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 316 reg = <0x100000 0x100000>; 317 clocks = <&display_clocks CLK_BUS_MIXER0>, 318 <&display_clocks CLK_MIXER0>; 319 clock-names = "bus", 320 "mod"; 321 resets = <&display_clocks RST_MIXER0>; 322 323 ports { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 327 mixer0_out: port@1 { 328 #address-cells = <1>; 329 #size-cells = <0>; 330 reg = <1>; 331 332 mixer0_out_tcon0: endpoint@0 { 333 reg = <0>; 334 remote-endpoint = <&tcon0_in_mixer0>; 335 }; 336 337 mixer0_out_tcon1: endpoint@1 { 338 reg = <1>; 339 remote-endpoint = <&tcon1_in_mixer0>; 340 }; 341 }; 342 }; 343 }; 344 345 mixer1: mixer@200000 { 346 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 347 reg = <0x200000 0x100000>; 348 clocks = <&display_clocks CLK_BUS_MIXER1>, 349 <&display_clocks CLK_MIXER1>; 350 clock-names = "bus", 351 "mod"; 352 resets = <&display_clocks RST_MIXER1>; 353 354 ports { 355 #address-cells = <1>; 356 #size-cells = <0>; 357 358 mixer1_out: port@1 { 359 #address-cells = <1>; 360 #size-cells = <0>; 361 reg = <1>; 362 363 mixer1_out_tcon0: endpoint@0 { 364 reg = <0>; 365 remote-endpoint = <&tcon0_in_mixer1>; 366 }; 367 368 mixer1_out_tcon1: endpoint@1 { 369 reg = <1>; 370 remote-endpoint = <&tcon1_in_mixer1>; 371 }; 372 }; 373 }; 374 }; 375 }; 376 377 syscon: syscon@1c00000 { 378 compatible = "allwinner,sun50i-a64-system-control"; 379 reg = <0x01c00000 0x1000>; 380 #address-cells = <1>; 381 #size-cells = <1>; 382 ranges; 383 384 sram_c: sram@18000 { 385 compatible = "mmio-sram"; 386 reg = <0x00018000 0x28000>; 387 #address-cells = <1>; 388 #size-cells = <1>; 389 ranges = <0 0x00018000 0x28000>; 390 391 de2_sram: sram-section@0 { 392 compatible = "allwinner,sun50i-a64-sram-c"; 393 reg = <0x0000 0x28000>; 394 }; 395 }; 396 397 sram_c1: sram@1d00000 { 398 compatible = "mmio-sram"; 399 reg = <0x01d00000 0x40000>; 400 #address-cells = <1>; 401 #size-cells = <1>; 402 ranges = <0 0x01d00000 0x40000>; 403 404 ve_sram: sram-section@0 { 405 compatible = "allwinner,sun50i-a64-sram-c1", 406 "allwinner,sun4i-a10-sram-c1"; 407 reg = <0x000000 0x40000>; 408 }; 409 }; 410 }; 411 412 dma: dma-controller@1c02000 { 413 compatible = "allwinner,sun50i-a64-dma"; 414 reg = <0x01c02000 0x1000>; 415 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&ccu CLK_BUS_DMA>; 417 dma-channels = <8>; 418 dma-requests = <27>; 419 resets = <&ccu RST_BUS_DMA>; 420 #dma-cells = <1>; 421 }; 422 423 tcon0: lcd-controller@1c0c000 { 424 compatible = "allwinner,sun50i-a64-tcon-lcd", 425 "allwinner,sun8i-a83t-tcon-lcd"; 426 reg = <0x01c0c000 0x1000>; 427 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 429 clock-names = "ahb", "tcon-ch0"; 430 clock-output-names = "tcon-data-clock"; 431 #clock-cells = <0>; 432 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 433 reset-names = "lcd", "lvds"; 434 435 ports { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 439 tcon0_in: port@0 { 440 #address-cells = <1>; 441 #size-cells = <0>; 442 reg = <0>; 443 444 tcon0_in_mixer0: endpoint@0 { 445 reg = <0>; 446 remote-endpoint = <&mixer0_out_tcon0>; 447 }; 448 449 tcon0_in_mixer1: endpoint@1 { 450 reg = <1>; 451 remote-endpoint = <&mixer1_out_tcon0>; 452 }; 453 }; 454 455 tcon0_out: port@1 { 456 #address-cells = <1>; 457 #size-cells = <0>; 458 reg = <1>; 459 460 tcon0_out_dsi: endpoint@1 { 461 reg = <1>; 462 remote-endpoint = <&dsi_in_tcon0>; 463 allwinner,tcon-channel = <1>; 464 }; 465 }; 466 }; 467 }; 468 469 tcon1: lcd-controller@1c0d000 { 470 compatible = "allwinner,sun50i-a64-tcon-tv", 471 "allwinner,sun8i-a83t-tcon-tv"; 472 reg = <0x01c0d000 0x1000>; 473 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 474 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 475 clock-names = "ahb", "tcon-ch1"; 476 resets = <&ccu RST_BUS_TCON1>; 477 reset-names = "lcd"; 478 479 ports { 480 #address-cells = <1>; 481 #size-cells = <0>; 482 483 tcon1_in: port@0 { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 reg = <0>; 487 488 tcon1_in_mixer0: endpoint@0 { 489 reg = <0>; 490 remote-endpoint = <&mixer0_out_tcon1>; 491 }; 492 493 tcon1_in_mixer1: endpoint@1 { 494 reg = <1>; 495 remote-endpoint = <&mixer1_out_tcon1>; 496 }; 497 }; 498 499 tcon1_out: port@1 { 500 #address-cells = <1>; 501 #size-cells = <0>; 502 reg = <1>; 503 504 tcon1_out_hdmi: endpoint@1 { 505 reg = <1>; 506 remote-endpoint = <&hdmi_in_tcon1>; 507 }; 508 }; 509 }; 510 }; 511 512 video-codec@1c0e000 { 513 compatible = "allwinner,sun50i-a64-video-engine"; 514 reg = <0x01c0e000 0x1000>; 515 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 516 <&ccu CLK_DRAM_VE>; 517 clock-names = "ahb", "mod", "ram"; 518 resets = <&ccu RST_BUS_VE>; 519 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 520 allwinner,sram = <&ve_sram 1>; 521 }; 522 523 mmc0: mmc@1c0f000 { 524 compatible = "allwinner,sun50i-a64-mmc"; 525 reg = <0x01c0f000 0x1000>; 526 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 527 clock-names = "ahb", "mmc"; 528 resets = <&ccu RST_BUS_MMC0>; 529 reset-names = "ahb"; 530 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 531 max-frequency = <150000000>; 532 status = "disabled"; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 }; 536 537 mmc1: mmc@1c10000 { 538 compatible = "allwinner,sun50i-a64-mmc"; 539 reg = <0x01c10000 0x1000>; 540 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 541 clock-names = "ahb", "mmc"; 542 resets = <&ccu RST_BUS_MMC1>; 543 reset-names = "ahb"; 544 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 545 max-frequency = <150000000>; 546 status = "disabled"; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 }; 550 551 mmc2: mmc@1c11000 { 552 compatible = "allwinner,sun50i-a64-emmc"; 553 reg = <0x01c11000 0x1000>; 554 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 555 clock-names = "ahb", "mmc"; 556 resets = <&ccu RST_BUS_MMC2>; 557 reset-names = "ahb"; 558 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 559 max-frequency = <150000000>; 560 status = "disabled"; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 }; 564 565 sid: eeprom@1c14000 { 566 compatible = "allwinner,sun50i-a64-sid"; 567 reg = <0x1c14000 0x400>; 568 #address-cells = <1>; 569 #size-cells = <1>; 570 571 ths_calibration: thermal-sensor-calibration@34 { 572 reg = <0x34 0x8>; 573 }; 574 }; 575 576 crypto: crypto@1c15000 { 577 compatible = "allwinner,sun50i-a64-crypto"; 578 reg = <0x01c15000 0x1000>; 579 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 581 clock-names = "bus", "mod"; 582 resets = <&ccu RST_BUS_CE>; 583 }; 584 585 msgbox: mailbox@1c17000 { 586 compatible = "allwinner,sun50i-a64-msgbox", 587 "allwinner,sun6i-a31-msgbox"; 588 reg = <0x01c17000 0x1000>; 589 clocks = <&ccu CLK_BUS_MSGBOX>; 590 resets = <&ccu RST_BUS_MSGBOX>; 591 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 592 #mbox-cells = <1>; 593 }; 594 595 usb_otg: usb@1c19000 { 596 compatible = "allwinner,sun8i-a33-musb"; 597 reg = <0x01c19000 0x0400>; 598 clocks = <&ccu CLK_BUS_OTG>; 599 resets = <&ccu RST_BUS_OTG>; 600 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 601 interrupt-names = "mc"; 602 phys = <&usbphy 0>; 603 phy-names = "usb"; 604 extcon = <&usbphy 0>; 605 dr_mode = "otg"; 606 status = "disabled"; 607 }; 608 609 usbphy: phy@1c19400 { 610 compatible = "allwinner,sun50i-a64-usb-phy"; 611 reg = <0x01c19400 0x14>, 612 <0x01c1a800 0x4>, 613 <0x01c1b800 0x4>; 614 reg-names = "phy_ctrl", 615 "pmu0", 616 "pmu1"; 617 clocks = <&ccu CLK_USB_PHY0>, 618 <&ccu CLK_USB_PHY1>; 619 clock-names = "usb0_phy", 620 "usb1_phy"; 621 resets = <&ccu RST_USB_PHY0>, 622 <&ccu RST_USB_PHY1>; 623 reset-names = "usb0_reset", 624 "usb1_reset"; 625 status = "disabled"; 626 #phy-cells = <1>; 627 }; 628 629 ehci0: usb@1c1a000 { 630 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 631 reg = <0x01c1a000 0x100>; 632 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&ccu CLK_BUS_OHCI0>, 634 <&ccu CLK_BUS_EHCI0>, 635 <&ccu CLK_USB_OHCI0>; 636 resets = <&ccu RST_BUS_OHCI0>, 637 <&ccu RST_BUS_EHCI0>; 638 phys = <&usbphy 0>; 639 phy-names = "usb"; 640 status = "disabled"; 641 }; 642 643 ohci0: usb@1c1a400 { 644 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 645 reg = <0x01c1a400 0x100>; 646 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&ccu CLK_BUS_OHCI0>, 648 <&ccu CLK_USB_OHCI0>; 649 resets = <&ccu RST_BUS_OHCI0>; 650 phys = <&usbphy 0>; 651 phy-names = "usb"; 652 status = "disabled"; 653 }; 654 655 ehci1: usb@1c1b000 { 656 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 657 reg = <0x01c1b000 0x100>; 658 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&ccu CLK_BUS_OHCI1>, 660 <&ccu CLK_BUS_EHCI1>, 661 <&ccu CLK_USB_OHCI1>; 662 resets = <&ccu RST_BUS_OHCI1>, 663 <&ccu RST_BUS_EHCI1>; 664 phys = <&usbphy 1>; 665 phy-names = "usb"; 666 status = "disabled"; 667 }; 668 669 ohci1: usb@1c1b400 { 670 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 671 reg = <0x01c1b400 0x100>; 672 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 673 clocks = <&ccu CLK_BUS_OHCI1>, 674 <&ccu CLK_USB_OHCI1>; 675 resets = <&ccu RST_BUS_OHCI1>; 676 phys = <&usbphy 1>; 677 phy-names = "usb"; 678 status = "disabled"; 679 }; 680 681 ccu: clock@1c20000 { 682 compatible = "allwinner,sun50i-a64-ccu"; 683 reg = <0x01c20000 0x400>; 684 clocks = <&osc24M>, <&rtc CLK_OSC32K>; 685 clock-names = "hosc", "losc"; 686 #clock-cells = <1>; 687 #reset-cells = <1>; 688 }; 689 690 pio: pinctrl@1c20800 { 691 compatible = "allwinner,sun50i-a64-pinctrl"; 692 reg = <0x01c20800 0x400>; 693 interrupt-parent = <&r_intc>; 694 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, 698 <&rtc CLK_OSC32K>; 699 clock-names = "apb", "hosc", "losc"; 700 gpio-controller; 701 #gpio-cells = <3>; 702 interrupt-controller; 703 #interrupt-cells = <3>; 704 705 /omit-if-no-ref/ 706 aif2_pins: aif2-pins { 707 pins = "PB4", "PB5", "PB6", "PB7"; 708 function = "aif2"; 709 }; 710 711 /omit-if-no-ref/ 712 aif3_pins: aif3-pins { 713 pins = "PG10", "PG11", "PG12", "PG13"; 714 function = "aif3"; 715 }; 716 717 csi_pins: csi-pins { 718 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 719 "PE7", "PE8", "PE9", "PE10", "PE11"; 720 function = "csi"; 721 }; 722 723 /omit-if-no-ref/ 724 csi_mclk_pin: csi-mclk-pin { 725 pins = "PE1"; 726 function = "csi"; 727 }; 728 729 i2c0_pins: i2c0-pins { 730 pins = "PH0", "PH1"; 731 function = "i2c0"; 732 }; 733 734 i2c1_pins: i2c1-pins { 735 pins = "PH2", "PH3"; 736 function = "i2c1"; 737 }; 738 739 i2c2_pins: i2c2-pins { 740 pins = "PE14", "PE15"; 741 function = "i2c2"; 742 }; 743 744 /omit-if-no-ref/ 745 lcd_rgb666_pins: lcd-rgb666-pins { 746 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 747 "PD5", "PD6", "PD7", "PD8", "PD9", 748 "PD10", "PD11", "PD12", "PD13", 749 "PD14", "PD15", "PD16", "PD17", 750 "PD18", "PD19", "PD20", "PD21"; 751 function = "lcd0"; 752 }; 753 754 mmc0_pins: mmc0-pins { 755 pins = "PF0", "PF1", "PF2", "PF3", 756 "PF4", "PF5"; 757 function = "mmc0"; 758 drive-strength = <30>; 759 bias-pull-up; 760 }; 761 762 mmc1_pins: mmc1-pins { 763 pins = "PG0", "PG1", "PG2", "PG3", 764 "PG4", "PG5"; 765 function = "mmc1"; 766 drive-strength = <30>; 767 bias-pull-up; 768 }; 769 770 mmc2_pins: mmc2-pins { 771 pins = "PC5", "PC6", "PC8", "PC9", 772 "PC10","PC11", "PC12", "PC13", 773 "PC14", "PC15", "PC16"; 774 function = "mmc2"; 775 drive-strength = <30>; 776 bias-pull-up; 777 }; 778 779 mmc2_ds_pin: mmc2-ds-pin { 780 pins = "PC1"; 781 function = "mmc2"; 782 drive-strength = <30>; 783 bias-pull-up; 784 }; 785 786 pwm_pin: pwm-pin { 787 pins = "PD22"; 788 function = "pwm"; 789 }; 790 791 rmii_pins: rmii-pins { 792 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 793 "PD18", "PD19", "PD20", "PD22", "PD23"; 794 function = "emac"; 795 drive-strength = <40>; 796 }; 797 798 rgmii_pins: rgmii-pins { 799 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 800 "PD13", "PD15", "PD16", "PD17", "PD18", 801 "PD19", "PD20", "PD21", "PD22", "PD23"; 802 function = "emac"; 803 drive-strength = <40>; 804 }; 805 806 spdif_tx_pin: spdif-tx-pin { 807 pins = "PH8"; 808 function = "spdif"; 809 }; 810 811 spi0_pins: spi0-pins { 812 pins = "PC0", "PC1", "PC2", "PC3"; 813 function = "spi0"; 814 }; 815 816 spi1_pins: spi1-pins { 817 pins = "PD0", "PD1", "PD2", "PD3"; 818 function = "spi1"; 819 }; 820 821 uart0_pb_pins: uart0-pb-pins { 822 pins = "PB8", "PB9"; 823 function = "uart0"; 824 }; 825 826 uart1_pins: uart1-pins { 827 pins = "PG6", "PG7"; 828 function = "uart1"; 829 }; 830 831 uart1_rts_cts_pins: uart1-rts-cts-pins { 832 pins = "PG8", "PG9"; 833 function = "uart1"; 834 }; 835 836 uart2_pins: uart2-pins { 837 pins = "PB0", "PB1"; 838 function = "uart2"; 839 }; 840 841 uart3_pins: uart3-pins { 842 pins = "PD0", "PD1"; 843 function = "uart3"; 844 }; 845 846 uart4_pins: uart4-pins { 847 pins = "PD2", "PD3"; 848 function = "uart4"; 849 }; 850 851 uart4_rts_cts_pins: uart4-rts-cts-pins { 852 pins = "PD4", "PD5"; 853 function = "uart4"; 854 }; 855 }; 856 857 timer@1c20c00 { 858 compatible = "allwinner,sun50i-a64-timer", 859 "allwinner,sun8i-a23-timer"; 860 reg = <0x01c20c00 0xa0>; 861 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&osc24M>; 864 }; 865 866 wdt0: watchdog@1c20ca0 { 867 compatible = "allwinner,sun50i-a64-wdt", 868 "allwinner,sun6i-a31-wdt"; 869 reg = <0x01c20ca0 0x20>; 870 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&osc24M>; 872 }; 873 874 spdif: spdif@1c21000 { 875 #sound-dai-cells = <0>; 876 compatible = "allwinner,sun50i-a64-spdif", 877 "allwinner,sun8i-h3-spdif"; 878 reg = <0x01c21000 0x400>; 879 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 881 resets = <&ccu RST_BUS_SPDIF>; 882 clock-names = "apb", "spdif"; 883 dmas = <&dma 2>; 884 dma-names = "tx"; 885 pinctrl-names = "default"; 886 pinctrl-0 = <&spdif_tx_pin>; 887 status = "disabled"; 888 }; 889 890 lradc: lradc@1c21800 { 891 compatible = "allwinner,sun50i-a64-lradc", 892 "allwinner,sun8i-a83t-r-lradc"; 893 reg = <0x01c21800 0x400>; 894 interrupt-parent = <&r_intc>; 895 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 896 status = "disabled"; 897 }; 898 899 i2s0: i2s@1c22000 { 900 #sound-dai-cells = <0>; 901 compatible = "allwinner,sun50i-a64-i2s", 902 "allwinner,sun8i-h3-i2s"; 903 reg = <0x01c22000 0x400>; 904 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 906 clock-names = "apb", "mod"; 907 resets = <&ccu RST_BUS_I2S0>; 908 dma-names = "rx", "tx"; 909 dmas = <&dma 3>, <&dma 3>; 910 status = "disabled"; 911 }; 912 913 i2s1: i2s@1c22400 { 914 #sound-dai-cells = <0>; 915 compatible = "allwinner,sun50i-a64-i2s", 916 "allwinner,sun8i-h3-i2s"; 917 reg = <0x01c22400 0x400>; 918 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 920 clock-names = "apb", "mod"; 921 resets = <&ccu RST_BUS_I2S1>; 922 dma-names = "rx", "tx"; 923 dmas = <&dma 4>, <&dma 4>; 924 status = "disabled"; 925 }; 926 927 i2s2: i2s@1c22800 { 928 #sound-dai-cells = <0>; 929 compatible = "allwinner,sun50i-a64-i2s", 930 "allwinner,sun8i-h3-i2s"; 931 reg = <0x01c22800 0x400>; 932 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 934 clock-names = "apb", "mod"; 935 resets = <&ccu RST_BUS_I2S2>; 936 dma-names = "rx", "tx"; 937 dmas = <&dma 27>, <&dma 27>; 938 status = "disabled"; 939 }; 940 941 dai: dai@1c22c00 { 942 #sound-dai-cells = <0>; 943 compatible = "allwinner,sun50i-a64-codec-i2s"; 944 reg = <0x01c22c00 0x200>; 945 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 947 clock-names = "apb", "mod"; 948 resets = <&ccu RST_BUS_CODEC>; 949 dmas = <&dma 15>, <&dma 15>; 950 dma-names = "rx", "tx"; 951 status = "disabled"; 952 }; 953 954 codec: codec@1c22e00 { 955 #sound-dai-cells = <1>; 956 compatible = "allwinner,sun50i-a64-codec", 957 "allwinner,sun8i-a33-codec"; 958 reg = <0x01c22e00 0x600>; 959 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 961 clock-names = "bus", "mod"; 962 status = "disabled"; 963 }; 964 965 ths: thermal-sensor@1c25000 { 966 compatible = "allwinner,sun50i-a64-ths"; 967 reg = <0x01c25000 0x100>; 968 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 969 clock-names = "bus", "mod"; 970 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 971 resets = <&ccu RST_BUS_THS>; 972 nvmem-cells = <&ths_calibration>; 973 nvmem-cell-names = "calibration"; 974 #thermal-sensor-cells = <1>; 975 }; 976 977 uart0: serial@1c28000 { 978 compatible = "snps,dw-apb-uart"; 979 reg = <0x01c28000 0x400>; 980 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 981 reg-shift = <2>; 982 reg-io-width = <4>; 983 clocks = <&ccu CLK_BUS_UART0>; 984 resets = <&ccu RST_BUS_UART0>; 985 status = "disabled"; 986 }; 987 988 uart1: serial@1c28400 { 989 compatible = "snps,dw-apb-uart"; 990 reg = <0x01c28400 0x400>; 991 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 992 reg-shift = <2>; 993 reg-io-width = <4>; 994 clocks = <&ccu CLK_BUS_UART1>; 995 resets = <&ccu RST_BUS_UART1>; 996 status = "disabled"; 997 }; 998 999 uart2: serial@1c28800 { 1000 compatible = "snps,dw-apb-uart"; 1001 reg = <0x01c28800 0x400>; 1002 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1003 reg-shift = <2>; 1004 reg-io-width = <4>; 1005 clocks = <&ccu CLK_BUS_UART2>; 1006 resets = <&ccu RST_BUS_UART2>; 1007 status = "disabled"; 1008 }; 1009 1010 uart3: serial@1c28c00 { 1011 compatible = "snps,dw-apb-uart"; 1012 reg = <0x01c28c00 0x400>; 1013 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1014 reg-shift = <2>; 1015 reg-io-width = <4>; 1016 clocks = <&ccu CLK_BUS_UART3>; 1017 resets = <&ccu RST_BUS_UART3>; 1018 status = "disabled"; 1019 }; 1020 1021 uart4: serial@1c29000 { 1022 compatible = "snps,dw-apb-uart"; 1023 reg = <0x01c29000 0x400>; 1024 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1025 reg-shift = <2>; 1026 reg-io-width = <4>; 1027 clocks = <&ccu CLK_BUS_UART4>; 1028 resets = <&ccu RST_BUS_UART4>; 1029 status = "disabled"; 1030 }; 1031 1032 i2c0: i2c@1c2ac00 { 1033 compatible = "allwinner,sun6i-a31-i2c"; 1034 reg = <0x01c2ac00 0x400>; 1035 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1036 clocks = <&ccu CLK_BUS_I2C0>; 1037 resets = <&ccu RST_BUS_I2C0>; 1038 pinctrl-names = "default"; 1039 pinctrl-0 = <&i2c0_pins>; 1040 status = "disabled"; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 }; 1044 1045 i2c1: i2c@1c2b000 { 1046 compatible = "allwinner,sun6i-a31-i2c"; 1047 reg = <0x01c2b000 0x400>; 1048 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1049 clocks = <&ccu CLK_BUS_I2C1>; 1050 resets = <&ccu RST_BUS_I2C1>; 1051 pinctrl-names = "default"; 1052 pinctrl-0 = <&i2c1_pins>; 1053 status = "disabled"; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 }; 1057 1058 i2c2: i2c@1c2b400 { 1059 compatible = "allwinner,sun6i-a31-i2c"; 1060 reg = <0x01c2b400 0x400>; 1061 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1062 clocks = <&ccu CLK_BUS_I2C2>; 1063 resets = <&ccu RST_BUS_I2C2>; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&i2c2_pins>; 1066 status = "disabled"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 }; 1070 1071 spi0: spi@1c68000 { 1072 compatible = "allwinner,sun8i-h3-spi"; 1073 reg = <0x01c68000 0x1000>; 1074 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 1076 clock-names = "ahb", "mod"; 1077 dmas = <&dma 23>, <&dma 23>; 1078 dma-names = "rx", "tx"; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&spi0_pins>; 1081 resets = <&ccu RST_BUS_SPI0>; 1082 status = "disabled"; 1083 num-cs = <1>; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 }; 1087 1088 spi1: spi@1c69000 { 1089 compatible = "allwinner,sun8i-h3-spi"; 1090 reg = <0x01c69000 0x1000>; 1091 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 1093 clock-names = "ahb", "mod"; 1094 dmas = <&dma 24>, <&dma 24>; 1095 dma-names = "rx", "tx"; 1096 pinctrl-names = "default"; 1097 pinctrl-0 = <&spi1_pins>; 1098 resets = <&ccu RST_BUS_SPI1>; 1099 status = "disabled"; 1100 num-cs = <1>; 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 }; 1104 1105 emac: ethernet@1c30000 { 1106 compatible = "allwinner,sun50i-a64-emac"; 1107 syscon = <&syscon>; 1108 reg = <0x01c30000 0x10000>; 1109 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1110 interrupt-names = "macirq"; 1111 resets = <&ccu RST_BUS_EMAC>; 1112 reset-names = "stmmaceth"; 1113 clocks = <&ccu CLK_BUS_EMAC>; 1114 clock-names = "stmmaceth"; 1115 status = "disabled"; 1116 1117 mdio: mdio { 1118 compatible = "snps,dwmac-mdio"; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 }; 1122 }; 1123 1124 mali: gpu@1c40000 { 1125 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 1126 reg = <0x01c40000 0x10000>; 1127 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1134 interrupt-names = "gp", 1135 "gpmmu", 1136 "pp0", 1137 "ppmmu0", 1138 "pp1", 1139 "ppmmu1", 1140 "pmu"; 1141 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 1142 clock-names = "bus", "core"; 1143 resets = <&ccu RST_BUS_GPU>; 1144 operating-points-v2 = <&gpu_opp_table>; 1145 }; 1146 1147 gic: interrupt-controller@1c81000 { 1148 compatible = "arm,gic-400"; 1149 reg = <0x01c81000 0x1000>, 1150 <0x01c82000 0x2000>, 1151 <0x01c84000 0x2000>, 1152 <0x01c86000 0x2000>; 1153 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1154 interrupt-controller; 1155 #interrupt-cells = <3>; 1156 }; 1157 1158 pwm: pwm@1c21400 { 1159 compatible = "allwinner,sun50i-a64-pwm", 1160 "allwinner,sun5i-a13-pwm"; 1161 reg = <0x01c21400 0x400>; 1162 clocks = <&osc24M>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&pwm_pin>; 1165 #pwm-cells = <3>; 1166 status = "disabled"; 1167 }; 1168 1169 mbus: dram-controller@1c62000 { 1170 compatible = "allwinner,sun50i-a64-mbus"; 1171 reg = <0x01c62000 0x1000>, 1172 <0x01c63000 0x1000>; 1173 reg-names = "mbus", "dram"; 1174 clocks = <&ccu CLK_MBUS>, 1175 <&ccu CLK_DRAM>, 1176 <&ccu CLK_BUS_DRAM>; 1177 clock-names = "mbus", "dram", "bus"; 1178 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1179 #address-cells = <1>; 1180 #size-cells = <1>; 1181 dma-ranges = <0x00000000 0x40000000 0xc0000000>; 1182 #interconnect-cells = <1>; 1183 }; 1184 1185 csi: csi@1cb0000 { 1186 compatible = "allwinner,sun50i-a64-csi"; 1187 reg = <0x01cb0000 0x1000>; 1188 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1189 clocks = <&ccu CLK_BUS_CSI>, 1190 <&ccu CLK_CSI_SCLK>, 1191 <&ccu CLK_DRAM_CSI>; 1192 clock-names = "bus", "mod", "ram"; 1193 resets = <&ccu RST_BUS_CSI>; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&csi_pins>; 1196 status = "disabled"; 1197 }; 1198 1199 dsi: dsi@1ca0000 { 1200 compatible = "allwinner,sun50i-a64-mipi-dsi"; 1201 reg = <0x01ca0000 0x1000>; 1202 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&ccu CLK_BUS_MIPI_DSI>; 1204 resets = <&ccu RST_BUS_MIPI_DSI>; 1205 phys = <&dphy>; 1206 phy-names = "dphy"; 1207 status = "disabled"; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 1211 port { 1212 dsi_in_tcon0: endpoint { 1213 remote-endpoint = <&tcon0_out_dsi>; 1214 }; 1215 }; 1216 }; 1217 1218 dphy: d-phy@1ca1000 { 1219 compatible = "allwinner,sun50i-a64-mipi-dphy", 1220 "allwinner,sun6i-a31-mipi-dphy"; 1221 reg = <0x01ca1000 0x1000>; 1222 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&ccu CLK_BUS_MIPI_DSI>, 1224 <&ccu CLK_DSI_DPHY>; 1225 clock-names = "bus", "mod"; 1226 resets = <&ccu RST_BUS_MIPI_DSI>; 1227 status = "disabled"; 1228 #phy-cells = <0>; 1229 }; 1230 1231 deinterlace: deinterlace@1e00000 { 1232 compatible = "allwinner,sun50i-a64-deinterlace", 1233 "allwinner,sun8i-h3-deinterlace"; 1234 reg = <0x01e00000 0x20000>; 1235 clocks = <&ccu CLK_BUS_DEINTERLACE>, 1236 <&ccu CLK_DEINTERLACE>, 1237 <&ccu CLK_DRAM_DEINTERLACE>; 1238 clock-names = "bus", "mod", "ram"; 1239 resets = <&ccu RST_BUS_DEINTERLACE>; 1240 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1241 interconnects = <&mbus 9>; 1242 interconnect-names = "dma-mem"; 1243 }; 1244 1245 hdmi: hdmi@1ee0000 { 1246 compatible = "allwinner,sun50i-a64-dw-hdmi", 1247 "allwinner,sun8i-a83t-dw-hdmi"; 1248 reg = <0x01ee0000 0x10000>; 1249 reg-io-width = <1>; 1250 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1251 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1252 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; 1253 clock-names = "iahb", "isfr", "tmds", "cec"; 1254 resets = <&ccu RST_BUS_HDMI1>; 1255 reset-names = "ctrl"; 1256 phys = <&hdmi_phy>; 1257 phy-names = "phy"; 1258 status = "disabled"; 1259 1260 ports { 1261 #address-cells = <1>; 1262 #size-cells = <0>; 1263 1264 hdmi_in: port@0 { 1265 reg = <0>; 1266 1267 hdmi_in_tcon1: endpoint { 1268 remote-endpoint = <&tcon1_out_hdmi>; 1269 }; 1270 }; 1271 1272 hdmi_out: port@1 { 1273 reg = <1>; 1274 }; 1275 }; 1276 }; 1277 1278 hdmi_phy: hdmi-phy@1ef0000 { 1279 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1280 reg = <0x01ef0000 0x10000>; 1281 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1282 <&ccu CLK_PLL_VIDEO0>; 1283 clock-names = "bus", "mod", "pll-0"; 1284 resets = <&ccu RST_BUS_HDMI0>; 1285 reset-names = "phy"; 1286 #phy-cells = <0>; 1287 }; 1288 1289 rtc: rtc@1f00000 { 1290 compatible = "allwinner,sun50i-a64-rtc", 1291 "allwinner,sun8i-h3-rtc"; 1292 reg = <0x01f00000 0x400>; 1293 interrupt-parent = <&r_intc>; 1294 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1296 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1297 clocks = <&osc32k>; 1298 #clock-cells = <1>; 1299 }; 1300 1301 r_intc: interrupt-controller@1f00c00 { 1302 compatible = "allwinner,sun50i-a64-r-intc", 1303 "allwinner,sun6i-a31-r-intc"; 1304 interrupt-controller; 1305 #interrupt-cells = <3>; 1306 reg = <0x01f00c00 0x400>; 1307 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1308 }; 1309 1310 r_ccu: clock@1f01400 { 1311 compatible = "allwinner,sun50i-a64-r-ccu"; 1312 reg = <0x01f01400 0x100>; 1313 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 1314 <&ccu CLK_PLL_PERIPH0>; 1315 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1316 #clock-cells = <1>; 1317 #reset-cells = <1>; 1318 }; 1319 1320 codec_analog: codec-analog@1f015c0 { 1321 compatible = "allwinner,sun50i-a64-codec-analog"; 1322 reg = <0x01f015c0 0x4>; 1323 status = "disabled"; 1324 }; 1325 1326 r_i2c: i2c@1f02400 { 1327 compatible = "allwinner,sun50i-a64-i2c", 1328 "allwinner,sun6i-a31-i2c"; 1329 reg = <0x01f02400 0x400>; 1330 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1331 clocks = <&r_ccu CLK_APB0_I2C>; 1332 resets = <&r_ccu RST_APB0_I2C>; 1333 status = "disabled"; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 }; 1337 1338 r_ir: ir@1f02000 { 1339 compatible = "allwinner,sun50i-a64-ir", 1340 "allwinner,sun6i-a31-ir"; 1341 reg = <0x01f02000 0x400>; 1342 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1343 clock-names = "apb", "ir"; 1344 resets = <&r_ccu RST_APB0_IR>; 1345 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1346 pinctrl-names = "default"; 1347 pinctrl-0 = <&r_ir_rx_pin>; 1348 status = "disabled"; 1349 }; 1350 1351 r_pwm: pwm@1f03800 { 1352 compatible = "allwinner,sun50i-a64-pwm", 1353 "allwinner,sun5i-a13-pwm"; 1354 reg = <0x01f03800 0x400>; 1355 clocks = <&osc24M>; 1356 pinctrl-names = "default"; 1357 pinctrl-0 = <&r_pwm_pin>; 1358 #pwm-cells = <3>; 1359 status = "disabled"; 1360 }; 1361 1362 r_pio: pinctrl@1f02c00 { 1363 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1364 reg = <0x01f02c00 0x400>; 1365 interrupt-parent = <&r_intc>; 1366 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1367 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1368 clock-names = "apb", "hosc", "losc"; 1369 gpio-controller; 1370 #gpio-cells = <3>; 1371 interrupt-controller; 1372 #interrupt-cells = <3>; 1373 1374 r_i2c_pl89_pins: r-i2c-pl89-pins { 1375 pins = "PL8", "PL9"; 1376 function = "s_i2c"; 1377 }; 1378 1379 r_ir_rx_pin: r-ir-rx-pin { 1380 pins = "PL11"; 1381 function = "s_cir_rx"; 1382 }; 1383 1384 r_pwm_pin: r-pwm-pin { 1385 pins = "PL10"; 1386 function = "s_pwm"; 1387 }; 1388 1389 r_rsb_pins: r-rsb-pins { 1390 pins = "PL0", "PL1"; 1391 function = "s_rsb"; 1392 }; 1393 }; 1394 1395 r_rsb: rsb@1f03400 { 1396 compatible = "allwinner,sun8i-a23-rsb"; 1397 reg = <0x01f03400 0x400>; 1398 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1399 clocks = <&r_ccu 6>; 1400 clock-frequency = <3000000>; 1401 resets = <&r_ccu 2>; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&r_rsb_pins>; 1404 status = "disabled"; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 }; 1408 }; 1409}; 1410