1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2016 ARM Ltd. 3// based on the Allwinner H3 dtsi: 4// Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 6#include <dt-bindings/clock/sun50i-a64-ccu.h> 7#include <dt-bindings/clock/sun6i-rtc.h> 8#include <dt-bindings/clock/sun8i-de2.h> 9#include <dt-bindings/clock/sun8i-r-ccu.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/sun50i-a64-ccu.h> 12#include <dt-bindings/reset/sun8i-de2.h> 13#include <dt-bindings/reset/sun8i-r-ccu.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 chosen { 22 #address-cells = <1>; 23 #size-cells = <1>; 24 ranges; 25 26 simplefb_lcd: framebuffer-lcd { 27 compatible = "allwinner,simple-framebuffer", 28 "simple-framebuffer"; 29 allwinner,pipeline = "mixer0-lcd0"; 30 clocks = <&ccu CLK_TCON0>, 31 <&display_clocks CLK_MIXER0>; 32 status = "disabled"; 33 }; 34 35 simplefb_hdmi: framebuffer-hdmi { 36 compatible = "allwinner,simple-framebuffer", 37 "simple-framebuffer"; 38 allwinner,pipeline = "mixer1-lcd1-hdmi"; 39 clocks = <&display_clocks CLK_MIXER1>, 40 <&ccu CLK_TCON1>, <&ccu CLK_HDMI>; 41 status = "disabled"; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 compatible = "arm,cortex-a53"; 51 device_type = "cpu"; 52 reg = <0>; 53 enable-method = "psci"; 54 next-level-cache = <&L2>; 55 clocks = <&ccu CLK_CPUX>; 56 clock-names = "cpu"; 57 #cooling-cells = <2>; 58 }; 59 60 cpu1: cpu@1 { 61 compatible = "arm,cortex-a53"; 62 device_type = "cpu"; 63 reg = <1>; 64 enable-method = "psci"; 65 next-level-cache = <&L2>; 66 clocks = <&ccu CLK_CPUX>; 67 clock-names = "cpu"; 68 #cooling-cells = <2>; 69 }; 70 71 cpu2: cpu@2 { 72 compatible = "arm,cortex-a53"; 73 device_type = "cpu"; 74 reg = <2>; 75 enable-method = "psci"; 76 next-level-cache = <&L2>; 77 clocks = <&ccu CLK_CPUX>; 78 clock-names = "cpu"; 79 #cooling-cells = <2>; 80 }; 81 82 cpu3: cpu@3 { 83 compatible = "arm,cortex-a53"; 84 device_type = "cpu"; 85 reg = <3>; 86 enable-method = "psci"; 87 next-level-cache = <&L2>; 88 clocks = <&ccu CLK_CPUX>; 89 clock-names = "cpu"; 90 #cooling-cells = <2>; 91 }; 92 93 L2: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 }; 98 }; 99 100 de: display-engine { 101 compatible = "allwinner,sun50i-a64-display-engine"; 102 allwinner,pipelines = <&mixer0>, 103 <&mixer1>; 104 status = "disabled"; 105 }; 106 107 gpu_opp_table: opp-table-gpu { 108 compatible = "operating-points-v2"; 109 110 opp-432000000 { 111 opp-hz = /bits/ 64 <432000000>; 112 }; 113 }; 114 115 osc24M: osc24M-clk { 116 #clock-cells = <0>; 117 compatible = "fixed-clock"; 118 clock-frequency = <24000000>; 119 clock-output-names = "osc24M"; 120 }; 121 122 osc32k: osc32k-clk { 123 #clock-cells = <0>; 124 compatible = "fixed-clock"; 125 clock-frequency = <32768>; 126 clock-output-names = "ext-osc32k"; 127 }; 128 129 pmu { 130 compatible = "arm,cortex-a53-pmu"; 131 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 135 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 136 }; 137 138 psci { 139 compatible = "arm,psci-0.2"; 140 method = "smc"; 141 }; 142 143 sound: sound { 144 #address-cells = <1>; 145 #size-cells = <0>; 146 compatible = "simple-audio-card"; 147 simple-audio-card,name = "sun50i-a64-audio"; 148 simple-audio-card,aux-devs = <&codec_analog>; 149 simple-audio-card,routing = 150 "Left DAC", "DACL", 151 "Right DAC", "DACR", 152 "ADCL", "Left ADC", 153 "ADCR", "Right ADC"; 154 status = "disabled"; 155 156 simple-audio-card,dai-link@0 { 157 format = "i2s"; 158 frame-master = <&link0_cpu>; 159 bitclock-master = <&link0_cpu>; 160 mclk-fs = <128>; 161 162 link0_cpu: cpu { 163 sound-dai = <&dai>; 164 }; 165 166 link0_codec: codec { 167 sound-dai = <&codec 0>; 168 }; 169 }; 170 }; 171 172 timer { 173 compatible = "arm,armv8-timer"; 174 allwinner,erratum-unknown1; 175 arm,no-tick-in-suspend; 176 interrupts = <GIC_PPI 13 177 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 178 <GIC_PPI 14 179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 180 <GIC_PPI 11 181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 182 <GIC_PPI 10 183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 184 }; 185 186 thermal-zones { 187 cpu_thermal: cpu0-thermal { 188 /* milliseconds */ 189 polling-delay-passive = <0>; 190 polling-delay = <0>; 191 thermal-sensors = <&ths 0>; 192 193 cooling-maps { 194 map0 { 195 trip = <&cpu_alert0>; 196 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 197 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 198 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 199 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 200 }; 201 map1 { 202 trip = <&cpu_alert1>; 203 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 204 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 205 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 206 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 207 }; 208 }; 209 210 trips { 211 cpu_alert0: cpu-alert0 { 212 /* milliCelsius */ 213 temperature = <75000>; 214 hysteresis = <2000>; 215 type = "passive"; 216 }; 217 218 cpu_alert1: cpu-alert1 { 219 /* milliCelsius */ 220 temperature = <90000>; 221 hysteresis = <2000>; 222 type = "hot"; 223 }; 224 225 cpu_crit: cpu-crit { 226 /* milliCelsius */ 227 temperature = <110000>; 228 hysteresis = <2000>; 229 type = "critical"; 230 }; 231 }; 232 }; 233 234 gpu0_thermal: gpu0-thermal { 235 /* milliseconds */ 236 polling-delay-passive = <0>; 237 polling-delay = <0>; 238 thermal-sensors = <&ths 1>; 239 }; 240 241 gpu1_thermal: gpu1-thermal { 242 /* milliseconds */ 243 polling-delay-passive = <0>; 244 polling-delay = <0>; 245 thermal-sensors = <&ths 2>; 246 }; 247 }; 248 249 soc { 250 compatible = "simple-bus"; 251 #address-cells = <1>; 252 #size-cells = <1>; 253 ranges; 254 255 bus@1000000 { 256 compatible = "allwinner,sun50i-a64-de2"; 257 reg = <0x1000000 0x400000>; 258 allwinner,sram = <&de2_sram 1>; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 ranges = <0 0x1000000 0x400000>; 262 263 display_clocks: clock@0 { 264 compatible = "allwinner,sun50i-a64-de2-clk"; 265 reg = <0x0 0x10000>; 266 clocks = <&ccu CLK_BUS_DE>, 267 <&ccu CLK_DE>; 268 clock-names = "bus", 269 "mod"; 270 resets = <&ccu RST_BUS_DE>; 271 #clock-cells = <1>; 272 #reset-cells = <1>; 273 }; 274 275 rotate: rotate@20000 { 276 compatible = "allwinner,sun50i-a64-de2-rotate", 277 "allwinner,sun8i-a83t-de2-rotate"; 278 reg = <0x20000 0x10000>; 279 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&display_clocks CLK_BUS_ROT>, 281 <&display_clocks CLK_ROT>; 282 clock-names = "bus", 283 "mod"; 284 resets = <&display_clocks RST_ROT>; 285 }; 286 287 mixer0: mixer@100000 { 288 compatible = "allwinner,sun50i-a64-de2-mixer-0"; 289 reg = <0x100000 0x100000>; 290 clocks = <&display_clocks CLK_BUS_MIXER0>, 291 <&display_clocks CLK_MIXER0>; 292 clock-names = "bus", 293 "mod"; 294 resets = <&display_clocks RST_MIXER0>; 295 296 ports { 297 #address-cells = <1>; 298 #size-cells = <0>; 299 300 mixer0_out: port@1 { 301 #address-cells = <1>; 302 #size-cells = <0>; 303 reg = <1>; 304 305 mixer0_out_tcon0: endpoint@0 { 306 reg = <0>; 307 remote-endpoint = <&tcon0_in_mixer0>; 308 }; 309 310 mixer0_out_tcon1: endpoint@1 { 311 reg = <1>; 312 remote-endpoint = <&tcon1_in_mixer0>; 313 }; 314 }; 315 }; 316 }; 317 318 mixer1: mixer@200000 { 319 compatible = "allwinner,sun50i-a64-de2-mixer-1"; 320 reg = <0x200000 0x100000>; 321 clocks = <&display_clocks CLK_BUS_MIXER1>, 322 <&display_clocks CLK_MIXER1>; 323 clock-names = "bus", 324 "mod"; 325 resets = <&display_clocks RST_MIXER1>; 326 327 ports { 328 #address-cells = <1>; 329 #size-cells = <0>; 330 331 mixer1_out: port@1 { 332 #address-cells = <1>; 333 #size-cells = <0>; 334 reg = <1>; 335 336 mixer1_out_tcon0: endpoint@0 { 337 reg = <0>; 338 remote-endpoint = <&tcon0_in_mixer1>; 339 }; 340 341 mixer1_out_tcon1: endpoint@1 { 342 reg = <1>; 343 remote-endpoint = <&tcon1_in_mixer1>; 344 }; 345 }; 346 }; 347 }; 348 }; 349 350 syscon: syscon@1c00000 { 351 compatible = "allwinner,sun50i-a64-system-control"; 352 reg = <0x01c00000 0x1000>; 353 #address-cells = <1>; 354 #size-cells = <1>; 355 ranges; 356 357 sram_c: sram@18000 { 358 compatible = "mmio-sram"; 359 reg = <0x00018000 0x28000>; 360 #address-cells = <1>; 361 #size-cells = <1>; 362 ranges = <0 0x00018000 0x28000>; 363 364 de2_sram: sram-section@0 { 365 compatible = "allwinner,sun50i-a64-sram-c"; 366 reg = <0x0000 0x28000>; 367 }; 368 }; 369 370 sram_c1: sram@1d00000 { 371 compatible = "mmio-sram"; 372 reg = <0x01d00000 0x40000>; 373 #address-cells = <1>; 374 #size-cells = <1>; 375 ranges = <0 0x01d00000 0x40000>; 376 377 ve_sram: sram-section@0 { 378 compatible = "allwinner,sun50i-a64-sram-c1", 379 "allwinner,sun4i-a10-sram-c1"; 380 reg = <0x000000 0x40000>; 381 }; 382 }; 383 }; 384 385 dma: dma-controller@1c02000 { 386 compatible = "allwinner,sun50i-a64-dma"; 387 reg = <0x01c02000 0x1000>; 388 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&ccu CLK_BUS_DMA>; 390 dma-channels = <8>; 391 dma-requests = <27>; 392 resets = <&ccu RST_BUS_DMA>; 393 #dma-cells = <1>; 394 }; 395 396 tcon0: lcd-controller@1c0c000 { 397 compatible = "allwinner,sun50i-a64-tcon-lcd", 398 "allwinner,sun8i-a83t-tcon-lcd"; 399 reg = <0x01c0c000 0x1000>; 400 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 401 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 402 clock-names = "ahb", "tcon-ch0"; 403 clock-output-names = "tcon-data-clock"; 404 #clock-cells = <0>; 405 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>; 406 reset-names = "lcd", "lvds"; 407 408 ports { 409 #address-cells = <1>; 410 #size-cells = <0>; 411 412 tcon0_in: port@0 { 413 #address-cells = <1>; 414 #size-cells = <0>; 415 reg = <0>; 416 417 tcon0_in_mixer0: endpoint@0 { 418 reg = <0>; 419 remote-endpoint = <&mixer0_out_tcon0>; 420 }; 421 422 tcon0_in_mixer1: endpoint@1 { 423 reg = <1>; 424 remote-endpoint = <&mixer1_out_tcon0>; 425 }; 426 }; 427 428 tcon0_out: port@1 { 429 #address-cells = <1>; 430 #size-cells = <0>; 431 reg = <1>; 432 433 tcon0_out_dsi: endpoint@1 { 434 reg = <1>; 435 remote-endpoint = <&dsi_in_tcon0>; 436 allwinner,tcon-channel = <1>; 437 }; 438 }; 439 }; 440 }; 441 442 tcon1: lcd-controller@1c0d000 { 443 compatible = "allwinner,sun50i-a64-tcon-tv", 444 "allwinner,sun8i-a83t-tcon-tv"; 445 reg = <0x01c0d000 0x1000>; 446 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>; 448 clock-names = "ahb", "tcon-ch1"; 449 resets = <&ccu RST_BUS_TCON1>; 450 reset-names = "lcd"; 451 452 ports { 453 #address-cells = <1>; 454 #size-cells = <0>; 455 456 tcon1_in: port@0 { 457 #address-cells = <1>; 458 #size-cells = <0>; 459 reg = <0>; 460 461 tcon1_in_mixer0: endpoint@0 { 462 reg = <0>; 463 remote-endpoint = <&mixer0_out_tcon1>; 464 }; 465 466 tcon1_in_mixer1: endpoint@1 { 467 reg = <1>; 468 remote-endpoint = <&mixer1_out_tcon1>; 469 }; 470 }; 471 472 tcon1_out: port@1 { 473 #address-cells = <1>; 474 #size-cells = <0>; 475 reg = <1>; 476 477 tcon1_out_hdmi: endpoint@1 { 478 reg = <1>; 479 remote-endpoint = <&hdmi_in_tcon1>; 480 }; 481 }; 482 }; 483 }; 484 485 video-codec@1c0e000 { 486 compatible = "allwinner,sun50i-a64-video-engine"; 487 reg = <0x01c0e000 0x1000>; 488 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 489 <&ccu CLK_DRAM_VE>; 490 clock-names = "ahb", "mod", "ram"; 491 resets = <&ccu RST_BUS_VE>; 492 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 493 allwinner,sram = <&ve_sram 1>; 494 }; 495 496 mmc0: mmc@1c0f000 { 497 compatible = "allwinner,sun50i-a64-mmc"; 498 reg = <0x01c0f000 0x1000>; 499 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 500 clock-names = "ahb", "mmc"; 501 resets = <&ccu RST_BUS_MMC0>; 502 reset-names = "ahb"; 503 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 504 max-frequency = <150000000>; 505 status = "disabled"; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 }; 509 510 mmc1: mmc@1c10000 { 511 compatible = "allwinner,sun50i-a64-mmc"; 512 reg = <0x01c10000 0x1000>; 513 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 514 clock-names = "ahb", "mmc"; 515 resets = <&ccu RST_BUS_MMC1>; 516 reset-names = "ahb"; 517 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 518 max-frequency = <150000000>; 519 status = "disabled"; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 }; 523 524 mmc2: mmc@1c11000 { 525 compatible = "allwinner,sun50i-a64-emmc"; 526 reg = <0x01c11000 0x1000>; 527 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 528 clock-names = "ahb", "mmc"; 529 resets = <&ccu RST_BUS_MMC2>; 530 reset-names = "ahb"; 531 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 532 max-frequency = <150000000>; 533 status = "disabled"; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 }; 537 538 sid: eeprom@1c14000 { 539 compatible = "allwinner,sun50i-a64-sid"; 540 reg = <0x1c14000 0x400>; 541 #address-cells = <1>; 542 #size-cells = <1>; 543 544 ths_calibration: thermal-sensor-calibration@34 { 545 reg = <0x34 0x8>; 546 }; 547 }; 548 549 crypto: crypto@1c15000 { 550 compatible = "allwinner,sun50i-a64-crypto"; 551 reg = <0x01c15000 0x1000>; 552 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 553 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 554 clock-names = "bus", "mod"; 555 resets = <&ccu RST_BUS_CE>; 556 }; 557 558 msgbox: mailbox@1c17000 { 559 compatible = "allwinner,sun50i-a64-msgbox", 560 "allwinner,sun6i-a31-msgbox"; 561 reg = <0x01c17000 0x1000>; 562 clocks = <&ccu CLK_BUS_MSGBOX>; 563 resets = <&ccu RST_BUS_MSGBOX>; 564 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 565 #mbox-cells = <1>; 566 }; 567 568 usb_otg: usb@1c19000 { 569 compatible = "allwinner,sun8i-a33-musb"; 570 reg = <0x01c19000 0x0400>; 571 clocks = <&ccu CLK_BUS_OTG>; 572 resets = <&ccu RST_BUS_OTG>; 573 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-names = "mc"; 575 phys = <&usbphy 0>; 576 phy-names = "usb"; 577 extcon = <&usbphy 0>; 578 dr_mode = "otg"; 579 status = "disabled"; 580 }; 581 582 usbphy: phy@1c19400 { 583 compatible = "allwinner,sun50i-a64-usb-phy"; 584 reg = <0x01c19400 0x14>, 585 <0x01c1a800 0x4>, 586 <0x01c1b800 0x4>; 587 reg-names = "phy_ctrl", 588 "pmu0", 589 "pmu1"; 590 clocks = <&ccu CLK_USB_PHY0>, 591 <&ccu CLK_USB_PHY1>; 592 clock-names = "usb0_phy", 593 "usb1_phy"; 594 resets = <&ccu RST_USB_PHY0>, 595 <&ccu RST_USB_PHY1>; 596 reset-names = "usb0_reset", 597 "usb1_reset"; 598 status = "disabled"; 599 #phy-cells = <1>; 600 }; 601 602 ehci0: usb@1c1a000 { 603 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 604 reg = <0x01c1a000 0x100>; 605 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&ccu CLK_BUS_OHCI0>, 607 <&ccu CLK_BUS_EHCI0>, 608 <&ccu CLK_USB_OHCI0>; 609 resets = <&ccu RST_BUS_OHCI0>, 610 <&ccu RST_BUS_EHCI0>; 611 phys = <&usbphy 0>; 612 phy-names = "usb"; 613 status = "disabled"; 614 }; 615 616 ohci0: usb@1c1a400 { 617 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 618 reg = <0x01c1a400 0x100>; 619 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&ccu CLK_BUS_OHCI0>, 621 <&ccu CLK_USB_OHCI0>; 622 resets = <&ccu RST_BUS_OHCI0>; 623 phys = <&usbphy 0>; 624 phy-names = "usb"; 625 status = "disabled"; 626 }; 627 628 ehci1: usb@1c1b000 { 629 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 630 reg = <0x01c1b000 0x100>; 631 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 632 clocks = <&ccu CLK_BUS_OHCI1>, 633 <&ccu CLK_BUS_EHCI1>, 634 <&ccu CLK_USB_OHCI1>; 635 resets = <&ccu RST_BUS_OHCI1>, 636 <&ccu RST_BUS_EHCI1>; 637 phys = <&usbphy 1>; 638 phy-names = "usb"; 639 status = "disabled"; 640 }; 641 642 ohci1: usb@1c1b400 { 643 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 644 reg = <0x01c1b400 0x100>; 645 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&ccu CLK_BUS_OHCI1>, 647 <&ccu CLK_USB_OHCI1>; 648 resets = <&ccu RST_BUS_OHCI1>; 649 phys = <&usbphy 1>; 650 phy-names = "usb"; 651 status = "disabled"; 652 }; 653 654 ccu: clock@1c20000 { 655 compatible = "allwinner,sun50i-a64-ccu"; 656 reg = <0x01c20000 0x400>; 657 clocks = <&osc24M>, <&rtc CLK_OSC32K>; 658 clock-names = "hosc", "losc"; 659 #clock-cells = <1>; 660 #reset-cells = <1>; 661 }; 662 663 pio: pinctrl@1c20800 { 664 compatible = "allwinner,sun50i-a64-pinctrl"; 665 reg = <0x01c20800 0x400>; 666 interrupt-parent = <&r_intc>; 667 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, 671 <&rtc CLK_OSC32K>; 672 clock-names = "apb", "hosc", "losc"; 673 gpio-controller; 674 #gpio-cells = <3>; 675 interrupt-controller; 676 #interrupt-cells = <3>; 677 678 /omit-if-no-ref/ 679 aif2_pins: aif2-pins { 680 pins = "PB4", "PB5", "PB6", "PB7"; 681 function = "aif2"; 682 }; 683 684 /omit-if-no-ref/ 685 aif3_pins: aif3-pins { 686 pins = "PG10", "PG11", "PG12", "PG13"; 687 function = "aif3"; 688 }; 689 690 csi_pins: csi-pins { 691 pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6", 692 "PE7", "PE8", "PE9", "PE10", "PE11"; 693 function = "csi"; 694 }; 695 696 /omit-if-no-ref/ 697 csi_mclk_pin: csi-mclk-pin { 698 pins = "PE1"; 699 function = "csi"; 700 }; 701 702 i2c0_pins: i2c0-pins { 703 pins = "PH0", "PH1"; 704 function = "i2c0"; 705 }; 706 707 i2c1_pins: i2c1-pins { 708 pins = "PH2", "PH3"; 709 function = "i2c1"; 710 }; 711 712 i2c2_pins: i2c2-pins { 713 pins = "PE14", "PE15"; 714 function = "i2c2"; 715 }; 716 717 /omit-if-no-ref/ 718 lcd_rgb666_pins: lcd-rgb666-pins { 719 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 720 "PD5", "PD6", "PD7", "PD8", "PD9", 721 "PD10", "PD11", "PD12", "PD13", 722 "PD14", "PD15", "PD16", "PD17", 723 "PD18", "PD19", "PD20", "PD21"; 724 function = "lcd0"; 725 }; 726 727 mmc0_pins: mmc0-pins { 728 pins = "PF0", "PF1", "PF2", "PF3", 729 "PF4", "PF5"; 730 function = "mmc0"; 731 drive-strength = <30>; 732 bias-pull-up; 733 }; 734 735 mmc1_pins: mmc1-pins { 736 pins = "PG0", "PG1", "PG2", "PG3", 737 "PG4", "PG5"; 738 function = "mmc1"; 739 drive-strength = <30>; 740 bias-pull-up; 741 }; 742 743 mmc2_pins: mmc2-pins { 744 pins = "PC5", "PC6", "PC8", "PC9", 745 "PC10","PC11", "PC12", "PC13", 746 "PC14", "PC15", "PC16"; 747 function = "mmc2"; 748 drive-strength = <30>; 749 bias-pull-up; 750 }; 751 752 mmc2_ds_pin: mmc2-ds-pin { 753 pins = "PC1"; 754 function = "mmc2"; 755 drive-strength = <30>; 756 bias-pull-up; 757 }; 758 759 pwm_pin: pwm-pin { 760 pins = "PD22"; 761 function = "pwm"; 762 }; 763 764 rmii_pins: rmii-pins { 765 pins = "PD10", "PD11", "PD13", "PD14", "PD17", 766 "PD18", "PD19", "PD20", "PD22", "PD23"; 767 function = "emac"; 768 drive-strength = <40>; 769 }; 770 771 rgmii_pins: rgmii-pins { 772 pins = "PD8", "PD9", "PD10", "PD11", "PD12", 773 "PD13", "PD15", "PD16", "PD17", "PD18", 774 "PD19", "PD20", "PD21", "PD22", "PD23"; 775 function = "emac"; 776 drive-strength = <40>; 777 }; 778 779 spdif_tx_pin: spdif-tx-pin { 780 pins = "PH8"; 781 function = "spdif"; 782 }; 783 784 spi0_pins: spi0-pins { 785 pins = "PC0", "PC1", "PC2", "PC3"; 786 function = "spi0"; 787 }; 788 789 spi1_pins: spi1-pins { 790 pins = "PD0", "PD1", "PD2", "PD3"; 791 function = "spi1"; 792 }; 793 794 uart0_pb_pins: uart0-pb-pins { 795 pins = "PB8", "PB9"; 796 function = "uart0"; 797 }; 798 799 uart1_pins: uart1-pins { 800 pins = "PG6", "PG7"; 801 function = "uart1"; 802 }; 803 804 uart1_rts_cts_pins: uart1-rts-cts-pins { 805 pins = "PG8", "PG9"; 806 function = "uart1"; 807 }; 808 809 uart2_pins: uart2-pins { 810 pins = "PB0", "PB1"; 811 function = "uart2"; 812 }; 813 814 uart3_pins: uart3-pins { 815 pins = "PD0", "PD1"; 816 function = "uart3"; 817 }; 818 819 uart4_pins: uart4-pins { 820 pins = "PD2", "PD3"; 821 function = "uart4"; 822 }; 823 824 uart4_rts_cts_pins: uart4-rts-cts-pins { 825 pins = "PD4", "PD5"; 826 function = "uart4"; 827 }; 828 }; 829 830 timer@1c20c00 { 831 compatible = "allwinner,sun50i-a64-timer", 832 "allwinner,sun8i-a23-timer"; 833 reg = <0x01c20c00 0xa0>; 834 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&osc24M>; 837 }; 838 839 wdt0: watchdog@1c20ca0 { 840 compatible = "allwinner,sun50i-a64-wdt", 841 "allwinner,sun6i-a31-wdt"; 842 reg = <0x01c20ca0 0x20>; 843 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&osc24M>; 845 }; 846 847 spdif: spdif@1c21000 { 848 #sound-dai-cells = <0>; 849 compatible = "allwinner,sun50i-a64-spdif", 850 "allwinner,sun8i-h3-spdif"; 851 reg = <0x01c21000 0x400>; 852 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 854 resets = <&ccu RST_BUS_SPDIF>; 855 clock-names = "apb", "spdif"; 856 dmas = <&dma 2>; 857 dma-names = "tx"; 858 pinctrl-names = "default"; 859 pinctrl-0 = <&spdif_tx_pin>; 860 status = "disabled"; 861 }; 862 863 lradc: lradc@1c21800 { 864 compatible = "allwinner,sun50i-a64-lradc", 865 "allwinner,sun8i-a83t-r-lradc"; 866 reg = <0x01c21800 0x400>; 867 interrupt-parent = <&r_intc>; 868 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 869 status = "disabled"; 870 }; 871 872 i2s0: i2s@1c22000 { 873 #sound-dai-cells = <0>; 874 compatible = "allwinner,sun50i-a64-i2s", 875 "allwinner,sun8i-h3-i2s"; 876 reg = <0x01c22000 0x400>; 877 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 879 clock-names = "apb", "mod"; 880 resets = <&ccu RST_BUS_I2S0>; 881 dma-names = "rx", "tx"; 882 dmas = <&dma 3>, <&dma 3>; 883 status = "disabled"; 884 }; 885 886 i2s1: i2s@1c22400 { 887 #sound-dai-cells = <0>; 888 compatible = "allwinner,sun50i-a64-i2s", 889 "allwinner,sun8i-h3-i2s"; 890 reg = <0x01c22400 0x400>; 891 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 892 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 893 clock-names = "apb", "mod"; 894 resets = <&ccu RST_BUS_I2S1>; 895 dma-names = "rx", "tx"; 896 dmas = <&dma 4>, <&dma 4>; 897 status = "disabled"; 898 }; 899 900 i2s2: i2s@1c22800 { 901 #sound-dai-cells = <0>; 902 compatible = "allwinner,sun50i-a64-i2s", 903 "allwinner,sun8i-h3-i2s"; 904 reg = <0x01c22800 0x400>; 905 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>; 907 clock-names = "apb", "mod"; 908 resets = <&ccu RST_BUS_I2S2>; 909 dma-names = "rx", "tx"; 910 dmas = <&dma 27>, <&dma 27>; 911 status = "disabled"; 912 }; 913 914 dai: dai@1c22c00 { 915 #sound-dai-cells = <0>; 916 compatible = "allwinner,sun50i-a64-codec-i2s"; 917 reg = <0x01c22c00 0x200>; 918 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 920 clock-names = "apb", "mod"; 921 resets = <&ccu RST_BUS_CODEC>; 922 dmas = <&dma 15>, <&dma 15>; 923 dma-names = "rx", "tx"; 924 status = "disabled"; 925 }; 926 927 codec: codec@1c22e00 { 928 #sound-dai-cells = <1>; 929 compatible = "allwinner,sun50i-a64-codec", 930 "allwinner,sun8i-a33-codec"; 931 reg = <0x01c22e00 0x600>; 932 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 933 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 934 clock-names = "bus", "mod"; 935 status = "disabled"; 936 }; 937 938 ths: thermal-sensor@1c25000 { 939 compatible = "allwinner,sun50i-a64-ths"; 940 reg = <0x01c25000 0x100>; 941 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 942 clock-names = "bus", "mod"; 943 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 944 resets = <&ccu RST_BUS_THS>; 945 nvmem-cells = <&ths_calibration>; 946 nvmem-cell-names = "calibration"; 947 #thermal-sensor-cells = <1>; 948 }; 949 950 uart0: serial@1c28000 { 951 compatible = "snps,dw-apb-uart"; 952 reg = <0x01c28000 0x400>; 953 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 954 reg-shift = <2>; 955 reg-io-width = <4>; 956 clocks = <&ccu CLK_BUS_UART0>; 957 resets = <&ccu RST_BUS_UART0>; 958 status = "disabled"; 959 }; 960 961 uart1: serial@1c28400 { 962 compatible = "snps,dw-apb-uart"; 963 reg = <0x01c28400 0x400>; 964 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 965 reg-shift = <2>; 966 reg-io-width = <4>; 967 clocks = <&ccu CLK_BUS_UART1>; 968 resets = <&ccu RST_BUS_UART1>; 969 status = "disabled"; 970 }; 971 972 uart2: serial@1c28800 { 973 compatible = "snps,dw-apb-uart"; 974 reg = <0x01c28800 0x400>; 975 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 976 reg-shift = <2>; 977 reg-io-width = <4>; 978 clocks = <&ccu CLK_BUS_UART2>; 979 resets = <&ccu RST_BUS_UART2>; 980 status = "disabled"; 981 }; 982 983 uart3: serial@1c28c00 { 984 compatible = "snps,dw-apb-uart"; 985 reg = <0x01c28c00 0x400>; 986 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 987 reg-shift = <2>; 988 reg-io-width = <4>; 989 clocks = <&ccu CLK_BUS_UART3>; 990 resets = <&ccu RST_BUS_UART3>; 991 status = "disabled"; 992 }; 993 994 uart4: serial@1c29000 { 995 compatible = "snps,dw-apb-uart"; 996 reg = <0x01c29000 0x400>; 997 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 998 reg-shift = <2>; 999 reg-io-width = <4>; 1000 clocks = <&ccu CLK_BUS_UART4>; 1001 resets = <&ccu RST_BUS_UART4>; 1002 status = "disabled"; 1003 }; 1004 1005 i2c0: i2c@1c2ac00 { 1006 compatible = "allwinner,sun6i-a31-i2c"; 1007 reg = <0x01c2ac00 0x400>; 1008 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&ccu CLK_BUS_I2C0>; 1010 resets = <&ccu RST_BUS_I2C0>; 1011 pinctrl-names = "default"; 1012 pinctrl-0 = <&i2c0_pins>; 1013 status = "disabled"; 1014 #address-cells = <1>; 1015 #size-cells = <0>; 1016 }; 1017 1018 i2c1: i2c@1c2b000 { 1019 compatible = "allwinner,sun6i-a31-i2c"; 1020 reg = <0x01c2b000 0x400>; 1021 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&ccu CLK_BUS_I2C1>; 1023 resets = <&ccu RST_BUS_I2C1>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&i2c1_pins>; 1026 status = "disabled"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 }; 1030 1031 i2c2: i2c@1c2b400 { 1032 compatible = "allwinner,sun6i-a31-i2c"; 1033 reg = <0x01c2b400 0x400>; 1034 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&ccu CLK_BUS_I2C2>; 1036 resets = <&ccu RST_BUS_I2C2>; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&i2c2_pins>; 1039 status = "disabled"; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 }; 1043 1044 spi0: spi@1c68000 { 1045 compatible = "allwinner,sun8i-h3-spi"; 1046 reg = <0x01c68000 0x1000>; 1047 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 1049 clock-names = "ahb", "mod"; 1050 dmas = <&dma 23>, <&dma 23>; 1051 dma-names = "rx", "tx"; 1052 pinctrl-names = "default"; 1053 pinctrl-0 = <&spi0_pins>; 1054 resets = <&ccu RST_BUS_SPI0>; 1055 status = "disabled"; 1056 num-cs = <1>; 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 }; 1060 1061 spi1: spi@1c69000 { 1062 compatible = "allwinner,sun8i-h3-spi"; 1063 reg = <0x01c69000 0x1000>; 1064 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 1066 clock-names = "ahb", "mod"; 1067 dmas = <&dma 24>, <&dma 24>; 1068 dma-names = "rx", "tx"; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&spi1_pins>; 1071 resets = <&ccu RST_BUS_SPI1>; 1072 status = "disabled"; 1073 num-cs = <1>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 }; 1077 1078 emac: ethernet@1c30000 { 1079 compatible = "allwinner,sun50i-a64-emac"; 1080 syscon = <&syscon>; 1081 reg = <0x01c30000 0x10000>; 1082 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1083 interrupt-names = "macirq"; 1084 resets = <&ccu RST_BUS_EMAC>; 1085 reset-names = "stmmaceth"; 1086 clocks = <&ccu CLK_BUS_EMAC>; 1087 clock-names = "stmmaceth"; 1088 status = "disabled"; 1089 1090 mdio: mdio { 1091 compatible = "snps,dwmac-mdio"; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 }; 1095 }; 1096 1097 mali: gpu@1c40000 { 1098 compatible = "allwinner,sun50i-a64-mali", "arm,mali-400"; 1099 reg = <0x01c40000 0x10000>; 1100 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1107 interrupt-names = "gp", 1108 "gpmmu", 1109 "pp0", 1110 "ppmmu0", 1111 "pp1", 1112 "ppmmu1", 1113 "pmu"; 1114 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 1115 clock-names = "bus", "core"; 1116 resets = <&ccu RST_BUS_GPU>; 1117 operating-points-v2 = <&gpu_opp_table>; 1118 }; 1119 1120 gic: interrupt-controller@1c81000 { 1121 compatible = "arm,gic-400"; 1122 reg = <0x01c81000 0x1000>, 1123 <0x01c82000 0x2000>, 1124 <0x01c84000 0x2000>, 1125 <0x01c86000 0x2000>; 1126 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1127 interrupt-controller; 1128 #interrupt-cells = <3>; 1129 }; 1130 1131 pwm: pwm@1c21400 { 1132 compatible = "allwinner,sun50i-a64-pwm", 1133 "allwinner,sun5i-a13-pwm"; 1134 reg = <0x01c21400 0x400>; 1135 clocks = <&osc24M>; 1136 pinctrl-names = "default"; 1137 pinctrl-0 = <&pwm_pin>; 1138 #pwm-cells = <3>; 1139 status = "disabled"; 1140 }; 1141 1142 mbus: dram-controller@1c62000 { 1143 compatible = "allwinner,sun50i-a64-mbus"; 1144 reg = <0x01c62000 0x1000>, 1145 <0x01c63000 0x1000>; 1146 reg-names = "mbus", "dram"; 1147 clocks = <&ccu CLK_MBUS>, 1148 <&ccu CLK_DRAM>, 1149 <&ccu CLK_BUS_DRAM>; 1150 clock-names = "mbus", "dram", "bus"; 1151 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1152 #address-cells = <1>; 1153 #size-cells = <1>; 1154 dma-ranges = <0x00000000 0x40000000 0xc0000000>; 1155 #interconnect-cells = <1>; 1156 }; 1157 1158 csi: csi@1cb0000 { 1159 compatible = "allwinner,sun50i-a64-csi"; 1160 reg = <0x01cb0000 0x1000>; 1161 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&ccu CLK_BUS_CSI>, 1163 <&ccu CLK_CSI_SCLK>, 1164 <&ccu CLK_DRAM_CSI>; 1165 clock-names = "bus", "mod", "ram"; 1166 resets = <&ccu RST_BUS_CSI>; 1167 pinctrl-names = "default"; 1168 pinctrl-0 = <&csi_pins>; 1169 status = "disabled"; 1170 }; 1171 1172 dsi: dsi@1ca0000 { 1173 compatible = "allwinner,sun50i-a64-mipi-dsi"; 1174 reg = <0x01ca0000 0x1000>; 1175 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1176 clocks = <&ccu CLK_BUS_MIPI_DSI>; 1177 resets = <&ccu RST_BUS_MIPI_DSI>; 1178 phys = <&dphy>; 1179 phy-names = "dphy"; 1180 status = "disabled"; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 1184 port { 1185 dsi_in_tcon0: endpoint { 1186 remote-endpoint = <&tcon0_out_dsi>; 1187 }; 1188 }; 1189 }; 1190 1191 dphy: d-phy@1ca1000 { 1192 compatible = "allwinner,sun50i-a64-mipi-dphy", 1193 "allwinner,sun6i-a31-mipi-dphy"; 1194 reg = <0x01ca1000 0x1000>; 1195 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1196 clocks = <&ccu CLK_BUS_MIPI_DSI>, 1197 <&ccu CLK_DSI_DPHY>; 1198 clock-names = "bus", "mod"; 1199 resets = <&ccu RST_BUS_MIPI_DSI>; 1200 status = "disabled"; 1201 #phy-cells = <0>; 1202 }; 1203 1204 deinterlace: deinterlace@1e00000 { 1205 compatible = "allwinner,sun50i-a64-deinterlace", 1206 "allwinner,sun8i-h3-deinterlace"; 1207 reg = <0x01e00000 0x20000>; 1208 clocks = <&ccu CLK_BUS_DEINTERLACE>, 1209 <&ccu CLK_DEINTERLACE>, 1210 <&ccu CLK_DRAM_DEINTERLACE>; 1211 clock-names = "bus", "mod", "ram"; 1212 resets = <&ccu RST_BUS_DEINTERLACE>; 1213 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1214 interconnects = <&mbus 9>; 1215 interconnect-names = "dma-mem"; 1216 }; 1217 1218 hdmi: hdmi@1ee0000 { 1219 compatible = "allwinner,sun50i-a64-dw-hdmi", 1220 "allwinner,sun8i-a83t-dw-hdmi"; 1221 reg = <0x01ee0000 0x10000>; 1222 reg-io-width = <1>; 1223 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1224 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1225 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>; 1226 clock-names = "iahb", "isfr", "tmds", "cec"; 1227 resets = <&ccu RST_BUS_HDMI1>; 1228 reset-names = "ctrl"; 1229 phys = <&hdmi_phy>; 1230 phy-names = "phy"; 1231 status = "disabled"; 1232 1233 ports { 1234 #address-cells = <1>; 1235 #size-cells = <0>; 1236 1237 hdmi_in: port@0 { 1238 reg = <0>; 1239 1240 hdmi_in_tcon1: endpoint { 1241 remote-endpoint = <&tcon1_out_hdmi>; 1242 }; 1243 }; 1244 1245 hdmi_out: port@1 { 1246 reg = <1>; 1247 }; 1248 }; 1249 }; 1250 1251 hdmi_phy: hdmi-phy@1ef0000 { 1252 compatible = "allwinner,sun50i-a64-hdmi-phy"; 1253 reg = <0x01ef0000 0x10000>; 1254 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 1255 <&ccu CLK_PLL_VIDEO0>; 1256 clock-names = "bus", "mod", "pll-0"; 1257 resets = <&ccu RST_BUS_HDMI0>; 1258 reset-names = "phy"; 1259 #phy-cells = <0>; 1260 }; 1261 1262 rtc: rtc@1f00000 { 1263 compatible = "allwinner,sun50i-a64-rtc", 1264 "allwinner,sun8i-h3-rtc"; 1265 reg = <0x01f00000 0x400>; 1266 interrupt-parent = <&r_intc>; 1267 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1269 clock-output-names = "osc32k", "osc32k-out", "iosc"; 1270 clocks = <&osc32k>; 1271 #clock-cells = <1>; 1272 }; 1273 1274 r_intc: interrupt-controller@1f00c00 { 1275 compatible = "allwinner,sun50i-a64-r-intc", 1276 "allwinner,sun6i-a31-r-intc"; 1277 interrupt-controller; 1278 #interrupt-cells = <3>; 1279 reg = <0x01f00c00 0x400>; 1280 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1281 }; 1282 1283 r_ccu: clock@1f01400 { 1284 compatible = "allwinner,sun50i-a64-r-ccu"; 1285 reg = <0x01f01400 0x100>; 1286 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 1287 <&ccu CLK_PLL_PERIPH0>; 1288 clock-names = "hosc", "losc", "iosc", "pll-periph"; 1289 #clock-cells = <1>; 1290 #reset-cells = <1>; 1291 }; 1292 1293 codec_analog: codec-analog@1f015c0 { 1294 compatible = "allwinner,sun50i-a64-codec-analog"; 1295 reg = <0x01f015c0 0x4>; 1296 status = "disabled"; 1297 }; 1298 1299 r_i2c: i2c@1f02400 { 1300 compatible = "allwinner,sun50i-a64-i2c", 1301 "allwinner,sun6i-a31-i2c"; 1302 reg = <0x01f02400 0x400>; 1303 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&r_ccu CLK_APB0_I2C>; 1305 resets = <&r_ccu RST_APB0_I2C>; 1306 status = "disabled"; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 }; 1310 1311 r_ir: ir@1f02000 { 1312 compatible = "allwinner,sun50i-a64-ir", 1313 "allwinner,sun6i-a31-ir"; 1314 reg = <0x01f02000 0x400>; 1315 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 1316 clock-names = "apb", "ir"; 1317 resets = <&r_ccu RST_APB0_IR>; 1318 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1319 pinctrl-names = "default"; 1320 pinctrl-0 = <&r_ir_rx_pin>; 1321 status = "disabled"; 1322 }; 1323 1324 r_pwm: pwm@1f03800 { 1325 compatible = "allwinner,sun50i-a64-pwm", 1326 "allwinner,sun5i-a13-pwm"; 1327 reg = <0x01f03800 0x400>; 1328 clocks = <&osc24M>; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&r_pwm_pin>; 1331 #pwm-cells = <3>; 1332 status = "disabled"; 1333 }; 1334 1335 r_pio: pinctrl@1f02c00 { 1336 compatible = "allwinner,sun50i-a64-r-pinctrl"; 1337 reg = <0x01f02c00 0x400>; 1338 interrupt-parent = <&r_intc>; 1339 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1340 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 1341 clock-names = "apb", "hosc", "losc"; 1342 gpio-controller; 1343 #gpio-cells = <3>; 1344 interrupt-controller; 1345 #interrupt-cells = <3>; 1346 1347 r_i2c_pl89_pins: r-i2c-pl89-pins { 1348 pins = "PL8", "PL9"; 1349 function = "s_i2c"; 1350 }; 1351 1352 r_ir_rx_pin: r-ir-rx-pin { 1353 pins = "PL11"; 1354 function = "s_cir_rx"; 1355 }; 1356 1357 r_pwm_pin: r-pwm-pin { 1358 pins = "PL10"; 1359 function = "s_pwm"; 1360 }; 1361 1362 r_rsb_pins: r-rsb-pins { 1363 pins = "PL0", "PL1"; 1364 function = "s_rsb"; 1365 }; 1366 }; 1367 1368 r_rsb: rsb@1f03400 { 1369 compatible = "allwinner,sun8i-a23-rsb"; 1370 reg = <0x01f03400 0x400>; 1371 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1372 clocks = <&r_ccu 6>; 1373 clock-frequency = <3000000>; 1374 resets = <&r_ccu 2>; 1375 pinctrl-names = "default"; 1376 pinctrl-0 = <&r_rsb_pins>; 1377 status = "disabled"; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 }; 1381 }; 1382}; 1383