1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-a100-ccu.h> 8#include <dt-bindings/clock/sun50i-a100-r-ccu.h> 9#include <dt-bindings/reset/sun50i-a100-ccu.h> 10#include <dt-bindings/reset/sun50i-a100-r-ccu.h> 11 12/ { 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu0: cpu@0 { 22 compatible = "arm,cortex-a53"; 23 device_type = "cpu"; 24 reg = <0x0>; 25 enable-method = "psci"; 26 }; 27 28 cpu1: cpu@1 { 29 compatible = "arm,cortex-a53"; 30 device_type = "cpu"; 31 reg = <0x1>; 32 enable-method = "psci"; 33 }; 34 35 cpu2: cpu@2 { 36 compatible = "arm,cortex-a53"; 37 device_type = "cpu"; 38 reg = <0x2>; 39 enable-method = "psci"; 40 }; 41 42 cpu3: cpu@3 { 43 compatible = "arm,cortex-a53"; 44 device_type = "cpu"; 45 reg = <0x3>; 46 enable-method = "psci"; 47 }; 48 }; 49 50 pmu { 51 compatible = "arm,cortex-a53-pmu"; 52 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 53 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 56 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 57 }; 58 59 psci { 60 compatible = "arm,psci-1.0"; 61 method = "smc"; 62 }; 63 64 dcxo24M: dcxo24M-clk { 65 compatible = "fixed-clock"; 66 clock-frequency = <24000000>; 67 clock-output-names = "dcxo24M"; 68 #clock-cells = <0>; 69 }; 70 71 iosc: internal-osc-clk { 72 compatible = "fixed-clock"; 73 clock-frequency = <16000000>; 74 clock-accuracy = <300000000>; 75 clock-output-names = "iosc"; 76 #clock-cells = <0>; 77 }; 78 79 osc32k: osc32k-clk { 80 compatible = "fixed-clock"; 81 clock-frequency = <32768>; 82 clock-output-names = "osc32k"; 83 #clock-cells = <0>; 84 }; 85 86 timer { 87 compatible = "arm,armv8-timer"; 88 interrupts = <GIC_PPI 13 89 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 90 <GIC_PPI 14 91 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 92 <GIC_PPI 11 93 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 94 <GIC_PPI 10 95 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 96 }; 97 98 soc { 99 compatible = "simple-bus"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges = <0 0 0 0x3fffffff>; 103 104 ccu: clock@3001000 { 105 compatible = "allwinner,sun50i-a100-ccu"; 106 reg = <0x03001000 0x1000>; 107 clocks = <&dcxo24M>, <&osc32k>, <&iosc>; 108 clock-names = "hosc", "losc", "iosc"; 109 #clock-cells = <1>; 110 #reset-cells = <1>; 111 }; 112 113 dma: dma-controller@3002000 { 114 compatible = "allwinner,sun50i-a100-dma"; 115 reg = <0x03002000 0x1000>; 116 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 118 clock-names = "bus", "mbus"; 119 resets = <&ccu RST_BUS_DMA>; 120 dma-channels = <8>; 121 dma-requests = <52>; 122 #dma-cells = <1>; 123 }; 124 125 gic: interrupt-controller@3021000 { 126 compatible = "arm,gic-400"; 127 reg = <0x03021000 0x1000>, <0x03022000 0x2000>, 128 <0x03024000 0x2000>, <0x03026000 0x2000>; 129 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 130 IRQ_TYPE_LEVEL_HIGH)>; 131 interrupt-controller; 132 #interrupt-cells = <3>; 133 }; 134 135 efuse@3006000 { 136 compatible = "allwinner,sun50i-a100-sid", 137 "allwinner,sun50i-a64-sid"; 138 reg = <0x03006000 0x1000>; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 142 ths_calibration: calib@14 { 143 reg = <0x14 8>; 144 }; 145 }; 146 147 watchdog@30090a0 { 148 compatible = "allwinner,sun50i-a100-wdt", 149 "allwinner,sun6i-a31-wdt"; 150 reg = <0x030090a0 0x20>; 151 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 152 clocks = <&dcxo24M>; 153 }; 154 155 pio: pinctrl@300b000 { 156 compatible = "allwinner,sun50i-a100-pinctrl"; 157 reg = <0x0300b000 0x400>; 158 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 165 clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>; 166 clock-names = "apb", "hosc", "losc"; 167 gpio-controller; 168 #gpio-cells = <3>; 169 interrupt-controller; 170 #interrupt-cells = <3>; 171 172 mmc0_pins: mmc0-pins { 173 pins = "PF0", "PF1", "PF2", "PF3", 174 "PF4", "PF5"; 175 function = "mmc0"; 176 drive-strength = <30>; 177 bias-pull-up; 178 }; 179 180 /omit-if-no-ref/ 181 mmc1_pins: mmc1-pins { 182 pins = "PG0", "PG1", "PG2", "PG3", 183 "PG4", "PG5"; 184 function = "mmc1"; 185 drive-strength = <30>; 186 bias-pull-up; 187 }; 188 189 mmc2_pins: mmc2-pins { 190 pins = "PC0", "PC1", "PC5", "PC6", 191 "PC8", "PC9", "PC10", "PC11", 192 "PC13", "PC14", "PC15", "PC16"; 193 function = "mmc2"; 194 drive-strength = <30>; 195 bias-pull-up; 196 }; 197 198 uart0_pb_pins: uart0-pb-pins { 199 pins = "PB9", "PB10"; 200 function = "uart0"; 201 }; 202 }; 203 204 mmc0: mmc@4020000 { 205 compatible = "allwinner,sun50i-a100-mmc"; 206 reg = <0x04020000 0x1000>; 207 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 208 clock-names = "ahb", "mmc"; 209 resets = <&ccu RST_BUS_MMC0>; 210 reset-names = "ahb"; 211 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&mmc0_pins>; 214 status = "disabled"; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 }; 218 219 mmc1: mmc@4021000 { 220 compatible = "allwinner,sun50i-a100-mmc"; 221 reg = <0x04021000 0x1000>; 222 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 223 clock-names = "ahb", "mmc"; 224 resets = <&ccu RST_BUS_MMC1>; 225 reset-names = "ahb"; 226 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 227 pinctrl-names = "default"; 228 pinctrl-0 = <&mmc1_pins>; 229 status = "disabled"; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 }; 233 234 mmc2: mmc@4022000 { 235 compatible = "allwinner,sun50i-a100-emmc"; 236 reg = <0x04022000 0x1000>; 237 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 238 clock-names = "ahb", "mmc"; 239 resets = <&ccu RST_BUS_MMC2>; 240 reset-names = "ahb"; 241 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&mmc2_pins>; 244 status = "disabled"; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 }; 248 249 uart0: serial@5000000 { 250 compatible = "snps,dw-apb-uart"; 251 reg = <0x05000000 0x400>; 252 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 253 reg-shift = <2>; 254 reg-io-width = <4>; 255 clocks = <&ccu CLK_BUS_UART0>; 256 resets = <&ccu RST_BUS_UART0>; 257 status = "disabled"; 258 }; 259 260 uart1: serial@5000400 { 261 compatible = "snps,dw-apb-uart"; 262 reg = <0x05000400 0x400>; 263 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 264 reg-shift = <2>; 265 reg-io-width = <4>; 266 clocks = <&ccu CLK_BUS_UART1>; 267 resets = <&ccu RST_BUS_UART1>; 268 status = "disabled"; 269 }; 270 271 uart2: serial@5000800 { 272 compatible = "snps,dw-apb-uart"; 273 reg = <0x05000800 0x400>; 274 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 275 reg-shift = <2>; 276 reg-io-width = <4>; 277 clocks = <&ccu CLK_BUS_UART2>; 278 resets = <&ccu RST_BUS_UART2>; 279 status = "disabled"; 280 }; 281 282 uart3: serial@5000c00 { 283 compatible = "snps,dw-apb-uart"; 284 reg = <0x05000c00 0x400>; 285 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 286 reg-shift = <2>; 287 reg-io-width = <4>; 288 clocks = <&ccu CLK_BUS_UART3>; 289 resets = <&ccu RST_BUS_UART3>; 290 status = "disabled"; 291 }; 292 293 uart4: serial@5001000 { 294 compatible = "snps,dw-apb-uart"; 295 reg = <0x05001000 0x400>; 296 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 297 reg-shift = <2>; 298 reg-io-width = <4>; 299 clocks = <&ccu CLK_BUS_UART4>; 300 resets = <&ccu RST_BUS_UART4>; 301 status = "disabled"; 302 }; 303 304 i2c0: i2c@5002000 { 305 compatible = "allwinner,sun50i-a100-i2c", 306 "allwinner,sun8i-v536-i2c", 307 "allwinner,sun6i-a31-i2c"; 308 reg = <0x05002000 0x400>; 309 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&ccu CLK_BUS_I2C0>; 311 resets = <&ccu RST_BUS_I2C0>; 312 dmas = <&dma 43>, <&dma 43>; 313 dma-names = "rx", "tx"; 314 status = "disabled"; 315 #address-cells = <1>; 316 #size-cells = <0>; 317 }; 318 319 i2c1: i2c@5002400 { 320 compatible = "allwinner,sun50i-a100-i2c", 321 "allwinner,sun8i-v536-i2c", 322 "allwinner,sun6i-a31-i2c"; 323 reg = <0x05002400 0x400>; 324 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&ccu CLK_BUS_I2C1>; 326 resets = <&ccu RST_BUS_I2C1>; 327 dmas = <&dma 44>, <&dma 44>; 328 dma-names = "rx", "tx"; 329 status = "disabled"; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 }; 333 334 i2c2: i2c@5002800 { 335 compatible = "allwinner,sun50i-a100-i2c", 336 "allwinner,sun8i-v536-i2c", 337 "allwinner,sun6i-a31-i2c"; 338 reg = <0x05002800 0x400>; 339 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&ccu CLK_BUS_I2C2>; 341 resets = <&ccu RST_BUS_I2C2>; 342 dmas = <&dma 45>, <&dma 45>; 343 dma-names = "rx", "tx"; 344 status = "disabled"; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 }; 348 349 i2c3: i2c@5002c00 { 350 compatible = "allwinner,sun50i-a100-i2c", 351 "allwinner,sun8i-v536-i2c", 352 "allwinner,sun6i-a31-i2c"; 353 reg = <0x05002c00 0x400>; 354 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&ccu CLK_BUS_I2C3>; 356 resets = <&ccu RST_BUS_I2C3>; 357 dmas = <&dma 46>, <&dma 46>; 358 dma-names = "rx", "tx"; 359 status = "disabled"; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 }; 363 364 ths: thermal-sensor@5070400 { 365 compatible = "allwinner,sun50i-a100-ths"; 366 reg = <0x05070400 0x100>; 367 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&ccu CLK_BUS_THS>; 369 clock-names = "bus"; 370 resets = <&ccu RST_BUS_THS>; 371 nvmem-cells = <&ths_calibration>; 372 nvmem-cell-names = "calibration"; 373 #thermal-sensor-cells = <1>; 374 }; 375 376 usb_otg: usb@5100000 { 377 compatible = "allwinner,sun50i-a100-musb", 378 "allwinner,sun8i-a33-musb"; 379 reg = <0x05100000 0x0400>; 380 clocks = <&ccu CLK_BUS_OTG>; 381 resets = <&ccu RST_BUS_OTG>; 382 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 383 interrupt-names = "mc"; 384 phys = <&usbphy 0>; 385 phy-names = "usb"; 386 extcon = <&usbphy 0>; 387 status = "disabled"; 388 }; 389 390 usbphy: phy@5100400 { 391 compatible = "allwinner,sun50i-a100-usb-phy", 392 "allwinner,sun20i-d1-usb-phy"; 393 reg = <0x05100400 0x100>, 394 <0x05101800 0x100>, 395 <0x05200800 0x100>; 396 reg-names = "phy_ctrl", 397 "pmu0", 398 "pmu1"; 399 clocks = <&ccu CLK_USB_PHY0>, 400 <&ccu CLK_USB_PHY1>; 401 clock-names = "usb0_phy", 402 "usb1_phy"; 403 resets = <&ccu RST_USB_PHY0>, 404 <&ccu RST_USB_PHY1>; 405 reset-names = "usb0_reset", 406 "usb1_reset"; 407 status = "disabled"; 408 #phy-cells = <1>; 409 }; 410 411 ehci0: usb@5101000 { 412 compatible = "allwinner,sun50i-a100-ehci", 413 "generic-ehci"; 414 reg = <0x05101000 0x100>; 415 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&ccu CLK_BUS_OHCI0>, 417 <&ccu CLK_BUS_EHCI0>, 418 <&ccu CLK_USB_OHCI0>; 419 resets = <&ccu RST_BUS_OHCI0>, 420 <&ccu RST_BUS_EHCI0>; 421 phys = <&usbphy 0>; 422 phy-names = "usb"; 423 status = "disabled"; 424 }; 425 426 ohci0: usb@5101400 { 427 compatible = "allwinner,sun50i-a100-ohci", 428 "generic-ohci"; 429 reg = <0x05101400 0x100>; 430 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&ccu CLK_BUS_OHCI0>, 432 <&ccu CLK_USB_OHCI0>; 433 resets = <&ccu RST_BUS_OHCI0>; 434 phys = <&usbphy 0>; 435 phy-names = "usb"; 436 status = "disabled"; 437 }; 438 439 ehci1: usb@5200000 { 440 compatible = "allwinner,sun50i-a100-ehci", 441 "generic-ehci"; 442 reg = <0x05200000 0x100>; 443 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&ccu CLK_BUS_OHCI1>, 445 <&ccu CLK_BUS_EHCI1>, 446 <&ccu CLK_USB_OHCI1>; 447 resets = <&ccu RST_BUS_OHCI1>, 448 <&ccu RST_BUS_EHCI1>; 449 phys = <&usbphy 1>; 450 phy-names = "usb"; 451 status = "disabled"; 452 }; 453 454 ohci1: usb@5200400 { 455 compatible = "allwinner,sun50i-a100-ohci", 456 "generic-ohci"; 457 reg = <0x05200400 0x100>; 458 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&ccu CLK_BUS_OHCI1>, 460 <&ccu CLK_USB_OHCI1>; 461 resets = <&ccu RST_BUS_OHCI1>; 462 phys = <&usbphy 1>; 463 phy-names = "usb"; 464 status = "disabled"; 465 }; 466 467 r_ccu: clock@7010000 { 468 compatible = "allwinner,sun50i-a100-r-ccu"; 469 reg = <0x07010000 0x300>; 470 clocks = <&dcxo24M>, <&osc32k>, <&iosc>, 471 <&ccu CLK_PLL_PERIPH0>; 472 clock-names = "hosc", "losc", "iosc", "pll-periph"; 473 #clock-cells = <1>; 474 #reset-cells = <1>; 475 }; 476 477 r_intc: interrupt-controller@7010320 { 478 compatible = "allwinner,sun50i-a100-nmi", 479 "allwinner,sun9i-a80-nmi"; 480 interrupt-controller; 481 #interrupt-cells = <2>; 482 reg = <0x07010320 0xc>; 483 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 484 }; 485 486 r_pio: pinctrl@7022000 { 487 compatible = "allwinner,sun50i-a100-r-pinctrl"; 488 reg = <0x07022000 0x400>; 489 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&r_ccu CLK_R_APB1>, <&dcxo24M>, <&osc32k>; 491 clock-names = "apb", "hosc", "losc"; 492 gpio-controller; 493 #gpio-cells = <3>; 494 interrupt-controller; 495 #interrupt-cells = <3>; 496 497 r_i2c0_pins: r-i2c0-pins { 498 pins = "PL0", "PL1"; 499 function = "s_i2c0"; 500 }; 501 502 r_i2c1_pins: r-i2c1-pins { 503 pins = "PL8", "PL9"; 504 function = "s_i2c1"; 505 }; 506 }; 507 508 r_uart: serial@7080000 { 509 compatible = "snps,dw-apb-uart"; 510 reg = <0x07080000 0x400>; 511 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 512 reg-shift = <2>; 513 reg-io-width = <4>; 514 clocks = <&r_ccu CLK_R_APB2_UART>; 515 resets = <&r_ccu RST_R_APB2_UART>; 516 status = "disabled"; 517 }; 518 519 r_i2c0: i2c@7081400 { 520 compatible = "allwinner,sun50i-a100-i2c", 521 "allwinner,sun8i-v536-i2c", 522 "allwinner,sun6i-a31-i2c"; 523 reg = <0x07081400 0x400>; 524 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&r_ccu CLK_R_APB2_I2C0>; 526 resets = <&r_ccu RST_R_APB2_I2C0>; 527 dmas = <&dma 50>, <&dma 50>; 528 dma-names = "rx", "tx"; 529 pinctrl-names = "default"; 530 pinctrl-0 = <&r_i2c0_pins>; 531 status = "disabled"; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 }; 535 536 r_i2c1: i2c@7081800 { 537 compatible = "allwinner,sun50i-a100-i2c", 538 "allwinner,sun8i-v536-i2c", 539 "allwinner,sun6i-a31-i2c"; 540 reg = <0x07081800 0x400>; 541 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&r_ccu CLK_R_APB2_I2C1>; 543 resets = <&r_ccu RST_R_APB2_I2C1>; 544 dmas = <&dma 51>, <&dma 51>; 545 dma-names = "rx", "tx"; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&r_i2c1_pins>; 548 status = "disabled"; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 }; 552 }; 553 554 thermal-zones { 555 cpu-thermal { 556 polling-delay-passive = <0>; 557 polling-delay = <0>; 558 thermal-sensors = <&ths 0>; 559 }; 560 561 ddr-thermal { 562 polling-delay-passive = <0>; 563 polling-delay = <0>; 564 thermal-sensors = <&ths 2>; 565 }; 566 567 gpu-thermal { 568 polling-delay-passive = <0>; 569 polling-delay = <0>; 570 thermal-sensors = <&ths 1>; 571 }; 572 }; 573}; 574