1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 3#include <dt-bindings/interrupt-controller/irq.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5 6/ { 7 interrupt-parent = <&gic>; 8 #address-cells = <2>; 9 #size-cells = <2>; 10 11 reserved-memory { 12 #address-cells = <2>; 13 #size-cells = <2>; 14 ranges; 15 16 npu-binary@84000000 { 17 no-map; 18 reg = <0x0 0x84000000 0x0 0xa00000>; 19 }; 20 21 npu-flag@84b0000 { 22 no-map; 23 reg = <0x0 0x84b00000 0x0 0x100000>; 24 }; 25 26 npu-pkt@85000000 { 27 no-map; 28 reg = <0x0 0x85000000 0x0 0x1a00000>; 29 }; 30 31 npu-phyaddr@86b00000 { 32 no-map; 33 reg = <0x0 0x86b00000 0x0 0x100000>; 34 }; 35 36 npu-rxdesc@86d00000 { 37 no-map; 38 reg = <0x0 0x86d00000 0x0 0x100000>; 39 }; 40 }; 41 42 psci { 43 compatible = "arm,psci-1.0"; 44 method = "smc"; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 cpu-map { 52 cluster0 { 53 core0 { 54 cpu = <&cpu0>; 55 }; 56 57 core1 { 58 cpu = <&cpu1>; 59 }; 60 61 core2 { 62 cpu = <&cpu2>; 63 }; 64 65 core3 { 66 cpu = <&cpu3>; 67 }; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x0>; 75 enable-method = "psci"; 76 clock-frequency = <80000000>; 77 next-level-cache = <&l2>; 78 }; 79 80 cpu1: cpu@1 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 reg = <0x1>; 84 enable-method = "psci"; 85 clock-frequency = <80000000>; 86 next-level-cache = <&l2>; 87 }; 88 89 cpu2: cpu@2 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53"; 92 reg = <0x2>; 93 enable-method = "psci"; 94 clock-frequency = <80000000>; 95 next-level-cache = <&l2>; 96 }; 97 98 cpu3: cpu@3 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a53"; 101 reg = <0x3>; 102 enable-method = "psci"; 103 clock-frequency = <80000000>; 104 next-level-cache = <&l2>; 105 }; 106 107 l2: l2-cache { 108 compatible = "cache"; 109 cache-size = <0x80000>; 110 cache-line-size = <64>; 111 cache-level = <2>; 112 cache-unified; 113 }; 114 }; 115 116 timer { 117 compatible = "arm,armv8-timer"; 118 interrupt-parent = <&gic>; 119 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 120 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 121 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 122 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 123 }; 124 125 soc { 126 compatible = "simple-bus"; 127 #address-cells = <2>; 128 #size-cells = <2>; 129 ranges; 130 131 gic: interrupt-controller@9000000 { 132 compatible = "arm,gic-v3"; 133 interrupt-controller; 134 #interrupt-cells = <3>; 135 #address-cells = <1>; 136 #size-cells = <1>; 137 reg = <0x0 0x09000000 0x0 0x20000>, 138 <0x0 0x09080000 0x0 0x80000>, 139 <0x0 0x09400000 0x0 0x2000>, 140 <0x0 0x09500000 0x0 0x2000>, 141 <0x0 0x09600000 0x0 0x20000>; 142 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 143 }; 144 145 uart1: serial@1fbf0000 { 146 compatible = "ns16550"; 147 reg = <0x0 0x1fbf0000 0x0 0x30>; 148 reg-io-width = <4>; 149 reg-shift = <2>; 150 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 151 clock-frequency = <1843200>; 152 }; 153 }; 154}; 155