1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Andreas Färber 4 */ 5 6#include <dt-bindings/clock/actions,s900-cmu.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/ { 10 compatible = "actions,s900"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <2>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a53", "arm,armv8"; 22 reg = <0x0 0x0>; 23 enable-method = "psci"; 24 }; 25 26 cpu1: cpu@1 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a53", "arm,armv8"; 29 reg = <0x0 0x1>; 30 enable-method = "psci"; 31 }; 32 33 cpu2: cpu@2 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53", "arm,armv8"; 36 reg = <0x0 0x2>; 37 enable-method = "psci"; 38 }; 39 40 cpu3: cpu@3 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 reg = <0x0 0x3>; 44 enable-method = "psci"; 45 }; 46 }; 47 48 reserved-memory { 49 #address-cells = <2>; 50 #size-cells = <2>; 51 ranges; 52 53 secmon@1f000000 { 54 reg = <0x0 0x1f000000 0x0 0x1000000>; 55 no-map; 56 }; 57 }; 58 59 psci { 60 compatible = "arm,psci-0.2"; 61 method = "smc"; 62 }; 63 64 arm-pmu { 65 compatible = "arm,cortex-a53-pmu"; 66 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 70 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 71 }; 72 73 timer { 74 compatible = "arm,armv8-timer"; 75 interrupts = <GIC_PPI 13 76 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 77 <GIC_PPI 14 78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 79 <GIC_PPI 11 80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 81 <GIC_PPI 10 82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 83 }; 84 85 hosc: hosc { 86 compatible = "fixed-clock"; 87 clock-frequency = <24000000>; 88 #clock-cells = <0>; 89 }; 90 91 losc: losc { 92 compatible = "fixed-clock"; 93 clock-frequency = <32768>; 94 #clock-cells = <0>; 95 }; 96 97 diff24M: diff24M { 98 compatible = "fixed-clock"; 99 clock-frequency = <24000000>; 100 #clock-cells = <0>; 101 }; 102 103 soc { 104 compatible = "simple-bus"; 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges; 108 109 gic: interrupt-controller@e00f1000 { 110 compatible = "arm,gic-400"; 111 reg = <0x0 0xe00f1000 0x0 0x1000>, 112 <0x0 0xe00f2000 0x0 0x2000>, 113 <0x0 0xe00f4000 0x0 0x2000>, 114 <0x0 0xe00f6000 0x0 0x2000>; 115 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 116 interrupt-controller; 117 #interrupt-cells = <3>; 118 }; 119 120 uart0: serial@e0120000 { 121 compatible = "actions,s900-uart", "actions,owl-uart"; 122 reg = <0x0 0xe0120000 0x0 0x2000>; 123 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 124 status = "disabled"; 125 }; 126 127 uart1: serial@e0122000 { 128 compatible = "actions,s900-uart", "actions,owl-uart"; 129 reg = <0x0 0xe0122000 0x0 0x2000>; 130 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 131 status = "disabled"; 132 }; 133 134 uart2: serial@e0124000 { 135 compatible = "actions,s900-uart", "actions,owl-uart"; 136 reg = <0x0 0xe0124000 0x0 0x2000>; 137 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 138 status = "disabled"; 139 }; 140 141 uart3: serial@e0126000 { 142 compatible = "actions,s900-uart", "actions,owl-uart"; 143 reg = <0x0 0xe0126000 0x0 0x2000>; 144 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 145 status = "disabled"; 146 }; 147 148 uart4: serial@e0128000 { 149 compatible = "actions,s900-uart", "actions,owl-uart"; 150 reg = <0x0 0xe0128000 0x0 0x2000>; 151 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 152 status = "disabled"; 153 }; 154 155 uart5: serial@e012a000 { 156 compatible = "actions,s900-uart", "actions,owl-uart"; 157 reg = <0x0 0xe012a000 0x0 0x2000>; 158 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 159 status = "disabled"; 160 }; 161 162 uart6: serial@e012c000 { 163 compatible = "actions,s900-uart", "actions,owl-uart"; 164 reg = <0x0 0xe012c000 0x0 0x2000>; 165 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 166 status = "disabled"; 167 }; 168 169 cmu: clock-controller@e0160000 { 170 compatible = "actions,s900-cmu"; 171 reg = <0x0 0xe0160000 0x0 0x1000>; 172 clocks = <&hosc>, <&losc>; 173 #clock-cells = <1>; 174 }; 175 176 timer: timer@e0228000 { 177 compatible = "actions,s900-timer"; 178 reg = <0x0 0xe0228000 0x0 0x8000>; 179 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 180 interrupt-names = "timer1"; 181 }; 182 }; 183}; 184