1 /* 2 * arch/arm/plat-orion/time.c 3 * 4 * Marvell Orion SoC timer handling. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 * 10 * Timer 0 is used as free-running clocksource, while timer 1 is 11 * used as clock_event_device. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/timer.h> 16 #include <linux/clockchips.h> 17 #include <linux/interrupt.h> 18 #include <linux/irq.h> 19 #include <linux/sched_clock.h> 20 #include <plat/time.h> 21 22 /* 23 * MBus bridge block registers. 24 */ 25 #define BRIDGE_CAUSE_OFF 0x0110 26 #define BRIDGE_MASK_OFF 0x0114 27 #define BRIDGE_INT_TIMER0 0x0002 28 #define BRIDGE_INT_TIMER1 0x0004 29 30 31 /* 32 * Timer block registers. 33 */ 34 #define TIMER_CTRL_OFF 0x0000 35 #define TIMER0_EN 0x0001 36 #define TIMER0_RELOAD_EN 0x0002 37 #define TIMER1_EN 0x0004 38 #define TIMER1_RELOAD_EN 0x0008 39 #define TIMER0_RELOAD_OFF 0x0010 40 #define TIMER0_VAL_OFF 0x0014 41 #define TIMER1_RELOAD_OFF 0x0018 42 #define TIMER1_VAL_OFF 0x001c 43 44 45 /* 46 * SoC-specific data. 47 */ 48 static void __iomem *bridge_base; 49 static u32 bridge_timer1_clr_mask; 50 static void __iomem *timer_base; 51 52 53 /* 54 * Number of timer ticks per jiffy. 55 */ 56 static u32 ticks_per_jiffy; 57 58 59 /* 60 * Orion's sched_clock implementation. It has a resolution of 61 * at least 7.5ns (133MHz TCLK). 62 */ 63 64 static u64 notrace orion_read_sched_clock(void) 65 { 66 return ~readl(timer_base + TIMER0_VAL_OFF); 67 } 68 69 /* 70 * Clockevent handling. 71 */ 72 static int 73 orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) 74 { 75 unsigned long flags; 76 u32 u; 77 78 if (delta == 0) 79 return -ETIME; 80 81 local_irq_save(flags); 82 83 /* 84 * Clear and enable clockevent timer interrupt. 85 */ 86 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); 87 88 u = readl(bridge_base + BRIDGE_MASK_OFF); 89 u |= BRIDGE_INT_TIMER1; 90 writel(u, bridge_base + BRIDGE_MASK_OFF); 91 92 /* 93 * Setup new clockevent timer value. 94 */ 95 writel(delta, timer_base + TIMER1_VAL_OFF); 96 97 /* 98 * Enable the timer. 99 */ 100 u = readl(timer_base + TIMER_CTRL_OFF); 101 u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN; 102 writel(u, timer_base + TIMER_CTRL_OFF); 103 104 local_irq_restore(flags); 105 106 return 0; 107 } 108 109 static int orion_clkevt_shutdown(struct clock_event_device *evt) 110 { 111 unsigned long flags; 112 u32 u; 113 114 local_irq_save(flags); 115 116 /* Disable timer */ 117 u = readl(timer_base + TIMER_CTRL_OFF); 118 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF); 119 120 /* Disable timer interrupt */ 121 u = readl(bridge_base + BRIDGE_MASK_OFF); 122 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); 123 124 /* ACK pending timer interrupt */ 125 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); 126 127 local_irq_restore(flags); 128 129 return 0; 130 } 131 132 static int orion_clkevt_set_periodic(struct clock_event_device *evt) 133 { 134 unsigned long flags; 135 u32 u; 136 137 local_irq_save(flags); 138 139 /* Setup timer to fire at 1/HZ intervals */ 140 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); 141 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); 142 143 /* Enable timer interrupt */ 144 u = readl(bridge_base + BRIDGE_MASK_OFF); 145 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); 146 147 /* Enable timer */ 148 u = readl(timer_base + TIMER_CTRL_OFF); 149 writel(u | TIMER1_EN | TIMER1_RELOAD_EN, timer_base + TIMER_CTRL_OFF); 150 151 local_irq_restore(flags); 152 153 return 0; 154 } 155 156 static struct clock_event_device orion_clkevt = { 157 .name = "orion_tick", 158 .features = CLOCK_EVT_FEAT_ONESHOT | 159 CLOCK_EVT_FEAT_PERIODIC, 160 .rating = 300, 161 .set_next_event = orion_clkevt_next_event, 162 .set_state_shutdown = orion_clkevt_shutdown, 163 .set_state_periodic = orion_clkevt_set_periodic, 164 .set_state_oneshot = orion_clkevt_shutdown, 165 .tick_resume = orion_clkevt_shutdown, 166 }; 167 168 static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) 169 { 170 /* 171 * ACK timer interrupt and call event handler. 172 */ 173 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); 174 orion_clkevt.event_handler(&orion_clkevt); 175 176 return IRQ_HANDLED; 177 } 178 179 static struct irqaction orion_timer_irq = { 180 .name = "orion_tick", 181 .flags = IRQF_TIMER, 182 .handler = orion_timer_interrupt 183 }; 184 185 void __init 186 orion_time_set_base(void __iomem *_timer_base) 187 { 188 timer_base = _timer_base; 189 } 190 191 void __init 192 orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask, 193 unsigned int irq, unsigned int tclk) 194 { 195 u32 u; 196 197 /* 198 * Set SoC-specific data. 199 */ 200 bridge_base = _bridge_base; 201 bridge_timer1_clr_mask = _bridge_timer1_clr_mask; 202 203 ticks_per_jiffy = (tclk + HZ/2) / HZ; 204 205 /* 206 * Set scale and timer for sched_clock. 207 */ 208 sched_clock_register(orion_read_sched_clock, 32, tclk); 209 210 /* 211 * Setup free-running clocksource timer (interrupts 212 * disabled). 213 */ 214 writel(0xffffffff, timer_base + TIMER0_VAL_OFF); 215 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); 216 u = readl(bridge_base + BRIDGE_MASK_OFF); 217 writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF); 218 u = readl(timer_base + TIMER_CTRL_OFF); 219 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF); 220 clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource", 221 tclk, 300, 32, clocksource_mmio_readl_down); 222 223 /* 224 * Setup clockevent timer (interrupt-driven). 225 */ 226 setup_irq(irq, &orion_timer_irq); 227 orion_clkevt.cpumask = cpumask_of(0); 228 clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe); 229 } 230