1 /* 2 * arch/arm/plat-orion/gpio.c 3 * 4 * Marvell Orion SoC GPIO handling. 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/bitops.h> 17 #include <linux/io.h> 18 #include <linux/gpio.h> 19 #include <linux/leds.h> 20 21 /* 22 * GPIO unit register offsets. 23 */ 24 #define GPIO_OUT_OFF 0x0000 25 #define GPIO_IO_CONF_OFF 0x0004 26 #define GPIO_BLINK_EN_OFF 0x0008 27 #define GPIO_IN_POL_OFF 0x000c 28 #define GPIO_DATA_IN_OFF 0x0010 29 #define GPIO_EDGE_CAUSE_OFF 0x0014 30 #define GPIO_EDGE_MASK_OFF 0x0018 31 #define GPIO_LEVEL_MASK_OFF 0x001c 32 33 struct orion_gpio_chip { 34 struct gpio_chip chip; 35 spinlock_t lock; 36 void __iomem *base; 37 unsigned long valid_input; 38 unsigned long valid_output; 39 int mask_offset; 40 int secondary_irq_base; 41 }; 42 43 static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip) 44 { 45 return ochip->base + GPIO_OUT_OFF; 46 } 47 48 static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip) 49 { 50 return ochip->base + GPIO_IO_CONF_OFF; 51 } 52 53 static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip) 54 { 55 return ochip->base + GPIO_BLINK_EN_OFF; 56 } 57 58 static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip) 59 { 60 return ochip->base + GPIO_IN_POL_OFF; 61 } 62 63 static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip) 64 { 65 return ochip->base + GPIO_DATA_IN_OFF; 66 } 67 68 static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip) 69 { 70 return ochip->base + GPIO_EDGE_CAUSE_OFF; 71 } 72 73 static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip) 74 { 75 return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF; 76 } 77 78 static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip) 79 { 80 return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF; 81 } 82 83 84 static struct orion_gpio_chip orion_gpio_chips[2]; 85 static int orion_gpio_chip_count; 86 87 static inline void 88 __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input) 89 { 90 u32 u; 91 92 u = readl(GPIO_IO_CONF(ochip)); 93 if (input) 94 u |= 1 << pin; 95 else 96 u &= ~(1 << pin); 97 writel(u, GPIO_IO_CONF(ochip)); 98 } 99 100 static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high) 101 { 102 u32 u; 103 104 u = readl(GPIO_OUT(ochip)); 105 if (high) 106 u |= 1 << pin; 107 else 108 u &= ~(1 << pin); 109 writel(u, GPIO_OUT(ochip)); 110 } 111 112 static inline void 113 __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink) 114 { 115 u32 u; 116 117 u = readl(GPIO_BLINK_EN(ochip)); 118 if (blink) 119 u |= 1 << pin; 120 else 121 u &= ~(1 << pin); 122 writel(u, GPIO_BLINK_EN(ochip)); 123 } 124 125 static inline int 126 orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode) 127 { 128 if (pin >= ochip->chip.ngpio) 129 goto err_out; 130 131 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input)) 132 goto err_out; 133 134 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output)) 135 goto err_out; 136 137 return 1; 138 139 err_out: 140 pr_debug("%s: invalid GPIO %d\n", __func__, pin); 141 return false; 142 } 143 144 /* 145 * GENERIC_GPIO primitives. 146 */ 147 static int orion_gpio_request(struct gpio_chip *chip, unsigned pin) 148 { 149 struct orion_gpio_chip *ochip = 150 container_of(chip, struct orion_gpio_chip, chip); 151 152 if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) || 153 orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) 154 return 0; 155 156 return -EINVAL; 157 } 158 159 static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 160 { 161 struct orion_gpio_chip *ochip = 162 container_of(chip, struct orion_gpio_chip, chip); 163 unsigned long flags; 164 165 if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK)) 166 return -EINVAL; 167 168 spin_lock_irqsave(&ochip->lock, flags); 169 __set_direction(ochip, pin, 1); 170 spin_unlock_irqrestore(&ochip->lock, flags); 171 172 return 0; 173 } 174 175 static int orion_gpio_get(struct gpio_chip *chip, unsigned pin) 176 { 177 struct orion_gpio_chip *ochip = 178 container_of(chip, struct orion_gpio_chip, chip); 179 int val; 180 181 if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) { 182 val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip)); 183 } else { 184 val = readl(GPIO_OUT(ochip)); 185 } 186 187 return (val >> pin) & 1; 188 } 189 190 static int 191 orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value) 192 { 193 struct orion_gpio_chip *ochip = 194 container_of(chip, struct orion_gpio_chip, chip); 195 unsigned long flags; 196 197 if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) 198 return -EINVAL; 199 200 spin_lock_irqsave(&ochip->lock, flags); 201 __set_blinking(ochip, pin, 0); 202 __set_level(ochip, pin, value); 203 __set_direction(ochip, pin, 0); 204 spin_unlock_irqrestore(&ochip->lock, flags); 205 206 return 0; 207 } 208 209 static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value) 210 { 211 struct orion_gpio_chip *ochip = 212 container_of(chip, struct orion_gpio_chip, chip); 213 unsigned long flags; 214 215 spin_lock_irqsave(&ochip->lock, flags); 216 __set_level(ochip, pin, value); 217 spin_unlock_irqrestore(&ochip->lock, flags); 218 } 219 220 static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin) 221 { 222 struct orion_gpio_chip *ochip = 223 container_of(chip, struct orion_gpio_chip, chip); 224 225 return ochip->secondary_irq_base + pin; 226 } 227 228 229 /* 230 * Orion-specific GPIO API extensions. 231 */ 232 static struct orion_gpio_chip *orion_gpio_chip_find(int pin) 233 { 234 int i; 235 236 for (i = 0; i < orion_gpio_chip_count; i++) { 237 struct orion_gpio_chip *ochip = orion_gpio_chips + i; 238 struct gpio_chip *chip = &ochip->chip; 239 240 if (pin >= chip->base && pin < chip->base + chip->ngpio) 241 return ochip; 242 } 243 244 return NULL; 245 } 246 247 void __init orion_gpio_set_unused(unsigned pin) 248 { 249 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); 250 251 if (ochip == NULL) 252 return; 253 254 pin -= ochip->chip.base; 255 256 /* Configure as output, drive low. */ 257 __set_level(ochip, pin, 0); 258 __set_direction(ochip, pin, 0); 259 } 260 261 void __init orion_gpio_set_valid(unsigned pin, int mode) 262 { 263 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); 264 265 if (ochip == NULL) 266 return; 267 268 pin -= ochip->chip.base; 269 270 if (mode == 1) 271 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK; 272 273 if (mode & GPIO_INPUT_OK) 274 __set_bit(pin, &ochip->valid_input); 275 else 276 __clear_bit(pin, &ochip->valid_input); 277 278 if (mode & GPIO_OUTPUT_OK) 279 __set_bit(pin, &ochip->valid_output); 280 else 281 __clear_bit(pin, &ochip->valid_output); 282 } 283 284 void orion_gpio_set_blink(unsigned pin, int blink) 285 { 286 struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); 287 unsigned long flags; 288 289 if (ochip == NULL) 290 return; 291 292 spin_lock_irqsave(&ochip->lock, flags); 293 __set_level(ochip, pin & 31, 0); 294 __set_blinking(ochip, pin & 31, blink); 295 spin_unlock_irqrestore(&ochip->lock, flags); 296 } 297 EXPORT_SYMBOL(orion_gpio_set_blink); 298 299 #define ORION_BLINK_HALF_PERIOD 100 /* ms */ 300 301 int orion_gpio_led_blink_set(unsigned gpio, int state, 302 unsigned long *delay_on, unsigned long *delay_off) 303 { 304 305 if (delay_on && delay_off && !*delay_on && !*delay_off) 306 *delay_on = *delay_off = ORION_BLINK_HALF_PERIOD; 307 308 switch (state) { 309 case GPIO_LED_NO_BLINK_LOW: 310 case GPIO_LED_NO_BLINK_HIGH: 311 orion_gpio_set_blink(gpio, 0); 312 gpio_set_value(gpio, state); 313 break; 314 case GPIO_LED_BLINK: 315 orion_gpio_set_blink(gpio, 1); 316 } 317 return 0; 318 } 319 EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set); 320 321 322 /***************************************************************************** 323 * Orion GPIO IRQ 324 * 325 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 326 * value of the line or the opposite value. 327 * 328 * Level IRQ handlers: DATA_IN is used directly as cause register. 329 * Interrupt are masked by LEVEL_MASK registers. 330 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 331 * Interrupt are masked by EDGE_MASK registers. 332 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 333 * the polarity to catch the next line transaction. 334 * This is a race condition that might not perfectly 335 * work on some use cases. 336 * 337 * Every eight GPIO lines are grouped (OR'ed) before going up to main 338 * cause register. 339 * 340 * EDGE cause mask 341 * data-in /--------| |-----| |----\ 342 * -----| |----- ---- to main cause reg 343 * X \----------------| |----/ 344 * polarity LEVEL mask 345 * 346 ****************************************************************************/ 347 348 static int gpio_irq_set_type(struct irq_data *d, u32 type) 349 { 350 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 351 struct irq_chip_type *ct = irq_data_get_chip_type(d); 352 struct orion_gpio_chip *ochip = gc->private; 353 int pin; 354 u32 u; 355 356 pin = d->irq - gc->irq_base; 357 358 u = readl(GPIO_IO_CONF(ochip)) & (1 << pin); 359 if (!u) { 360 printk(KERN_ERR "orion gpio_irq_set_type failed " 361 "(irq %d, pin %d).\n", d->irq, pin); 362 return -EINVAL; 363 } 364 365 type &= IRQ_TYPE_SENSE_MASK; 366 if (type == IRQ_TYPE_NONE) 367 return -EINVAL; 368 369 /* Check if we need to change chip and handler */ 370 if (!(ct->type & type)) 371 if (irq_setup_alt_chip(d, type)) 372 return -EINVAL; 373 374 /* 375 * Configure interrupt polarity. 376 */ 377 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) { 378 u = readl(GPIO_IN_POL(ochip)); 379 u &= ~(1 << pin); 380 writel(u, GPIO_IN_POL(ochip)); 381 } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) { 382 u = readl(GPIO_IN_POL(ochip)); 383 u |= 1 << pin; 384 writel(u, GPIO_IN_POL(ochip)); 385 } else if (type == IRQ_TYPE_EDGE_BOTH) { 386 u32 v; 387 388 v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip)); 389 390 /* 391 * set initial polarity based on current input level 392 */ 393 u = readl(GPIO_IN_POL(ochip)); 394 if (v & (1 << pin)) 395 u |= 1 << pin; /* falling */ 396 else 397 u &= ~(1 << pin); /* rising */ 398 writel(u, GPIO_IN_POL(ochip)); 399 } 400 401 return 0; 402 } 403 404 void __init orion_gpio_init(int gpio_base, int ngpio, 405 u32 base, int mask_offset, int secondary_irq_base) 406 { 407 struct orion_gpio_chip *ochip; 408 struct irq_chip_generic *gc; 409 struct irq_chip_type *ct; 410 char gc_label[16]; 411 412 if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips)) 413 return; 414 415 snprintf(gc_label, sizeof(gc_label), "orion_gpio%d", 416 orion_gpio_chip_count); 417 418 ochip = orion_gpio_chips + orion_gpio_chip_count; 419 ochip->chip.label = kstrdup(gc_label, GFP_KERNEL); 420 ochip->chip.request = orion_gpio_request; 421 ochip->chip.direction_input = orion_gpio_direction_input; 422 ochip->chip.get = orion_gpio_get; 423 ochip->chip.direction_output = orion_gpio_direction_output; 424 ochip->chip.set = orion_gpio_set; 425 ochip->chip.to_irq = orion_gpio_to_irq; 426 ochip->chip.base = gpio_base; 427 ochip->chip.ngpio = ngpio; 428 ochip->chip.can_sleep = 0; 429 spin_lock_init(&ochip->lock); 430 ochip->base = (void __iomem *)base; 431 ochip->valid_input = 0; 432 ochip->valid_output = 0; 433 ochip->mask_offset = mask_offset; 434 ochip->secondary_irq_base = secondary_irq_base; 435 436 gpiochip_add(&ochip->chip); 437 438 orion_gpio_chip_count++; 439 440 /* 441 * Mask and clear GPIO interrupts. 442 */ 443 writel(0, GPIO_EDGE_CAUSE(ochip)); 444 writel(0, GPIO_EDGE_MASK(ochip)); 445 writel(0, GPIO_LEVEL_MASK(ochip)); 446 447 gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base, 448 ochip->base, handle_level_irq); 449 gc->private = ochip; 450 451 ct = gc->chip_types; 452 ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF; 453 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 454 ct->chip.irq_mask = irq_gc_mask_clr_bit; 455 ct->chip.irq_unmask = irq_gc_mask_set_bit; 456 ct->chip.irq_set_type = gpio_irq_set_type; 457 458 ct++; 459 ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF; 460 ct->regs.ack = GPIO_EDGE_CAUSE_OFF; 461 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 462 ct->chip.irq_ack = irq_gc_ack_clr_bit; 463 ct->chip.irq_mask = irq_gc_mask_clr_bit; 464 ct->chip.irq_unmask = irq_gc_mask_set_bit; 465 ct->chip.irq_set_type = gpio_irq_set_type; 466 ct->handler = handle_edge_irq; 467 468 irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE, 469 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); 470 } 471 472 void orion_gpio_irq_handler(int pinoff) 473 { 474 struct orion_gpio_chip *ochip; 475 u32 cause, type; 476 int i; 477 478 ochip = orion_gpio_chip_find(pinoff); 479 if (ochip == NULL) 480 return; 481 482 cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip)); 483 cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip)); 484 485 for (i = 0; i < ochip->chip.ngpio; i++) { 486 int irq; 487 488 irq = ochip->secondary_irq_base + i; 489 490 if (!(cause & (1 << i))) 491 continue; 492 493 type = irqd_get_trigger_type(irq_get_irq_data(irq)); 494 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 495 /* Swap polarity (race with GPIO line) */ 496 u32 polarity; 497 498 polarity = readl(GPIO_IN_POL(ochip)); 499 polarity ^= 1 << i; 500 writel(polarity, GPIO_IN_POL(ochip)); 501 } 502 generic_handle_irq(irq); 503 } 504 } 505