xref: /linux/arch/arm/plat-orion/gpio.c (revision 22c55fb9eb92395d999b8404d73e58540d11bdd8) 
1 /*
2  * arch/arm/plat-orion/gpio.c
3  *
4  * Marvell Orion SoC GPIO handling.
5  *
6  * This file is licensed under the terms of the GNU General Public
7  * License version 2.  This program is licensed "as is" without any
8  * warranty of any kind, whether express or implied.
9  */
10 
11 #define DEBUG
12 
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
18 #include <linux/spinlock.h>
19 #include <linux/bitops.h>
20 #include <linux/io.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/leds.h>
24 #include <linux/of.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_address.h>
27 #include <plat/orion-gpio.h>
28 
29 /*
30  * GPIO unit register offsets.
31  */
32 #define GPIO_OUT_OFF		0x0000
33 #define GPIO_IO_CONF_OFF	0x0004
34 #define GPIO_BLINK_EN_OFF	0x0008
35 #define GPIO_IN_POL_OFF		0x000c
36 #define GPIO_DATA_IN_OFF	0x0010
37 #define GPIO_EDGE_CAUSE_OFF	0x0014
38 #define GPIO_EDGE_MASK_OFF	0x0018
39 #define GPIO_LEVEL_MASK_OFF	0x001c
40 
41 struct orion_gpio_chip {
42 	struct gpio_chip	chip;
43 	spinlock_t		lock;
44 	void __iomem		*base;
45 	unsigned long		valid_input;
46 	unsigned long		valid_output;
47 	int			mask_offset;
48 	int			secondary_irq_base;
49 	struct irq_domain       *domain;
50 };
51 
52 static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
53 {
54 	return ochip->base + GPIO_OUT_OFF;
55 }
56 
57 static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
58 {
59 	return ochip->base + GPIO_IO_CONF_OFF;
60 }
61 
62 static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
63 {
64 	return ochip->base + GPIO_BLINK_EN_OFF;
65 }
66 
67 static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
68 {
69 	return ochip->base + GPIO_IN_POL_OFF;
70 }
71 
72 static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
73 {
74 	return ochip->base + GPIO_DATA_IN_OFF;
75 }
76 
77 static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
78 {
79 	return ochip->base + GPIO_EDGE_CAUSE_OFF;
80 }
81 
82 static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
83 {
84 	return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
85 }
86 
87 static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
88 {
89 	return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
90 }
91 
92 
93 static struct orion_gpio_chip orion_gpio_chips[2];
94 static int orion_gpio_chip_count;
95 
96 static inline void
97 __set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
98 {
99 	u32 u;
100 
101 	u = readl(GPIO_IO_CONF(ochip));
102 	if (input)
103 		u |= 1 << pin;
104 	else
105 		u &= ~(1 << pin);
106 	writel(u, GPIO_IO_CONF(ochip));
107 }
108 
109 static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
110 {
111 	u32 u;
112 
113 	u = readl(GPIO_OUT(ochip));
114 	if (high)
115 		u |= 1 << pin;
116 	else
117 		u &= ~(1 << pin);
118 	writel(u, GPIO_OUT(ochip));
119 }
120 
121 static inline void
122 __set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
123 {
124 	u32 u;
125 
126 	u = readl(GPIO_BLINK_EN(ochip));
127 	if (blink)
128 		u |= 1 << pin;
129 	else
130 		u &= ~(1 << pin);
131 	writel(u, GPIO_BLINK_EN(ochip));
132 }
133 
134 static inline int
135 orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
136 {
137 	if (pin >= ochip->chip.ngpio)
138 		goto err_out;
139 
140 	if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
141 		goto err_out;
142 
143 	if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
144 		goto err_out;
145 
146 	return 1;
147 
148 err_out:
149 	pr_debug("%s: invalid GPIO %d\n", __func__, pin);
150 	return false;
151 }
152 
153 /*
154  * GPIO primitives.
155  */
156 static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
157 {
158 	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
159 
160 	if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
161 	    orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
162 		return 0;
163 
164 	return -EINVAL;
165 }
166 
167 static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
168 {
169 	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
170 	unsigned long flags;
171 
172 	if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
173 		return -EINVAL;
174 
175 	spin_lock_irqsave(&ochip->lock, flags);
176 	__set_direction(ochip, pin, 1);
177 	spin_unlock_irqrestore(&ochip->lock, flags);
178 
179 	return 0;
180 }
181 
182 static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
183 {
184 	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
185 	int val;
186 
187 	if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
188 		val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
189 	} else {
190 		val = readl(GPIO_OUT(ochip));
191 	}
192 
193 	return (val >> pin) & 1;
194 }
195 
196 static int
197 orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
198 {
199 	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
200 	unsigned long flags;
201 
202 	if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
203 		return -EINVAL;
204 
205 	spin_lock_irqsave(&ochip->lock, flags);
206 	__set_blinking(ochip, pin, 0);
207 	__set_level(ochip, pin, value);
208 	__set_direction(ochip, pin, 0);
209 	spin_unlock_irqrestore(&ochip->lock, flags);
210 
211 	return 0;
212 }
213 
214 static int orion_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
215 {
216 	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
217 	unsigned long flags;
218 
219 	spin_lock_irqsave(&ochip->lock, flags);
220 	__set_level(ochip, pin, value);
221 	spin_unlock_irqrestore(&ochip->lock, flags);
222 
223 	return 0;
224 }
225 
226 static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
227 {
228 	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
229 
230 	return irq_create_mapping(ochip->domain,
231 				  ochip->secondary_irq_base + pin);
232 }
233 
234 /*
235  * Orion-specific GPIO API extensions.
236  */
237 static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
238 {
239 	int i;
240 
241 	for (i = 0; i < orion_gpio_chip_count; i++) {
242 		struct orion_gpio_chip *ochip = orion_gpio_chips + i;
243 		struct gpio_chip *chip = &ochip->chip;
244 
245 		if (pin >= chip->base && pin < chip->base + chip->ngpio)
246 			return ochip;
247 	}
248 
249 	return NULL;
250 }
251 
252 void __init orion_gpio_set_unused(unsigned pin)
253 {
254 	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
255 
256 	if (ochip == NULL)
257 		return;
258 
259 	pin -= ochip->chip.base;
260 
261 	/* Configure as output, drive low. */
262 	__set_level(ochip, pin, 0);
263 	__set_direction(ochip, pin, 0);
264 }
265 
266 void __init orion_gpio_set_valid(unsigned pin, int mode)
267 {
268 	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
269 
270 	if (ochip == NULL)
271 		return;
272 
273 	pin -= ochip->chip.base;
274 
275 	if (mode == 1)
276 		mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
277 
278 	if (mode & GPIO_INPUT_OK)
279 		__set_bit(pin, &ochip->valid_input);
280 	else
281 		__clear_bit(pin, &ochip->valid_input);
282 
283 	if (mode & GPIO_OUTPUT_OK)
284 		__set_bit(pin, &ochip->valid_output);
285 	else
286 		__clear_bit(pin, &ochip->valid_output);
287 }
288 
289 void orion_gpio_set_blink(unsigned pin, int blink)
290 {
291 	struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
292 	unsigned long flags;
293 
294 	if (ochip == NULL)
295 		return;
296 
297 	spin_lock_irqsave(&ochip->lock, flags);
298 	__set_level(ochip, pin & 31, 0);
299 	__set_blinking(ochip, pin & 31, blink);
300 	spin_unlock_irqrestore(&ochip->lock, flags);
301 }
302 EXPORT_SYMBOL(orion_gpio_set_blink);
303 
304 #define ORION_BLINK_HALF_PERIOD 100 /* ms */
305 
306 int orion_gpio_led_blink_set(struct gpio_desc *desc, int state,
307 	unsigned long *delay_on, unsigned long *delay_off)
308 {
309 	unsigned gpio = desc_to_gpio(desc);
310 
311 	if (delay_on && delay_off && !*delay_on && !*delay_off)
312 		*delay_on = *delay_off = ORION_BLINK_HALF_PERIOD;
313 
314 	switch (state) {
315 	case GPIO_LED_NO_BLINK_LOW:
316 	case GPIO_LED_NO_BLINK_HIGH:
317 		orion_gpio_set_blink(gpio, 0);
318 		gpiod_set_raw_value(desc, state);
319 		break;
320 	case GPIO_LED_BLINK:
321 		orion_gpio_set_blink(gpio, 1);
322 	}
323 	return 0;
324 }
325 EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set);
326 
327 
328 /*****************************************************************************
329  * Orion GPIO IRQ
330  *
331  * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
332  * value of the line or the opposite value.
333  *
334  * Level IRQ handlers: DATA_IN is used directly as cause register.
335  *                     Interrupt are masked by LEVEL_MASK registers.
336  * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
337  *                     Interrupt are masked by EDGE_MASK registers.
338  * Both-edge handlers: Similar to regular Edge handlers, but also swaps
339  *                     the polarity to catch the next line transaction.
340  *                     This is a race condition that might not perfectly
341  *                     work on some use cases.
342  *
343  * Every eight GPIO lines are grouped (OR'ed) before going up to main
344  * cause register.
345  *
346  *                    EDGE  cause    mask
347  *        data-in   /--------| |-----| |----\
348  *     -----| |-----                         ---- to main cause reg
349  *           X      \----------------| |----/
350  *        polarity    LEVEL          mask
351  *
352  ****************************************************************************/
353 
354 static int gpio_irq_set_type(struct irq_data *d, u32 type)
355 {
356 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
357 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
358 	struct orion_gpio_chip *ochip = gc->private;
359 	int pin;
360 	u32 u;
361 
362 	pin = d->hwirq - ochip->secondary_irq_base;
363 
364 	u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
365 	if (!u) {
366 		return -EINVAL;
367 	}
368 
369 	type &= IRQ_TYPE_SENSE_MASK;
370 	if (type == IRQ_TYPE_NONE)
371 		return -EINVAL;
372 
373 	/* Check if we need to change chip and handler */
374 	if (!(ct->type & type))
375 		if (irq_setup_alt_chip(d, type))
376 			return -EINVAL;
377 
378 	/*
379 	 * Configure interrupt polarity.
380 	 */
381 	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
382 		u = readl(GPIO_IN_POL(ochip));
383 		u &= ~(1 << pin);
384 		writel(u, GPIO_IN_POL(ochip));
385 	} else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
386 		u = readl(GPIO_IN_POL(ochip));
387 		u |= 1 << pin;
388 		writel(u, GPIO_IN_POL(ochip));
389 	} else if (type == IRQ_TYPE_EDGE_BOTH) {
390 		u32 v;
391 
392 		v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
393 
394 		/*
395 		 * set initial polarity based on current input level
396 		 */
397 		u = readl(GPIO_IN_POL(ochip));
398 		if (v & (1 << pin))
399 			u |= 1 << pin;		/* falling */
400 		else
401 			u &= ~(1 << pin);	/* rising */
402 		writel(u, GPIO_IN_POL(ochip));
403 	}
404 	return 0;
405 }
406 
407 static void gpio_irq_handler(struct irq_desc *desc)
408 {
409 	struct orion_gpio_chip *ochip = irq_desc_get_handler_data(desc);
410 	u32 cause, type;
411 	int i;
412 
413 	if (ochip == NULL)
414 		return;
415 
416 	cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
417 	cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
418 
419 	for (i = 0; i < ochip->chip.ngpio; i++) {
420 		int irq;
421 
422 		irq = ochip->secondary_irq_base + i;
423 
424 		if (!(cause & (1 << i)))
425 			continue;
426 
427 		type = irq_get_trigger_type(irq);
428 		if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
429 			/* Swap polarity (race with GPIO line) */
430 			u32 polarity;
431 
432 			polarity = readl(GPIO_IN_POL(ochip));
433 			polarity ^= 1 << i;
434 			writel(polarity, GPIO_IN_POL(ochip));
435 		}
436 		generic_handle_irq(irq);
437 	}
438 }
439 
440 #ifdef CONFIG_DEBUG_FS
441 #include <linux/seq_file.h>
442 
443 static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
444 {
445 
446 	struct orion_gpio_chip *ochip = gpiochip_get_data(chip);
447 	u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
448 	const char *label;
449 	int i;
450 
451 	out	= readl_relaxed(GPIO_OUT(ochip));
452 	io_conf	= readl_relaxed(GPIO_IO_CONF(ochip));
453 	blink	= readl_relaxed(GPIO_BLINK_EN(ochip));
454 	in_pol	= readl_relaxed(GPIO_IN_POL(ochip));
455 	data_in	= readl_relaxed(GPIO_DATA_IN(ochip));
456 	cause	= readl_relaxed(GPIO_EDGE_CAUSE(ochip));
457 	edg_msk	= readl_relaxed(GPIO_EDGE_MASK(ochip));
458 	lvl_msk	= readl_relaxed(GPIO_LEVEL_MASK(ochip));
459 
460 	for_each_requested_gpio(chip, i, label) {
461 		u32 msk;
462 		bool is_out;
463 
464 		msk = 1 << i;
465 		is_out = !(io_conf & msk);
466 
467 		seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
468 
469 		if (is_out) {
470 			seq_printf(s, " out %s %s\n",
471 				   str_hi_lo(out & msk),
472 				   blink & msk ? "(blink )" : "");
473 			continue;
474 		}
475 
476 		seq_printf(s, " in  %s (act %s) - IRQ",
477 			   str_hi_lo((data_in ^ in_pol) & msk),
478 			   str_lo_hi(in_pol & msk));
479 		if (!((edg_msk | lvl_msk) & msk)) {
480 			seq_puts(s, " disabled\n");
481 			continue;
482 		}
483 		if (edg_msk & msk)
484 			seq_puts(s, " edge ");
485 		if (lvl_msk & msk)
486 			seq_puts(s, " level");
487 		seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear  ");
488 	}
489 }
490 #else
491 #define orion_gpio_dbg_show NULL
492 #endif
493 
494 static void orion_gpio_unmask_irq(struct irq_data *d)
495 {
496 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
497 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
498 	u32 reg_val;
499 	u32 mask = d->mask;
500 
501 	guard(raw_spinlock)(&gc->lock);
502 	reg_val = irq_reg_readl(gc, ct->regs.mask);
503 	reg_val |= mask;
504 	irq_reg_writel(gc, reg_val, ct->regs.mask);
505 }
506 
507 static void orion_gpio_mask_irq(struct irq_data *d)
508 {
509 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
510 	struct irq_chip_type *ct = irq_data_get_chip_type(d);
511 	u32 mask = d->mask;
512 	u32 reg_val;
513 
514 	guard(raw_spinlock)(&gc->lock);
515 	reg_val = irq_reg_readl(gc, ct->regs.mask);
516 	reg_val &= ~mask;
517 	irq_reg_writel(gc, reg_val, ct->regs.mask);
518 }
519 
520 void __init orion_gpio_init(int gpio_base, int ngpio,
521 			    void __iomem *base, int mask_offset,
522 			    int secondary_irq_base,
523 			    int irqs[4])
524 {
525 	struct orion_gpio_chip *ochip;
526 	struct irq_chip_generic *gc;
527 	struct irq_chip_type *ct;
528 	char gc_label[16];
529 	int i;
530 
531 	if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
532 		return;
533 
534 	snprintf(gc_label, sizeof(gc_label), "orion_gpio%d",
535 		orion_gpio_chip_count);
536 
537 	ochip = orion_gpio_chips + orion_gpio_chip_count;
538 	ochip->chip.label = kstrdup(gc_label, GFP_KERNEL);
539 	ochip->chip.request = orion_gpio_request;
540 	ochip->chip.direction_input = orion_gpio_direction_input;
541 	ochip->chip.get = orion_gpio_get;
542 	ochip->chip.direction_output = orion_gpio_direction_output;
543 	ochip->chip.set = orion_gpio_set;
544 	ochip->chip.to_irq = orion_gpio_to_irq;
545 	ochip->chip.base = gpio_base;
546 	ochip->chip.ngpio = ngpio;
547 	ochip->chip.can_sleep = 0;
548 	ochip->chip.dbg_show = orion_gpio_dbg_show;
549 
550 	spin_lock_init(&ochip->lock);
551 	ochip->base = (void __iomem *)base;
552 	ochip->valid_input = 0;
553 	ochip->valid_output = 0;
554 	ochip->mask_offset = mask_offset;
555 	ochip->secondary_irq_base = secondary_irq_base;
556 
557 	gpiochip_add_data(&ochip->chip, ochip);
558 
559 	/*
560 	 * Mask and clear GPIO interrupts.
561 	 */
562 	writel(0, GPIO_EDGE_CAUSE(ochip));
563 	writel(0, GPIO_EDGE_MASK(ochip));
564 	writel(0, GPIO_LEVEL_MASK(ochip));
565 
566 	/* Setup the interrupt handlers. Each chip can have up to 4
567 	 * interrupt handlers, with each handler dealing with 8 GPIO
568 	 * pins. */
569 
570 	for (i = 0; i < 4; i++) {
571 		if (irqs[i]) {
572 			irq_set_chained_handler_and_data(irqs[i],
573 							 gpio_irq_handler,
574 							 ochip);
575 		}
576 	}
577 
578 	gc = irq_alloc_generic_chip("orion_gpio_irq", 2,
579 				    secondary_irq_base,
580 				    ochip->base, handle_level_irq);
581 	gc->private = ochip;
582 	ct = gc->chip_types;
583 	ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
584 	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
585 	ct->chip.irq_mask = orion_gpio_mask_irq;
586 	ct->chip.irq_unmask = orion_gpio_unmask_irq;
587 	ct->chip.irq_set_type = gpio_irq_set_type;
588 	ct->chip.name = ochip->chip.label;
589 
590 	ct++;
591 	ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
592 	ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
593 	ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
594 	ct->chip.irq_ack = irq_gc_ack_clr_bit;
595 	ct->chip.irq_mask = orion_gpio_mask_irq;
596 	ct->chip.irq_unmask = orion_gpio_unmask_irq;
597 	ct->chip.irq_set_type = gpio_irq_set_type;
598 	ct->handler = handle_edge_irq;
599 	ct->chip.name = ochip->chip.label;
600 
601 	irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
602 			       IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
603 
604 	/* Setup irq domain on top of the generic chip. */
605 	ochip->domain = irq_domain_create_legacy(NULL,
606 						 ochip->chip.ngpio,
607 						 ochip->secondary_irq_base,
608 						 ochip->secondary_irq_base,
609 						 &irq_domain_simple_ops,
610 						 ochip);
611 	if (!ochip->domain)
612 		panic("%s: couldn't allocate irq domain (DT).\n",
613 		      ochip->chip.label);
614 
615 	orion_gpio_chip_count++;
616 }
617