1 /* 2 * Just-In-Time compiler for BPF filters on 32bit ARM 3 * 4 * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; version 2 of the License. 9 */ 10 11 #ifndef PFILTER_OPCODES_ARM_H 12 #define PFILTER_OPCODES_ARM_H 13 14 #define ARM_R0 0 15 #define ARM_R1 1 16 #define ARM_R2 2 17 #define ARM_R3 3 18 #define ARM_R4 4 19 #define ARM_R5 5 20 #define ARM_R6 6 21 #define ARM_R7 7 22 #define ARM_R8 8 23 #define ARM_R9 9 24 #define ARM_R10 10 25 #define ARM_FP 11 26 #define ARM_IP 12 27 #define ARM_SP 13 28 #define ARM_LR 14 29 #define ARM_PC 15 30 31 #define ARM_COND_EQ 0x0 32 #define ARM_COND_NE 0x1 33 #define ARM_COND_CS 0x2 34 #define ARM_COND_HS ARM_COND_CS 35 #define ARM_COND_CC 0x3 36 #define ARM_COND_LO ARM_COND_CC 37 #define ARM_COND_MI 0x4 38 #define ARM_COND_PL 0x5 39 #define ARM_COND_VS 0x6 40 #define ARM_COND_VC 0x7 41 #define ARM_COND_HI 0x8 42 #define ARM_COND_LS 0x9 43 #define ARM_COND_GE 0xa 44 #define ARM_COND_LT 0xb 45 #define ARM_COND_GT 0xc 46 #define ARM_COND_LE 0xd 47 #define ARM_COND_AL 0xe 48 49 /* register shift types */ 50 #define SRTYPE_LSL 0 51 #define SRTYPE_LSR 1 52 #define SRTYPE_ASR 2 53 #define SRTYPE_ROR 3 54 55 #define ARM_INST_ADD_R 0x00800000 56 #define ARM_INST_ADD_I 0x02800000 57 58 #define ARM_INST_AND_R 0x00000000 59 #define ARM_INST_AND_I 0x02000000 60 61 #define ARM_INST_BIC_R 0x01c00000 62 #define ARM_INST_BIC_I 0x03c00000 63 64 #define ARM_INST_B 0x0a000000 65 #define ARM_INST_BX 0x012FFF10 66 #define ARM_INST_BLX_R 0x012fff30 67 68 #define ARM_INST_CMP_R 0x01500000 69 #define ARM_INST_CMP_I 0x03500000 70 71 #define ARM_INST_EOR_R 0x00200000 72 #define ARM_INST_EOR_I 0x02200000 73 74 #define ARM_INST_LDRB_I 0x05d00000 75 #define ARM_INST_LDRB_R 0x07d00000 76 #define ARM_INST_LDRH_I 0x01d000b0 77 #define ARM_INST_LDR_I 0x05900000 78 79 #define ARM_INST_LDM 0x08900000 80 81 #define ARM_INST_LSL_I 0x01a00000 82 #define ARM_INST_LSL_R 0x01a00010 83 84 #define ARM_INST_LSR_I 0x01a00020 85 #define ARM_INST_LSR_R 0x01a00030 86 87 #define ARM_INST_MOV_R 0x01a00000 88 #define ARM_INST_MOV_I 0x03a00000 89 #define ARM_INST_MOVW 0x03000000 90 #define ARM_INST_MOVT 0x03400000 91 92 #define ARM_INST_MUL 0x00000090 93 94 #define ARM_INST_POP 0x08bd0000 95 #define ARM_INST_PUSH 0x092d0000 96 97 #define ARM_INST_ORR_R 0x01800000 98 #define ARM_INST_ORR_I 0x03800000 99 100 #define ARM_INST_REV 0x06bf0f30 101 #define ARM_INST_REV16 0x06bf0fb0 102 103 #define ARM_INST_RSB_I 0x02600000 104 105 #define ARM_INST_SUB_R 0x00400000 106 #define ARM_INST_SUB_I 0x02400000 107 108 #define ARM_INST_STR_I 0x05800000 109 110 #define ARM_INST_TST_R 0x01100000 111 #define ARM_INST_TST_I 0x03100000 112 113 #define ARM_INST_UDIV 0x0730f010 114 115 #define ARM_INST_UMULL 0x00800090 116 117 /* 118 * Use a suitable undefined instruction to use for ARM/Thumb2 faulting. 119 * We need to be careful not to conflict with those used by other modules 120 * (BUG, kprobes, etc) and the register_undef_hook() system. 121 * 122 * The ARM architecture reference manual guarantees that the following 123 * instruction space will produce an undefined instruction exception on 124 * all CPUs: 125 * 126 * ARM: xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx ARMv7-AR, section A5.4 127 * Thumb: 1101 1110 xxxx xxxx ARMv7-M, section A5.2.6 128 */ 129 #define ARM_INST_UDF 0xe7fddef1 130 131 /* register */ 132 #define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm)) 133 /* immediate */ 134 #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) 135 136 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) 137 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) 138 139 #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) 140 #define ARM_AND_I(rd, rn, imm) _AL3_I(ARM_INST_AND, rd, rn, imm) 141 142 #define ARM_BIC_R(rd, rn, rm) _AL3_R(ARM_INST_BIC, rd, rn, rm) 143 #define ARM_BIC_I(rd, rn, imm) _AL3_I(ARM_INST_BIC, rd, rn, imm) 144 145 #define ARM_B(imm24) (ARM_INST_B | ((imm24) & 0xffffff)) 146 #define ARM_BX(rm) (ARM_INST_BX | (rm)) 147 #define ARM_BLX_R(rm) (ARM_INST_BLX_R | (rm)) 148 149 #define ARM_CMP_R(rn, rm) _AL3_R(ARM_INST_CMP, 0, rn, rm) 150 #define ARM_CMP_I(rn, imm) _AL3_I(ARM_INST_CMP, 0, rn, imm) 151 152 #define ARM_EOR_R(rd, rn, rm) _AL3_R(ARM_INST_EOR, rd, rn, rm) 153 #define ARM_EOR_I(rd, rn, imm) _AL3_I(ARM_INST_EOR, rd, rn, imm) 154 155 #define ARM_LDR_I(rt, rn, off) (ARM_INST_LDR_I | (rt) << 12 | (rn) << 16 \ 156 | (off)) 157 #define ARM_LDRB_I(rt, rn, off) (ARM_INST_LDRB_I | (rt) << 12 | (rn) << 16 \ 158 | (off)) 159 #define ARM_LDRB_R(rt, rn, rm) (ARM_INST_LDRB_R | (rt) << 12 | (rn) << 16 \ 160 | (rm)) 161 #define ARM_LDRH_I(rt, rn, off) (ARM_INST_LDRH_I | (rt) << 12 | (rn) << 16 \ 162 | (((off) & 0xf0) << 4) | ((off) & 0xf)) 163 164 #define ARM_LDM(rn, regs) (ARM_INST_LDM | (rn) << 16 | (regs)) 165 166 #define ARM_LSL_R(rd, rn, rm) (_AL3_R(ARM_INST_LSL, rd, 0, rn) | (rm) << 8) 167 #define ARM_LSL_I(rd, rn, imm) (_AL3_I(ARM_INST_LSL, rd, 0, rn) | (imm) << 7) 168 169 #define ARM_LSR_R(rd, rn, rm) (_AL3_R(ARM_INST_LSR, rd, 0, rn) | (rm) << 8) 170 #define ARM_LSR_I(rd, rn, imm) (_AL3_I(ARM_INST_LSR, rd, 0, rn) | (imm) << 7) 171 172 #define ARM_MOV_R(rd, rm) _AL3_R(ARM_INST_MOV, rd, 0, rm) 173 #define ARM_MOV_I(rd, imm) _AL3_I(ARM_INST_MOV, rd, 0, imm) 174 175 #define ARM_MOVW(rd, imm) \ 176 (ARM_INST_MOVW | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff)) 177 178 #define ARM_MOVT(rd, imm) \ 179 (ARM_INST_MOVT | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff)) 180 181 #define ARM_MUL(rd, rm, rn) (ARM_INST_MUL | (rd) << 16 | (rm) << 8 | (rn)) 182 183 #define ARM_POP(regs) (ARM_INST_POP | (regs)) 184 #define ARM_PUSH(regs) (ARM_INST_PUSH | (regs)) 185 186 #define ARM_ORR_R(rd, rn, rm) _AL3_R(ARM_INST_ORR, rd, rn, rm) 187 #define ARM_ORR_I(rd, rn, imm) _AL3_I(ARM_INST_ORR, rd, rn, imm) 188 #define ARM_ORR_S(rd, rn, rm, type, rs) \ 189 (ARM_ORR_R(rd, rn, rm) | (type) << 5 | (rs) << 7) 190 191 #define ARM_REV(rd, rm) (ARM_INST_REV | (rd) << 12 | (rm)) 192 #define ARM_REV16(rd, rm) (ARM_INST_REV16 | (rd) << 12 | (rm)) 193 194 #define ARM_RSB_I(rd, rn, imm) _AL3_I(ARM_INST_RSB, rd, rn, imm) 195 196 #define ARM_SUB_R(rd, rn, rm) _AL3_R(ARM_INST_SUB, rd, rn, rm) 197 #define ARM_SUB_I(rd, rn, imm) _AL3_I(ARM_INST_SUB, rd, rn, imm) 198 199 #define ARM_STR_I(rt, rn, off) (ARM_INST_STR_I | (rt) << 12 | (rn) << 16 \ 200 | (off)) 201 202 #define ARM_TST_R(rn, rm) _AL3_R(ARM_INST_TST, 0, rn, rm) 203 #define ARM_TST_I(rn, imm) _AL3_I(ARM_INST_TST, 0, rn, imm) 204 205 #define ARM_UDIV(rd, rn, rm) (ARM_INST_UDIV | (rd) << 16 | (rn) | (rm) << 8) 206 207 #define ARM_UMULL(rd_lo, rd_hi, rn, rm) (ARM_INST_UMULL | (rd_hi) << 16 \ 208 | (rd_lo) << 12 | (rm) << 8 | rn) 209 210 #endif /* PFILTER_OPCODES_ARM_H */ 211