1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Just-In-Time compiler for eBPF filters on 32bit ARM 4 * 5 * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com> 6 * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com> 7 */ 8 9 #include <linux/bpf.h> 10 #include <linux/bitops.h> 11 #include <linux/compiler.h> 12 #include <linux/errno.h> 13 #include <linux/filter.h> 14 #include <linux/netdevice.h> 15 #include <linux/string.h> 16 #include <linux/slab.h> 17 #include <linux/if_vlan.h> 18 19 #include <asm/cacheflush.h> 20 #include <asm/hwcap.h> 21 #include <asm/opcodes.h> 22 #include <asm/system_info.h> 23 24 #include "bpf_jit_32.h" 25 26 /* 27 * eBPF prog stack layout: 28 * 29 * high 30 * original ARM_SP => +-----+ 31 * | | callee saved registers 32 * +-----+ <= (BPF_FP + SCRATCH_SIZE) 33 * | ... | eBPF JIT scratch space 34 * eBPF fp register => +-----+ 35 * (BPF_FP) | ... | eBPF prog stack 36 * +-----+ 37 * |RSVD | JIT scratchpad 38 * current ARM_SP => +-----+ <= (BPF_FP - STACK_SIZE + SCRATCH_SIZE) 39 * | ... | caller-saved registers 40 * +-----+ 41 * | ... | arguments passed on stack 42 * ARM_SP during call => +-----| 43 * | | 44 * | ... | Function call stack 45 * | | 46 * +-----+ 47 * low 48 * 49 * The callee saved registers depends on whether frame pointers are enabled. 50 * With frame pointers (to be compliant with the ABI): 51 * 52 * high 53 * original ARM_SP => +--------------+ \ 54 * | pc | | 55 * current ARM_FP => +--------------+ } callee saved registers 56 * |r4-r9,fp,ip,lr| | 57 * +--------------+ / 58 * low 59 * 60 * Without frame pointers: 61 * 62 * high 63 * original ARM_SP => +--------------+ 64 * | r4-r9,fp,lr | callee saved registers 65 * current ARM_FP => +--------------+ 66 * low 67 * 68 * When popping registers off the stack at the end of a BPF function, we 69 * reference them via the current ARM_FP register. 70 * 71 * Some eBPF operations are implemented via a call to a helper function. 72 * Such calls are "invisible" in the eBPF code, so it is up to the calling 73 * program to preserve any caller-saved ARM registers during the call. The 74 * JIT emits code to push and pop those registers onto the stack, immediately 75 * above the callee stack frame. 76 */ 77 #define CALLEE_MASK (1 << ARM_R4 | 1 << ARM_R5 | 1 << ARM_R6 | \ 78 1 << ARM_R7 | 1 << ARM_R8 | 1 << ARM_R9 | \ 79 1 << ARM_FP) 80 #define CALLEE_PUSH_MASK (CALLEE_MASK | 1 << ARM_LR) 81 #define CALLEE_POP_MASK (CALLEE_MASK | 1 << ARM_PC) 82 83 #define CALLER_MASK (1 << ARM_R0 | 1 << ARM_R1 | 1 << ARM_R2 | 1 << ARM_R3) 84 85 enum { 86 /* Stack layout - these are offsets from (top of stack - 4) */ 87 BPF_R2_HI, 88 BPF_R2_LO, 89 BPF_R3_HI, 90 BPF_R3_LO, 91 BPF_R4_HI, 92 BPF_R4_LO, 93 BPF_R5_HI, 94 BPF_R5_LO, 95 BPF_R7_HI, 96 BPF_R7_LO, 97 BPF_R8_HI, 98 BPF_R8_LO, 99 BPF_R9_HI, 100 BPF_R9_LO, 101 BPF_FP_HI, 102 BPF_FP_LO, 103 BPF_TC_HI, 104 BPF_TC_LO, 105 BPF_AX_HI, 106 BPF_AX_LO, 107 /* Stack space for BPF_REG_2, BPF_REG_3, BPF_REG_4, 108 * BPF_REG_5, BPF_REG_7, BPF_REG_8, BPF_REG_9, 109 * BPF_REG_FP and Tail call counts. 110 */ 111 BPF_JIT_SCRATCH_REGS, 112 }; 113 114 /* 115 * Negative "register" values indicate the register is stored on the stack 116 * and are the offset from the top of the eBPF JIT scratch space. 117 */ 118 #define STACK_OFFSET(k) (-4 - (k) * 4) 119 #define SCRATCH_SIZE (BPF_JIT_SCRATCH_REGS * 4) 120 121 #ifdef CONFIG_FRAME_POINTER 122 #define EBPF_SCRATCH_TO_ARM_FP(x) ((x) - 4 * hweight16(CALLEE_PUSH_MASK) - 4) 123 #else 124 #define EBPF_SCRATCH_TO_ARM_FP(x) (x) 125 #endif 126 127 #define TMP_REG_1 (MAX_BPF_JIT_REG + 0) /* TEMP Register 1 */ 128 #define TMP_REG_2 (MAX_BPF_JIT_REG + 1) /* TEMP Register 2 */ 129 #define TCALL_CNT (MAX_BPF_JIT_REG + 2) /* Tail Call Count */ 130 131 #define FLAG_IMM_OVERFLOW (1 << 0) 132 133 /* 134 * Map eBPF registers to ARM 32bit registers or stack scratch space. 135 * 136 * 1. First argument is passed using the arm 32bit registers and rest of the 137 * arguments are passed on stack scratch space. 138 * 2. First callee-saved argument is mapped to arm 32 bit registers and rest 139 * arguments are mapped to scratch space on stack. 140 * 3. We need two 64 bit temp registers to do complex operations on eBPF 141 * registers. 142 * 143 * As the eBPF registers are all 64 bit registers and arm has only 32 bit 144 * registers, we have to map each eBPF registers with two arm 32 bit regs or 145 * scratch memory space and we have to build eBPF 64 bit register from those. 146 * 147 */ 148 static const s8 bpf2a32[][2] = { 149 /* return value from in-kernel function, and exit value from eBPF */ 150 [BPF_REG_0] = {ARM_R1, ARM_R0}, 151 /* arguments from eBPF program to in-kernel function */ 152 [BPF_REG_1] = {ARM_R3, ARM_R2}, 153 /* Stored on stack scratch space */ 154 [BPF_REG_2] = {STACK_OFFSET(BPF_R2_HI), STACK_OFFSET(BPF_R2_LO)}, 155 [BPF_REG_3] = {STACK_OFFSET(BPF_R3_HI), STACK_OFFSET(BPF_R3_LO)}, 156 [BPF_REG_4] = {STACK_OFFSET(BPF_R4_HI), STACK_OFFSET(BPF_R4_LO)}, 157 [BPF_REG_5] = {STACK_OFFSET(BPF_R5_HI), STACK_OFFSET(BPF_R5_LO)}, 158 /* callee saved registers that in-kernel function will preserve */ 159 [BPF_REG_6] = {ARM_R5, ARM_R4}, 160 /* Stored on stack scratch space */ 161 [BPF_REG_7] = {STACK_OFFSET(BPF_R7_HI), STACK_OFFSET(BPF_R7_LO)}, 162 [BPF_REG_8] = {STACK_OFFSET(BPF_R8_HI), STACK_OFFSET(BPF_R8_LO)}, 163 [BPF_REG_9] = {STACK_OFFSET(BPF_R9_HI), STACK_OFFSET(BPF_R9_LO)}, 164 /* Read only Frame Pointer to access Stack */ 165 [BPF_REG_FP] = {STACK_OFFSET(BPF_FP_HI), STACK_OFFSET(BPF_FP_LO)}, 166 /* Temporary Register for BPF JIT, can be used 167 * for constant blindings and others. 168 */ 169 [TMP_REG_1] = {ARM_R7, ARM_R6}, 170 [TMP_REG_2] = {ARM_R9, ARM_R8}, 171 /* Tail call count. Stored on stack scratch space. */ 172 [TCALL_CNT] = {STACK_OFFSET(BPF_TC_HI), STACK_OFFSET(BPF_TC_LO)}, 173 /* temporary register for blinding constants. 174 * Stored on stack scratch space. 175 */ 176 [BPF_REG_AX] = {STACK_OFFSET(BPF_AX_HI), STACK_OFFSET(BPF_AX_LO)}, 177 }; 178 179 #define dst_lo dst[1] 180 #define dst_hi dst[0] 181 #define src_lo src[1] 182 #define src_hi src[0] 183 184 /* 185 * JIT Context: 186 * 187 * prog : bpf_prog 188 * idx : index of current last JITed instruction. 189 * prologue_bytes : bytes used in prologue. 190 * epilogue_offset : offset of epilogue starting. 191 * offsets : array of eBPF instruction offsets in 192 * JITed code. 193 * target : final JITed code. 194 * epilogue_bytes : no of bytes used in epilogue. 195 * imm_count : no of immediate counts used for global 196 * variables. 197 * imms : array of global variable addresses. 198 */ 199 200 struct jit_ctx { 201 const struct bpf_prog *prog; 202 unsigned int idx; 203 unsigned int prologue_bytes; 204 unsigned int epilogue_offset; 205 unsigned int cpu_architecture; 206 u32 flags; 207 u32 *offsets; 208 u32 *target; 209 u32 stack_size; 210 #if __LINUX_ARM_ARCH__ < 7 211 u16 epilogue_bytes; 212 u16 imm_count; 213 u32 *imms; 214 #endif 215 }; 216 217 /* 218 * Wrappers which handle both OABI and EABI and assures Thumb2 interworking 219 * (where the assembly routines like __aeabi_uidiv could cause problems). 220 */ 221 static u32 jit_udiv32(u32 dividend, u32 divisor) 222 { 223 return dividend / divisor; 224 } 225 226 static u32 jit_mod32(u32 dividend, u32 divisor) 227 { 228 return dividend % divisor; 229 } 230 231 static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx) 232 { 233 inst |= (cond << 28); 234 inst = __opcode_to_mem_arm(inst); 235 236 if (ctx->target != NULL) 237 ctx->target[ctx->idx] = inst; 238 239 ctx->idx++; 240 } 241 242 /* 243 * Emit an instruction that will be executed unconditionally. 244 */ 245 static inline void emit(u32 inst, struct jit_ctx *ctx) 246 { 247 _emit(ARM_COND_AL, inst, ctx); 248 } 249 250 /* 251 * This is rather horrid, but necessary to convert an integer constant 252 * to an immediate operand for the opcodes, and be able to detect at 253 * build time whether the constant can't be converted (iow, usable in 254 * BUILD_BUG_ON()). 255 */ 256 #define imm12val(v, s) (rol32(v, (s)) | (s) << 7) 257 #define const_imm8m(x) \ 258 ({ int r; \ 259 u32 v = (x); \ 260 if (!(v & ~0x000000ff)) \ 261 r = imm12val(v, 0); \ 262 else if (!(v & ~0xc000003f)) \ 263 r = imm12val(v, 2); \ 264 else if (!(v & ~0xf000000f)) \ 265 r = imm12val(v, 4); \ 266 else if (!(v & ~0xfc000003)) \ 267 r = imm12val(v, 6); \ 268 else if (!(v & ~0xff000000)) \ 269 r = imm12val(v, 8); \ 270 else if (!(v & ~0x3fc00000)) \ 271 r = imm12val(v, 10); \ 272 else if (!(v & ~0x0ff00000)) \ 273 r = imm12val(v, 12); \ 274 else if (!(v & ~0x03fc0000)) \ 275 r = imm12val(v, 14); \ 276 else if (!(v & ~0x00ff0000)) \ 277 r = imm12val(v, 16); \ 278 else if (!(v & ~0x003fc000)) \ 279 r = imm12val(v, 18); \ 280 else if (!(v & ~0x000ff000)) \ 281 r = imm12val(v, 20); \ 282 else if (!(v & ~0x0003fc00)) \ 283 r = imm12val(v, 22); \ 284 else if (!(v & ~0x0000ff00)) \ 285 r = imm12val(v, 24); \ 286 else if (!(v & ~0x00003fc0)) \ 287 r = imm12val(v, 26); \ 288 else if (!(v & ~0x00000ff0)) \ 289 r = imm12val(v, 28); \ 290 else if (!(v & ~0x000003fc)) \ 291 r = imm12val(v, 30); \ 292 else \ 293 r = -1; \ 294 r; }) 295 296 /* 297 * Checks if immediate value can be converted to imm12(12 bits) value. 298 */ 299 static int imm8m(u32 x) 300 { 301 u32 rot; 302 303 for (rot = 0; rot < 16; rot++) 304 if ((x & ~ror32(0xff, 2 * rot)) == 0) 305 return rol32(x, 2 * rot) | (rot << 8); 306 return -1; 307 } 308 309 #define imm8m(x) (__builtin_constant_p(x) ? const_imm8m(x) : imm8m(x)) 310 311 static u32 arm_bpf_ldst_imm12(u32 op, u8 rt, u8 rn, s16 imm12) 312 { 313 op |= rt << 12 | rn << 16; 314 if (imm12 >= 0) 315 op |= ARM_INST_LDST__U; 316 else 317 imm12 = -imm12; 318 return op | (imm12 & ARM_INST_LDST__IMM12); 319 } 320 321 static u32 arm_bpf_ldst_imm8(u32 op, u8 rt, u8 rn, s16 imm8) 322 { 323 op |= rt << 12 | rn << 16; 324 if (imm8 >= 0) 325 op |= ARM_INST_LDST__U; 326 else 327 imm8 = -imm8; 328 return op | (imm8 & 0xf0) << 4 | (imm8 & 0x0f); 329 } 330 331 #define ARM_LDR_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_LDR_I, rt, rn, off) 332 #define ARM_LDRB_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_LDRB_I, rt, rn, off) 333 #define ARM_LDRD_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRD_I, rt, rn, off) 334 #define ARM_LDRH_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRH_I, rt, rn, off) 335 336 #define ARM_LDRSH_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRSH_I, rt, rn, off) 337 #define ARM_LDRSB_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_LDRSB_I, rt, rn, off) 338 339 #define ARM_STR_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_STR_I, rt, rn, off) 340 #define ARM_STRB_I(rt, rn, off) arm_bpf_ldst_imm12(ARM_INST_STRB_I, rt, rn, off) 341 #define ARM_STRD_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_STRD_I, rt, rn, off) 342 #define ARM_STRH_I(rt, rn, off) arm_bpf_ldst_imm8(ARM_INST_STRH_I, rt, rn, off) 343 344 /* 345 * Initializes the JIT space with undefined instructions. 346 */ 347 static void jit_fill_hole(void *area, unsigned int size) 348 { 349 u32 *ptr; 350 /* We are guaranteed to have aligned memory. */ 351 for (ptr = area; size >= sizeof(u32); size -= sizeof(u32)) 352 *ptr++ = __opcode_to_mem_arm(ARM_INST_UDF); 353 } 354 355 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 356 /* EABI requires the stack to be aligned to 64-bit boundaries */ 357 #define STACK_ALIGNMENT 8 358 #else 359 /* Stack must be aligned to 32-bit boundaries */ 360 #define STACK_ALIGNMENT 4 361 #endif 362 363 /* total stack size used in JITed code */ 364 #define _STACK_SIZE (ctx->prog->aux->stack_depth + SCRATCH_SIZE) 365 #define STACK_SIZE ALIGN(_STACK_SIZE, STACK_ALIGNMENT) 366 367 #if __LINUX_ARM_ARCH__ < 7 368 369 static u16 imm_offset(u32 k, struct jit_ctx *ctx) 370 { 371 unsigned int i = 0, offset; 372 u16 imm; 373 374 /* on the "fake" run we just count them (duplicates included) */ 375 if (ctx->target == NULL) { 376 ctx->imm_count++; 377 return 0; 378 } 379 380 while ((i < ctx->imm_count) && ctx->imms[i]) { 381 if (ctx->imms[i] == k) 382 break; 383 i++; 384 } 385 386 if (ctx->imms[i] == 0) 387 ctx->imms[i] = k; 388 389 /* constants go just after the epilogue */ 390 offset = ctx->offsets[ctx->prog->len - 1] * 4; 391 offset += ctx->prologue_bytes; 392 offset += ctx->epilogue_bytes; 393 offset += i * 4; 394 395 ctx->target[offset / 4] = k; 396 397 /* PC in ARM mode == address of the instruction + 8 */ 398 imm = offset - (8 + ctx->idx * 4); 399 400 if (imm & ~0xfff) { 401 /* 402 * literal pool is too far, signal it into flags. we 403 * can only detect it on the second pass unfortunately. 404 */ 405 ctx->flags |= FLAG_IMM_OVERFLOW; 406 return 0; 407 } 408 409 return imm; 410 } 411 412 #endif /* __LINUX_ARM_ARCH__ */ 413 414 static inline int bpf2a32_offset(int bpf_to, int bpf_from, 415 const struct jit_ctx *ctx) { 416 int to, from; 417 418 if (ctx->target == NULL) 419 return 0; 420 to = ctx->offsets[bpf_to]; 421 from = ctx->offsets[bpf_from]; 422 423 return to - from - 1; 424 } 425 426 /* 427 * Move an immediate that's not an imm8m to a core register. 428 */ 429 static inline void emit_mov_i_no8m(const u8 rd, u32 val, struct jit_ctx *ctx) 430 { 431 #if __LINUX_ARM_ARCH__ < 7 432 emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx); 433 #else 434 emit(ARM_MOVW(rd, val & 0xffff), ctx); 435 if (val > 0xffff) 436 emit(ARM_MOVT(rd, val >> 16), ctx); 437 #endif 438 } 439 440 static inline void emit_mov_i(const u8 rd, u32 val, struct jit_ctx *ctx) 441 { 442 int imm12 = imm8m(val); 443 444 if (imm12 >= 0) 445 emit(ARM_MOV_I(rd, imm12), ctx); 446 else 447 emit_mov_i_no8m(rd, val, ctx); 448 } 449 450 static void emit_bx_r(u8 tgt_reg, struct jit_ctx *ctx) 451 { 452 if (elf_hwcap & HWCAP_THUMB) 453 emit(ARM_BX(tgt_reg), ctx); 454 else 455 emit(ARM_MOV_R(ARM_PC, tgt_reg), ctx); 456 } 457 458 static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx) 459 { 460 #if __LINUX_ARM_ARCH__ < 5 461 emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx); 462 emit_bx_r(tgt_reg, ctx); 463 #else 464 emit(ARM_BLX_R(tgt_reg), ctx); 465 #endif 466 } 467 468 static inline int epilogue_offset(const struct jit_ctx *ctx) 469 { 470 int to, from; 471 /* No need for 1st dummy run */ 472 if (ctx->target == NULL) 473 return 0; 474 to = ctx->epilogue_offset; 475 from = ctx->idx; 476 477 return to - from - 2; 478 } 479 480 static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op) 481 { 482 const int exclude_mask = BIT(ARM_R0) | BIT(ARM_R1); 483 const s8 *tmp = bpf2a32[TMP_REG_1]; 484 485 #if __LINUX_ARM_ARCH__ == 7 486 if (elf_hwcap & HWCAP_IDIVA) { 487 if (op == BPF_DIV) 488 emit(ARM_UDIV(rd, rm, rn), ctx); 489 else { 490 emit(ARM_UDIV(ARM_IP, rm, rn), ctx); 491 emit(ARM_MLS(rd, rn, ARM_IP, rm), ctx); 492 } 493 return; 494 } 495 #endif 496 497 /* 498 * For BPF_ALU | BPF_DIV | BPF_K instructions 499 * As ARM_R1 and ARM_R0 contains 1st argument of bpf 500 * function, we need to save it on caller side to save 501 * it from getting destroyed within callee. 502 * After the return from the callee, we restore ARM_R0 503 * ARM_R1. 504 */ 505 if (rn != ARM_R1) { 506 emit(ARM_MOV_R(tmp[0], ARM_R1), ctx); 507 emit(ARM_MOV_R(ARM_R1, rn), ctx); 508 } 509 if (rm != ARM_R0) { 510 emit(ARM_MOV_R(tmp[1], ARM_R0), ctx); 511 emit(ARM_MOV_R(ARM_R0, rm), ctx); 512 } 513 514 /* Push caller-saved registers on stack */ 515 emit(ARM_PUSH(CALLER_MASK & ~exclude_mask), ctx); 516 517 /* Call appropriate function */ 518 emit_mov_i(ARM_IP, op == BPF_DIV ? 519 (u32)jit_udiv32 : (u32)jit_mod32, ctx); 520 emit_blx_r(ARM_IP, ctx); 521 522 /* Restore caller-saved registers from stack */ 523 emit(ARM_POP(CALLER_MASK & ~exclude_mask), ctx); 524 525 /* Save return value */ 526 if (rd != ARM_R0) 527 emit(ARM_MOV_R(rd, ARM_R0), ctx); 528 529 /* Restore ARM_R0 and ARM_R1 */ 530 if (rn != ARM_R1) 531 emit(ARM_MOV_R(ARM_R1, tmp[0]), ctx); 532 if (rm != ARM_R0) 533 emit(ARM_MOV_R(ARM_R0, tmp[1]), ctx); 534 } 535 536 /* Is the translated BPF register on stack? */ 537 static bool is_stacked(s8 reg) 538 { 539 return reg < 0; 540 } 541 542 /* If a BPF register is on the stack (stk is true), load it to the 543 * supplied temporary register and return the temporary register 544 * for subsequent operations, otherwise just use the CPU register. 545 */ 546 static s8 arm_bpf_get_reg32(s8 reg, s8 tmp, struct jit_ctx *ctx) 547 { 548 if (is_stacked(reg)) { 549 emit(ARM_LDR_I(tmp, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(reg)), ctx); 550 reg = tmp; 551 } 552 return reg; 553 } 554 555 static const s8 *arm_bpf_get_reg64(const s8 *reg, const s8 *tmp, 556 struct jit_ctx *ctx) 557 { 558 if (is_stacked(reg[1])) { 559 if (__LINUX_ARM_ARCH__ >= 6 || 560 ctx->cpu_architecture >= CPU_ARCH_ARMv5TE) { 561 emit(ARM_LDRD_I(tmp[1], ARM_FP, 562 EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx); 563 } else { 564 emit(ARM_LDR_I(tmp[1], ARM_FP, 565 EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx); 566 emit(ARM_LDR_I(tmp[0], ARM_FP, 567 EBPF_SCRATCH_TO_ARM_FP(reg[0])), ctx); 568 } 569 reg = tmp; 570 } 571 return reg; 572 } 573 574 /* If a BPF register is on the stack (stk is true), save the register 575 * back to the stack. If the source register is not the same, then 576 * move it into the correct register. 577 */ 578 static void arm_bpf_put_reg32(s8 reg, s8 src, struct jit_ctx *ctx) 579 { 580 if (is_stacked(reg)) 581 emit(ARM_STR_I(src, ARM_FP, EBPF_SCRATCH_TO_ARM_FP(reg)), ctx); 582 else if (reg != src) 583 emit(ARM_MOV_R(reg, src), ctx); 584 } 585 586 static void arm_bpf_put_reg64(const s8 *reg, const s8 *src, 587 struct jit_ctx *ctx) 588 { 589 if (is_stacked(reg[1])) { 590 if (__LINUX_ARM_ARCH__ >= 6 || 591 ctx->cpu_architecture >= CPU_ARCH_ARMv5TE) { 592 emit(ARM_STRD_I(src[1], ARM_FP, 593 EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx); 594 } else { 595 emit(ARM_STR_I(src[1], ARM_FP, 596 EBPF_SCRATCH_TO_ARM_FP(reg[1])), ctx); 597 emit(ARM_STR_I(src[0], ARM_FP, 598 EBPF_SCRATCH_TO_ARM_FP(reg[0])), ctx); 599 } 600 } else { 601 if (reg[1] != src[1]) 602 emit(ARM_MOV_R(reg[1], src[1]), ctx); 603 if (reg[0] != src[0]) 604 emit(ARM_MOV_R(reg[0], src[0]), ctx); 605 } 606 } 607 608 static inline void emit_a32_mov_i(const s8 dst, const u32 val, 609 struct jit_ctx *ctx) 610 { 611 const s8 *tmp = bpf2a32[TMP_REG_1]; 612 613 if (is_stacked(dst)) { 614 emit_mov_i(tmp[1], val, ctx); 615 arm_bpf_put_reg32(dst, tmp[1], ctx); 616 } else { 617 emit_mov_i(dst, val, ctx); 618 } 619 } 620 621 static void emit_a32_mov_i64(const s8 dst[], u64 val, struct jit_ctx *ctx) 622 { 623 const s8 *tmp = bpf2a32[TMP_REG_1]; 624 const s8 *rd = is_stacked(dst_lo) ? tmp : dst; 625 626 emit_mov_i(rd[1], (u32)val, ctx); 627 emit_mov_i(rd[0], val >> 32, ctx); 628 629 arm_bpf_put_reg64(dst, rd, ctx); 630 } 631 632 /* Sign extended move */ 633 static inline void emit_a32_mov_se_i64(const bool is64, const s8 dst[], 634 const u32 val, struct jit_ctx *ctx) { 635 u64 val64 = val; 636 637 if (is64 && (val & (1<<31))) 638 val64 |= 0xffffffff00000000ULL; 639 emit_a32_mov_i64(dst, val64, ctx); 640 } 641 642 static inline void emit_a32_add_r(const u8 dst, const u8 src, 643 const bool is64, const bool hi, 644 struct jit_ctx *ctx) { 645 /* 64 bit : 646 * adds dst_lo, dst_lo, src_lo 647 * adc dst_hi, dst_hi, src_hi 648 * 32 bit : 649 * add dst_lo, dst_lo, src_lo 650 */ 651 if (!hi && is64) 652 emit(ARM_ADDS_R(dst, dst, src), ctx); 653 else if (hi && is64) 654 emit(ARM_ADC_R(dst, dst, src), ctx); 655 else 656 emit(ARM_ADD_R(dst, dst, src), ctx); 657 } 658 659 static inline void emit_a32_sub_r(const u8 dst, const u8 src, 660 const bool is64, const bool hi, 661 struct jit_ctx *ctx) { 662 /* 64 bit : 663 * subs dst_lo, dst_lo, src_lo 664 * sbc dst_hi, dst_hi, src_hi 665 * 32 bit : 666 * sub dst_lo, dst_lo, src_lo 667 */ 668 if (!hi && is64) 669 emit(ARM_SUBS_R(dst, dst, src), ctx); 670 else if (hi && is64) 671 emit(ARM_SBC_R(dst, dst, src), ctx); 672 else 673 emit(ARM_SUB_R(dst, dst, src), ctx); 674 } 675 676 static inline void emit_alu_r(const u8 dst, const u8 src, const bool is64, 677 const bool hi, const u8 op, struct jit_ctx *ctx){ 678 switch (BPF_OP(op)) { 679 /* dst = dst + src */ 680 case BPF_ADD: 681 emit_a32_add_r(dst, src, is64, hi, ctx); 682 break; 683 /* dst = dst - src */ 684 case BPF_SUB: 685 emit_a32_sub_r(dst, src, is64, hi, ctx); 686 break; 687 /* dst = dst | src */ 688 case BPF_OR: 689 emit(ARM_ORR_R(dst, dst, src), ctx); 690 break; 691 /* dst = dst & src */ 692 case BPF_AND: 693 emit(ARM_AND_R(dst, dst, src), ctx); 694 break; 695 /* dst = dst ^ src */ 696 case BPF_XOR: 697 emit(ARM_EOR_R(dst, dst, src), ctx); 698 break; 699 /* dst = dst * src */ 700 case BPF_MUL: 701 emit(ARM_MUL(dst, dst, src), ctx); 702 break; 703 /* dst = dst << src */ 704 case BPF_LSH: 705 emit(ARM_LSL_R(dst, dst, src), ctx); 706 break; 707 /* dst = dst >> src */ 708 case BPF_RSH: 709 emit(ARM_LSR_R(dst, dst, src), ctx); 710 break; 711 /* dst = dst >> src (signed)*/ 712 case BPF_ARSH: 713 emit(ARM_MOV_SR(dst, dst, SRTYPE_ASR, src), ctx); 714 break; 715 } 716 } 717 718 /* ALU operation (64 bit) */ 719 static inline void emit_a32_alu_r64(const bool is64, const s8 dst[], 720 const s8 src[], struct jit_ctx *ctx, 721 const u8 op) { 722 const s8 *tmp = bpf2a32[TMP_REG_1]; 723 const s8 *tmp2 = bpf2a32[TMP_REG_2]; 724 const s8 *rd; 725 726 rd = arm_bpf_get_reg64(dst, tmp, ctx); 727 if (is64) { 728 const s8 *rs; 729 730 rs = arm_bpf_get_reg64(src, tmp2, ctx); 731 732 /* ALU operation */ 733 emit_alu_r(rd[1], rs[1], true, false, op, ctx); 734 emit_alu_r(rd[0], rs[0], true, true, op, ctx); 735 } else { 736 s8 rs; 737 738 rs = arm_bpf_get_reg32(src_lo, tmp2[1], ctx); 739 740 /* ALU operation */ 741 emit_alu_r(rd[1], rs, true, false, op, ctx); 742 if (!ctx->prog->aux->verifier_zext) 743 emit_a32_mov_i(rd[0], 0, ctx); 744 } 745 746 arm_bpf_put_reg64(dst, rd, ctx); 747 } 748 749 /* dst = src (4 bytes)*/ 750 static inline void emit_a32_mov_r(const s8 dst, const s8 src, const u8 off, 751 struct jit_ctx *ctx) { 752 const s8 *tmp = bpf2a32[TMP_REG_1]; 753 s8 rt; 754 755 rt = arm_bpf_get_reg32(src, tmp[0], ctx); 756 if (off && off != 32) { 757 emit(ARM_LSL_I(rt, rt, 32 - off), ctx); 758 emit(ARM_ASR_I(rt, rt, 32 - off), ctx); 759 } 760 arm_bpf_put_reg32(dst, rt, ctx); 761 } 762 763 /* dst = src */ 764 static inline void emit_a32_mov_r64(const bool is64, const s8 dst[], 765 const s8 src[], 766 struct jit_ctx *ctx) { 767 if (!is64) { 768 emit_a32_mov_r(dst_lo, src_lo, 0, ctx); 769 if (!ctx->prog->aux->verifier_zext) 770 /* Zero out high 4 bytes */ 771 emit_a32_mov_i(dst_hi, 0, ctx); 772 } else if (__LINUX_ARM_ARCH__ < 6 && 773 ctx->cpu_architecture < CPU_ARCH_ARMv5TE) { 774 /* complete 8 byte move */ 775 emit_a32_mov_r(dst_lo, src_lo, 0, ctx); 776 emit_a32_mov_r(dst_hi, src_hi, 0, ctx); 777 } else if (is_stacked(src_lo) && is_stacked(dst_lo)) { 778 const u8 *tmp = bpf2a32[TMP_REG_1]; 779 780 emit(ARM_LDRD_I(tmp[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(src_lo)), ctx); 781 emit(ARM_STRD_I(tmp[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(dst_lo)), ctx); 782 } else if (is_stacked(src_lo)) { 783 emit(ARM_LDRD_I(dst[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(src_lo)), ctx); 784 } else if (is_stacked(dst_lo)) { 785 emit(ARM_STRD_I(src[1], ARM_FP, EBPF_SCRATCH_TO_ARM_FP(dst_lo)), ctx); 786 } else { 787 emit(ARM_MOV_R(dst[0], src[0]), ctx); 788 emit(ARM_MOV_R(dst[1], src[1]), ctx); 789 } 790 } 791 792 /* dst = (signed)src */ 793 static inline void emit_a32_movsx_r64(const bool is64, const u8 off, const s8 dst[], const s8 src[], 794 struct jit_ctx *ctx) { 795 const s8 *tmp = bpf2a32[TMP_REG_1]; 796 const s8 *rt; 797 798 rt = arm_bpf_get_reg64(dst, tmp, ctx); 799 800 emit_a32_mov_r(dst_lo, src_lo, off, ctx); 801 if (!is64) { 802 if (!ctx->prog->aux->verifier_zext) 803 /* Zero out high 4 bytes */ 804 emit_a32_mov_i(dst_hi, 0, ctx); 805 } else { 806 emit(ARM_ASR_I(rt[0], rt[1], 31), ctx); 807 } 808 } 809 810 /* Shift operations */ 811 static inline void emit_a32_alu_i(const s8 dst, const u32 val, 812 struct jit_ctx *ctx, const u8 op) { 813 const s8 *tmp = bpf2a32[TMP_REG_1]; 814 s8 rd; 815 816 rd = arm_bpf_get_reg32(dst, tmp[0], ctx); 817 818 /* Do shift operation */ 819 switch (op) { 820 case BPF_LSH: 821 emit(ARM_LSL_I(rd, rd, val), ctx); 822 break; 823 case BPF_RSH: 824 emit(ARM_LSR_I(rd, rd, val), ctx); 825 break; 826 case BPF_ARSH: 827 emit(ARM_ASR_I(rd, rd, val), ctx); 828 break; 829 case BPF_NEG: 830 emit(ARM_RSB_I(rd, rd, val), ctx); 831 break; 832 } 833 834 arm_bpf_put_reg32(dst, rd, ctx); 835 } 836 837 /* dst = ~dst (64 bit) */ 838 static inline void emit_a32_neg64(const s8 dst[], 839 struct jit_ctx *ctx){ 840 const s8 *tmp = bpf2a32[TMP_REG_1]; 841 const s8 *rd; 842 843 /* Setup Operand */ 844 rd = arm_bpf_get_reg64(dst, tmp, ctx); 845 846 /* Do Negate Operation */ 847 emit(ARM_RSBS_I(rd[1], rd[1], 0), ctx); 848 emit(ARM_RSC_I(rd[0], rd[0], 0), ctx); 849 850 arm_bpf_put_reg64(dst, rd, ctx); 851 } 852 853 /* dst = dst << src */ 854 static inline void emit_a32_lsh_r64(const s8 dst[], const s8 src[], 855 struct jit_ctx *ctx) { 856 const s8 *tmp = bpf2a32[TMP_REG_1]; 857 const s8 *tmp2 = bpf2a32[TMP_REG_2]; 858 const s8 *rd; 859 s8 rt; 860 861 /* Setup Operands */ 862 rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx); 863 rd = arm_bpf_get_reg64(dst, tmp, ctx); 864 865 /* Do LSH operation */ 866 emit(ARM_SUB_I(ARM_IP, rt, 32), ctx); 867 emit(ARM_RSB_I(tmp2[0], rt, 32), ctx); 868 emit(ARM_MOV_SR(ARM_LR, rd[0], SRTYPE_ASL, rt), ctx); 869 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[1], SRTYPE_ASL, ARM_IP), ctx); 870 emit(ARM_ORR_SR(ARM_IP, ARM_LR, rd[1], SRTYPE_LSR, tmp2[0]), ctx); 871 emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_ASL, rt), ctx); 872 873 arm_bpf_put_reg32(dst_lo, ARM_LR, ctx); 874 arm_bpf_put_reg32(dst_hi, ARM_IP, ctx); 875 } 876 877 /* dst = dst >> src (signed)*/ 878 static inline void emit_a32_arsh_r64(const s8 dst[], const s8 src[], 879 struct jit_ctx *ctx) { 880 const s8 *tmp = bpf2a32[TMP_REG_1]; 881 const s8 *tmp2 = bpf2a32[TMP_REG_2]; 882 const s8 *rd; 883 s8 rt; 884 885 /* Setup Operands */ 886 rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx); 887 rd = arm_bpf_get_reg64(dst, tmp, ctx); 888 889 /* Do the ARSH operation */ 890 emit(ARM_RSB_I(ARM_IP, rt, 32), ctx); 891 emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx); 892 emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_LSR, rt), ctx); 893 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASL, ARM_IP), ctx); 894 _emit(ARM_COND_PL, 895 ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASR, tmp2[0]), ctx); 896 emit(ARM_MOV_SR(ARM_IP, rd[0], SRTYPE_ASR, rt), ctx); 897 898 arm_bpf_put_reg32(dst_lo, ARM_LR, ctx); 899 arm_bpf_put_reg32(dst_hi, ARM_IP, ctx); 900 } 901 902 /* dst = dst >> src */ 903 static inline void emit_a32_rsh_r64(const s8 dst[], const s8 src[], 904 struct jit_ctx *ctx) { 905 const s8 *tmp = bpf2a32[TMP_REG_1]; 906 const s8 *tmp2 = bpf2a32[TMP_REG_2]; 907 const s8 *rd; 908 s8 rt; 909 910 /* Setup Operands */ 911 rt = arm_bpf_get_reg32(src_lo, tmp2[1], ctx); 912 rd = arm_bpf_get_reg64(dst, tmp, ctx); 913 914 /* Do RSH operation */ 915 emit(ARM_RSB_I(ARM_IP, rt, 32), ctx); 916 emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx); 917 emit(ARM_MOV_SR(ARM_LR, rd[1], SRTYPE_LSR, rt), ctx); 918 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_ASL, ARM_IP), ctx); 919 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd[0], SRTYPE_LSR, tmp2[0]), ctx); 920 emit(ARM_MOV_SR(ARM_IP, rd[0], SRTYPE_LSR, rt), ctx); 921 922 arm_bpf_put_reg32(dst_lo, ARM_LR, ctx); 923 arm_bpf_put_reg32(dst_hi, ARM_IP, ctx); 924 } 925 926 /* dst = dst << val */ 927 static inline void emit_a32_lsh_i64(const s8 dst[], 928 const u32 val, struct jit_ctx *ctx){ 929 const s8 *tmp = bpf2a32[TMP_REG_1]; 930 const s8 *tmp2 = bpf2a32[TMP_REG_2]; 931 const s8 *rd; 932 933 /* Setup operands */ 934 rd = arm_bpf_get_reg64(dst, tmp, ctx); 935 936 /* Do LSH operation */ 937 if (val < 32) { 938 emit(ARM_MOV_SI(tmp2[0], rd[0], SRTYPE_ASL, val), ctx); 939 emit(ARM_ORR_SI(rd[0], tmp2[0], rd[1], SRTYPE_LSR, 32 - val), ctx); 940 emit(ARM_MOV_SI(rd[1], rd[1], SRTYPE_ASL, val), ctx); 941 } else { 942 if (val == 32) 943 emit(ARM_MOV_R(rd[0], rd[1]), ctx); 944 else 945 emit(ARM_MOV_SI(rd[0], rd[1], SRTYPE_ASL, val - 32), ctx); 946 emit(ARM_EOR_R(rd[1], rd[1], rd[1]), ctx); 947 } 948 949 arm_bpf_put_reg64(dst, rd, ctx); 950 } 951 952 /* dst = dst >> val */ 953 static inline void emit_a32_rsh_i64(const s8 dst[], 954 const u32 val, struct jit_ctx *ctx) { 955 const s8 *tmp = bpf2a32[TMP_REG_1]; 956 const s8 *tmp2 = bpf2a32[TMP_REG_2]; 957 const s8 *rd; 958 959 /* Setup operands */ 960 rd = arm_bpf_get_reg64(dst, tmp, ctx); 961 962 /* Do LSR operation */ 963 if (val == 0) { 964 /* An immediate value of 0 encodes a shift amount of 32 965 * for LSR. To shift by 0, don't do anything. 966 */ 967 } else if (val < 32) { 968 emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx); 969 emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx); 970 emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_LSR, val), ctx); 971 } else if (val == 32) { 972 emit(ARM_MOV_R(rd[1], rd[0]), ctx); 973 emit(ARM_MOV_I(rd[0], 0), ctx); 974 } else { 975 emit(ARM_MOV_SI(rd[1], rd[0], SRTYPE_LSR, val - 32), ctx); 976 emit(ARM_MOV_I(rd[0], 0), ctx); 977 } 978 979 arm_bpf_put_reg64(dst, rd, ctx); 980 } 981 982 /* dst = dst >> val (signed) */ 983 static inline void emit_a32_arsh_i64(const s8 dst[], 984 const u32 val, struct jit_ctx *ctx){ 985 const s8 *tmp = bpf2a32[TMP_REG_1]; 986 const s8 *tmp2 = bpf2a32[TMP_REG_2]; 987 const s8 *rd; 988 989 /* Setup operands */ 990 rd = arm_bpf_get_reg64(dst, tmp, ctx); 991 992 /* Do ARSH operation */ 993 if (val == 0) { 994 /* An immediate value of 0 encodes a shift amount of 32 995 * for ASR. To shift by 0, don't do anything. 996 */ 997 } else if (val < 32) { 998 emit(ARM_MOV_SI(tmp2[1], rd[1], SRTYPE_LSR, val), ctx); 999 emit(ARM_ORR_SI(rd[1], tmp2[1], rd[0], SRTYPE_ASL, 32 - val), ctx); 1000 emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, val), ctx); 1001 } else if (val == 32) { 1002 emit(ARM_MOV_R(rd[1], rd[0]), ctx); 1003 emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, 31), ctx); 1004 } else { 1005 emit(ARM_MOV_SI(rd[1], rd[0], SRTYPE_ASR, val - 32), ctx); 1006 emit(ARM_MOV_SI(rd[0], rd[0], SRTYPE_ASR, 31), ctx); 1007 } 1008 1009 arm_bpf_put_reg64(dst, rd, ctx); 1010 } 1011 1012 static inline void emit_a32_mul_r64(const s8 dst[], const s8 src[], 1013 struct jit_ctx *ctx) { 1014 const s8 *tmp = bpf2a32[TMP_REG_1]; 1015 const s8 *tmp2 = bpf2a32[TMP_REG_2]; 1016 const s8 *rd, *rt; 1017 1018 /* Setup operands for multiplication */ 1019 rd = arm_bpf_get_reg64(dst, tmp, ctx); 1020 rt = arm_bpf_get_reg64(src, tmp2, ctx); 1021 1022 /* Do Multiplication */ 1023 emit(ARM_MUL(ARM_IP, rd[1], rt[0]), ctx); 1024 emit(ARM_MUL(ARM_LR, rd[0], rt[1]), ctx); 1025 emit(ARM_ADD_R(ARM_LR, ARM_IP, ARM_LR), ctx); 1026 1027 emit(ARM_UMULL(ARM_IP, rd[0], rd[1], rt[1]), ctx); 1028 emit(ARM_ADD_R(rd[0], ARM_LR, rd[0]), ctx); 1029 1030 arm_bpf_put_reg32(dst_lo, ARM_IP, ctx); 1031 arm_bpf_put_reg32(dst_hi, rd[0], ctx); 1032 } 1033 1034 static bool is_ldst_imm(s16 off, const u8 size) 1035 { 1036 s16 off_max = 0; 1037 1038 switch (size) { 1039 case BPF_B: 1040 case BPF_W: 1041 off_max = 0xfff; 1042 break; 1043 case BPF_H: 1044 off_max = 0xff; 1045 break; 1046 case BPF_DW: 1047 /* Need to make sure off+4 does not overflow. */ 1048 off_max = 0xfff - 4; 1049 break; 1050 } 1051 return -off_max <= off && off <= off_max; 1052 } 1053 1054 static bool is_ldst_imm8(s16 off, const u8 size) 1055 { 1056 s16 off_max = 0; 1057 1058 switch (size) { 1059 case BPF_B: 1060 off_max = 0xff; 1061 break; 1062 case BPF_W: 1063 off_max = 0xfff; 1064 break; 1065 case BPF_H: 1066 off_max = 0xff; 1067 break; 1068 } 1069 return -off_max <= off && off <= off_max; 1070 } 1071 1072 /* *(size *)(dst + off) = src */ 1073 static inline void emit_str_r(const s8 dst, const s8 src[], 1074 s16 off, struct jit_ctx *ctx, const u8 sz){ 1075 const s8 *tmp = bpf2a32[TMP_REG_1]; 1076 s8 rd; 1077 1078 rd = arm_bpf_get_reg32(dst, tmp[1], ctx); 1079 1080 if (!is_ldst_imm(off, sz)) { 1081 emit_a32_mov_i(tmp[0], off, ctx); 1082 emit(ARM_ADD_R(tmp[0], tmp[0], rd), ctx); 1083 rd = tmp[0]; 1084 off = 0; 1085 } 1086 switch (sz) { 1087 case BPF_B: 1088 /* Store a Byte */ 1089 emit(ARM_STRB_I(src_lo, rd, off), ctx); 1090 break; 1091 case BPF_H: 1092 /* Store a HalfWord */ 1093 emit(ARM_STRH_I(src_lo, rd, off), ctx); 1094 break; 1095 case BPF_W: 1096 /* Store a Word */ 1097 emit(ARM_STR_I(src_lo, rd, off), ctx); 1098 break; 1099 case BPF_DW: 1100 /* Store a Double Word */ 1101 emit(ARM_STR_I(src_lo, rd, off), ctx); 1102 emit(ARM_STR_I(src_hi, rd, off + 4), ctx); 1103 break; 1104 } 1105 } 1106 1107 /* dst = *(size*)(src + off) */ 1108 static inline void emit_ldx_r(const s8 dst[], const s8 src, 1109 s16 off, struct jit_ctx *ctx, const u8 sz){ 1110 const s8 *tmp = bpf2a32[TMP_REG_1]; 1111 const s8 *rd = is_stacked(dst_lo) ? tmp : dst; 1112 s8 rm = src; 1113 1114 if (!is_ldst_imm(off, sz)) { 1115 emit_a32_mov_i(tmp[0], off, ctx); 1116 emit(ARM_ADD_R(tmp[0], tmp[0], src), ctx); 1117 rm = tmp[0]; 1118 off = 0; 1119 } else if (rd[1] == rm) { 1120 emit(ARM_MOV_R(tmp[0], rm), ctx); 1121 rm = tmp[0]; 1122 } 1123 switch (sz) { 1124 case BPF_B: 1125 /* Load a Byte */ 1126 emit(ARM_LDRB_I(rd[1], rm, off), ctx); 1127 if (!ctx->prog->aux->verifier_zext) 1128 emit_a32_mov_i(rd[0], 0, ctx); 1129 break; 1130 case BPF_H: 1131 /* Load a HalfWord */ 1132 emit(ARM_LDRH_I(rd[1], rm, off), ctx); 1133 if (!ctx->prog->aux->verifier_zext) 1134 emit_a32_mov_i(rd[0], 0, ctx); 1135 break; 1136 case BPF_W: 1137 /* Load a Word */ 1138 emit(ARM_LDR_I(rd[1], rm, off), ctx); 1139 if (!ctx->prog->aux->verifier_zext) 1140 emit_a32_mov_i(rd[0], 0, ctx); 1141 break; 1142 case BPF_DW: 1143 /* Load a Double Word */ 1144 emit(ARM_LDR_I(rd[1], rm, off), ctx); 1145 emit(ARM_LDR_I(rd[0], rm, off + 4), ctx); 1146 break; 1147 } 1148 arm_bpf_put_reg64(dst, rd, ctx); 1149 } 1150 1151 /* dst = *(signed size*)(src + off) */ 1152 static inline void emit_ldsx_r(const s8 dst[], const s8 src, 1153 s16 off, struct jit_ctx *ctx, const u8 sz){ 1154 const s8 *tmp = bpf2a32[TMP_REG_1]; 1155 const s8 *rd = is_stacked(dst_lo) ? tmp : dst; 1156 s8 rm = src; 1157 int add_off; 1158 1159 if (!is_ldst_imm8(off, sz)) { 1160 /* 1161 * offset does not fit in the load/store immediate, 1162 * construct an ADD instruction to apply the offset. 1163 */ 1164 add_off = imm8m(off); 1165 if (add_off > 0) { 1166 emit(ARM_ADD_I(tmp[0], src, add_off), ctx); 1167 rm = tmp[0]; 1168 } else { 1169 emit_a32_mov_i(tmp[0], off, ctx); 1170 emit(ARM_ADD_R(tmp[0], tmp[0], src), ctx); 1171 rm = tmp[0]; 1172 } 1173 off = 0; 1174 } 1175 1176 switch (sz) { 1177 case BPF_B: 1178 /* Load a Byte with sign extension*/ 1179 emit(ARM_LDRSB_I(rd[1], rm, off), ctx); 1180 break; 1181 case BPF_H: 1182 /* Load a HalfWord with sign extension*/ 1183 emit(ARM_LDRSH_I(rd[1], rm, off), ctx); 1184 break; 1185 case BPF_W: 1186 /* Load a Word*/ 1187 emit(ARM_LDR_I(rd[1], rm, off), ctx); 1188 break; 1189 } 1190 /* Carry the sign extension to upper 32 bits */ 1191 emit(ARM_ASR_I(rd[0], rd[1], 31), ctx); 1192 arm_bpf_put_reg64(dst, rd, ctx); 1193 } 1194 1195 /* Arithmatic Operation */ 1196 static inline void emit_ar_r(const u8 rd, const u8 rt, const u8 rm, 1197 const u8 rn, struct jit_ctx *ctx, u8 op, 1198 bool is_jmp64) { 1199 switch (op) { 1200 case BPF_JSET: 1201 if (is_jmp64) { 1202 emit(ARM_AND_R(ARM_IP, rt, rn), ctx); 1203 emit(ARM_AND_R(ARM_LR, rd, rm), ctx); 1204 emit(ARM_ORRS_R(ARM_IP, ARM_LR, ARM_IP), ctx); 1205 } else { 1206 emit(ARM_ANDS_R(ARM_IP, rt, rn), ctx); 1207 } 1208 break; 1209 case BPF_JEQ: 1210 case BPF_JNE: 1211 case BPF_JGT: 1212 case BPF_JGE: 1213 case BPF_JLE: 1214 case BPF_JLT: 1215 if (is_jmp64) { 1216 emit(ARM_CMP_R(rd, rm), ctx); 1217 /* Only compare low halve if high halve are equal. */ 1218 _emit(ARM_COND_EQ, ARM_CMP_R(rt, rn), ctx); 1219 } else { 1220 emit(ARM_CMP_R(rt, rn), ctx); 1221 } 1222 break; 1223 case BPF_JSLE: 1224 case BPF_JSGT: 1225 emit(ARM_CMP_R(rn, rt), ctx); 1226 if (is_jmp64) 1227 emit(ARM_SBCS_R(ARM_IP, rm, rd), ctx); 1228 break; 1229 case BPF_JSLT: 1230 case BPF_JSGE: 1231 emit(ARM_CMP_R(rt, rn), ctx); 1232 if (is_jmp64) 1233 emit(ARM_SBCS_R(ARM_IP, rd, rm), ctx); 1234 break; 1235 } 1236 } 1237 1238 static int out_offset = -1; /* initialized on the first pass of build_body() */ 1239 static int emit_bpf_tail_call(struct jit_ctx *ctx) 1240 { 1241 1242 /* bpf_tail_call(void *prog_ctx, struct bpf_array *array, u64 index) */ 1243 const s8 *r2 = bpf2a32[BPF_REG_2]; 1244 const s8 *r3 = bpf2a32[BPF_REG_3]; 1245 const s8 *tmp = bpf2a32[TMP_REG_1]; 1246 const s8 *tmp2 = bpf2a32[TMP_REG_2]; 1247 const s8 *tcc = bpf2a32[TCALL_CNT]; 1248 const s8 *tc; 1249 const int idx0 = ctx->idx; 1250 #define cur_offset (ctx->idx - idx0) 1251 #define jmp_offset (out_offset - (cur_offset) - 2) 1252 u32 lo, hi; 1253 s8 r_array, r_index; 1254 int off; 1255 1256 /* if (index >= array->map.max_entries) 1257 * goto out; 1258 */ 1259 BUILD_BUG_ON(offsetof(struct bpf_array, map.max_entries) > 1260 ARM_INST_LDST__IMM12); 1261 off = offsetof(struct bpf_array, map.max_entries); 1262 r_array = arm_bpf_get_reg32(r2[1], tmp2[0], ctx); 1263 /* index is 32-bit for arrays */ 1264 r_index = arm_bpf_get_reg32(r3[1], tmp2[1], ctx); 1265 /* array->map.max_entries */ 1266 emit(ARM_LDR_I(tmp[1], r_array, off), ctx); 1267 /* index >= array->map.max_entries */ 1268 emit(ARM_CMP_R(r_index, tmp[1]), ctx); 1269 _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx); 1270 1271 /* tmp2[0] = array, tmp2[1] = index */ 1272 1273 /* 1274 * if (tail_call_cnt >= MAX_TAIL_CALL_CNT) 1275 * goto out; 1276 * tail_call_cnt++; 1277 */ 1278 lo = (u32)MAX_TAIL_CALL_CNT; 1279 hi = (u32)((u64)MAX_TAIL_CALL_CNT >> 32); 1280 tc = arm_bpf_get_reg64(tcc, tmp, ctx); 1281 emit(ARM_CMP_I(tc[0], hi), ctx); 1282 _emit(ARM_COND_EQ, ARM_CMP_I(tc[1], lo), ctx); 1283 _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx); 1284 emit(ARM_ADDS_I(tc[1], tc[1], 1), ctx); 1285 emit(ARM_ADC_I(tc[0], tc[0], 0), ctx); 1286 arm_bpf_put_reg64(tcc, tmp, ctx); 1287 1288 /* prog = array->ptrs[index] 1289 * if (prog == NULL) 1290 * goto out; 1291 */ 1292 BUILD_BUG_ON(imm8m(offsetof(struct bpf_array, ptrs)) < 0); 1293 off = imm8m(offsetof(struct bpf_array, ptrs)); 1294 emit(ARM_ADD_I(tmp[1], r_array, off), ctx); 1295 emit(ARM_LDR_R_SI(tmp[1], tmp[1], r_index, SRTYPE_ASL, 2), ctx); 1296 emit(ARM_CMP_I(tmp[1], 0), ctx); 1297 _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx); 1298 1299 /* goto *(prog->bpf_func + prologue_size); */ 1300 BUILD_BUG_ON(offsetof(struct bpf_prog, bpf_func) > 1301 ARM_INST_LDST__IMM12); 1302 off = offsetof(struct bpf_prog, bpf_func); 1303 emit(ARM_LDR_I(tmp[1], tmp[1], off), ctx); 1304 emit(ARM_ADD_I(tmp[1], tmp[1], ctx->prologue_bytes), ctx); 1305 emit_bx_r(tmp[1], ctx); 1306 1307 /* out: */ 1308 if (out_offset == -1) 1309 out_offset = cur_offset; 1310 if (cur_offset != out_offset) { 1311 pr_err_once("tail_call out_offset = %d, expected %d!\n", 1312 cur_offset, out_offset); 1313 return -1; 1314 } 1315 return 0; 1316 #undef cur_offset 1317 #undef jmp_offset 1318 } 1319 1320 /* 0xabcd => 0xcdab */ 1321 static inline void emit_rev16(const u8 rd, const u8 rn, struct jit_ctx *ctx) 1322 { 1323 #if __LINUX_ARM_ARCH__ < 6 1324 const s8 *tmp2 = bpf2a32[TMP_REG_2]; 1325 1326 emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx); 1327 emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 8), ctx); 1328 emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx); 1329 emit(ARM_ORR_SI(rd, tmp2[0], tmp2[1], SRTYPE_LSL, 8), ctx); 1330 #else /* ARMv6+ */ 1331 emit(ARM_REV16(rd, rn), ctx); 1332 #endif 1333 } 1334 1335 /* 0xabcdefgh => 0xghefcdab */ 1336 static inline void emit_rev32(const u8 rd, const u8 rn, struct jit_ctx *ctx) 1337 { 1338 #if __LINUX_ARM_ARCH__ < 6 1339 const s8 *tmp2 = bpf2a32[TMP_REG_2]; 1340 1341 emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx); 1342 emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 24), ctx); 1343 emit(ARM_ORR_SI(ARM_IP, tmp2[0], tmp2[1], SRTYPE_LSL, 24), ctx); 1344 1345 emit(ARM_MOV_SI(tmp2[1], rn, SRTYPE_LSR, 8), ctx); 1346 emit(ARM_AND_I(tmp2[1], tmp2[1], 0xff), ctx); 1347 emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 16), ctx); 1348 emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx); 1349 emit(ARM_MOV_SI(tmp2[0], tmp2[0], SRTYPE_LSL, 8), ctx); 1350 emit(ARM_ORR_SI(tmp2[0], tmp2[0], tmp2[1], SRTYPE_LSL, 16), ctx); 1351 emit(ARM_ORR_R(rd, ARM_IP, tmp2[0]), ctx); 1352 1353 #else /* ARMv6+ */ 1354 emit(ARM_REV(rd, rn), ctx); 1355 #endif 1356 } 1357 1358 // push the scratch stack register on top of the stack 1359 static inline void emit_push_r64(const s8 src[], struct jit_ctx *ctx) 1360 { 1361 const s8 *tmp2 = bpf2a32[TMP_REG_2]; 1362 const s8 *rt; 1363 u16 reg_set = 0; 1364 1365 rt = arm_bpf_get_reg64(src, tmp2, ctx); 1366 1367 reg_set = (1 << rt[1]) | (1 << rt[0]); 1368 emit(ARM_PUSH(reg_set), ctx); 1369 } 1370 1371 static void build_prologue(struct jit_ctx *ctx) 1372 { 1373 const s8 arm_r0 = bpf2a32[BPF_REG_0][1]; 1374 const s8 *bpf_r1 = bpf2a32[BPF_REG_1]; 1375 const s8 *bpf_fp = bpf2a32[BPF_REG_FP]; 1376 const s8 *tcc = bpf2a32[TCALL_CNT]; 1377 1378 /* Save callee saved registers. */ 1379 #ifdef CONFIG_FRAME_POINTER 1380 u16 reg_set = CALLEE_PUSH_MASK | 1 << ARM_IP | 1 << ARM_PC; 1381 emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx); 1382 emit(ARM_PUSH(reg_set), ctx); 1383 emit(ARM_SUB_I(ARM_FP, ARM_IP, 4), ctx); 1384 #else 1385 emit(ARM_PUSH(CALLEE_PUSH_MASK), ctx); 1386 emit(ARM_MOV_R(ARM_FP, ARM_SP), ctx); 1387 #endif 1388 /* mov r3, #0 */ 1389 /* sub r2, sp, #SCRATCH_SIZE */ 1390 emit(ARM_MOV_I(bpf_r1[0], 0), ctx); 1391 emit(ARM_SUB_I(bpf_r1[1], ARM_SP, SCRATCH_SIZE), ctx); 1392 1393 ctx->stack_size = imm8m(STACK_SIZE); 1394 1395 /* Set up function call stack */ 1396 emit(ARM_SUB_I(ARM_SP, ARM_SP, ctx->stack_size), ctx); 1397 1398 /* Set up BPF prog stack base register */ 1399 emit_a32_mov_r64(true, bpf_fp, bpf_r1, ctx); 1400 1401 /* Initialize Tail Count */ 1402 emit(ARM_MOV_I(bpf_r1[1], 0), ctx); 1403 emit_a32_mov_r64(true, tcc, bpf_r1, ctx); 1404 1405 /* Move BPF_CTX to BPF_R1 */ 1406 emit(ARM_MOV_R(bpf_r1[1], arm_r0), ctx); 1407 1408 /* end of prologue */ 1409 } 1410 1411 /* restore callee saved registers. */ 1412 static void build_epilogue(struct jit_ctx *ctx) 1413 { 1414 #ifdef CONFIG_FRAME_POINTER 1415 /* When using frame pointers, some additional registers need to 1416 * be loaded. */ 1417 u16 reg_set = CALLEE_POP_MASK | 1 << ARM_SP; 1418 emit(ARM_SUB_I(ARM_SP, ARM_FP, hweight16(reg_set) * 4), ctx); 1419 emit(ARM_LDM(ARM_SP, reg_set), ctx); 1420 #else 1421 /* Restore callee saved registers. */ 1422 emit(ARM_MOV_R(ARM_SP, ARM_FP), ctx); 1423 emit(ARM_POP(CALLEE_POP_MASK), ctx); 1424 #endif 1425 } 1426 1427 /* 1428 * Convert an eBPF instruction to native instruction, i.e 1429 * JITs an eBPF instruction. 1430 * Returns : 1431 * 0 - Successfully JITed an 8-byte eBPF instruction 1432 * >0 - Successfully JITed a 16-byte eBPF instruction 1433 * <0 - Failed to JIT. 1434 */ 1435 static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx) 1436 { 1437 const u8 code = insn->code; 1438 const s8 *dst = bpf2a32[insn->dst_reg]; 1439 const s8 *src = bpf2a32[insn->src_reg]; 1440 const s8 *tmp = bpf2a32[TMP_REG_1]; 1441 const s8 *tmp2 = bpf2a32[TMP_REG_2]; 1442 const s16 off = insn->off; 1443 const s32 imm = insn->imm; 1444 const int i = insn - ctx->prog->insnsi; 1445 const bool is64 = BPF_CLASS(code) == BPF_ALU64; 1446 const s8 *rd, *rs; 1447 s8 rd_lo, rt, rm, rn; 1448 s32 jmp_offset; 1449 1450 #define check_imm(bits, imm) do { \ 1451 if ((imm) >= (1 << ((bits) - 1)) || \ 1452 (imm) < -(1 << ((bits) - 1))) { \ 1453 pr_info("[%2d] imm=%d(0x%x) out of range\n", \ 1454 i, imm, imm); \ 1455 return -EINVAL; \ 1456 } \ 1457 } while (0) 1458 #define check_imm24(imm) check_imm(24, imm) 1459 1460 switch (code) { 1461 /* ALU operations */ 1462 1463 /* dst = src */ 1464 case BPF_ALU | BPF_MOV | BPF_K: 1465 case BPF_ALU | BPF_MOV | BPF_X: 1466 case BPF_ALU64 | BPF_MOV | BPF_K: 1467 case BPF_ALU64 | BPF_MOV | BPF_X: 1468 switch (BPF_SRC(code)) { 1469 case BPF_X: 1470 if (imm == 1) { 1471 /* Special mov32 for zext */ 1472 emit_a32_mov_i(dst_hi, 0, ctx); 1473 break; 1474 } 1475 if (insn->off) 1476 emit_a32_movsx_r64(is64, insn->off, dst, src, ctx); 1477 else 1478 emit_a32_mov_r64(is64, dst, src, ctx); 1479 break; 1480 case BPF_K: 1481 /* Sign-extend immediate value to destination reg */ 1482 emit_a32_mov_se_i64(is64, dst, imm, ctx); 1483 break; 1484 } 1485 break; 1486 /* dst = dst + src/imm */ 1487 /* dst = dst - src/imm */ 1488 /* dst = dst | src/imm */ 1489 /* dst = dst & src/imm */ 1490 /* dst = dst ^ src/imm */ 1491 /* dst = dst * src/imm */ 1492 /* dst = dst << src */ 1493 /* dst = dst >> src */ 1494 case BPF_ALU | BPF_ADD | BPF_K: 1495 case BPF_ALU | BPF_ADD | BPF_X: 1496 case BPF_ALU | BPF_SUB | BPF_K: 1497 case BPF_ALU | BPF_SUB | BPF_X: 1498 case BPF_ALU | BPF_OR | BPF_K: 1499 case BPF_ALU | BPF_OR | BPF_X: 1500 case BPF_ALU | BPF_AND | BPF_K: 1501 case BPF_ALU | BPF_AND | BPF_X: 1502 case BPF_ALU | BPF_XOR | BPF_K: 1503 case BPF_ALU | BPF_XOR | BPF_X: 1504 case BPF_ALU | BPF_MUL | BPF_K: 1505 case BPF_ALU | BPF_MUL | BPF_X: 1506 case BPF_ALU | BPF_LSH | BPF_X: 1507 case BPF_ALU | BPF_RSH | BPF_X: 1508 case BPF_ALU | BPF_ARSH | BPF_X: 1509 case BPF_ALU64 | BPF_ADD | BPF_K: 1510 case BPF_ALU64 | BPF_ADD | BPF_X: 1511 case BPF_ALU64 | BPF_SUB | BPF_K: 1512 case BPF_ALU64 | BPF_SUB | BPF_X: 1513 case BPF_ALU64 | BPF_OR | BPF_K: 1514 case BPF_ALU64 | BPF_OR | BPF_X: 1515 case BPF_ALU64 | BPF_AND | BPF_K: 1516 case BPF_ALU64 | BPF_AND | BPF_X: 1517 case BPF_ALU64 | BPF_XOR | BPF_K: 1518 case BPF_ALU64 | BPF_XOR | BPF_X: 1519 switch (BPF_SRC(code)) { 1520 case BPF_X: 1521 emit_a32_alu_r64(is64, dst, src, ctx, BPF_OP(code)); 1522 break; 1523 case BPF_K: 1524 /* Move immediate value to the temporary register 1525 * and then do the ALU operation on the temporary 1526 * register as this will sign-extend the immediate 1527 * value into temporary reg and then it would be 1528 * safe to do the operation on it. 1529 */ 1530 emit_a32_mov_se_i64(is64, tmp2, imm, ctx); 1531 emit_a32_alu_r64(is64, dst, tmp2, ctx, BPF_OP(code)); 1532 break; 1533 } 1534 break; 1535 /* dst = dst / src(imm) */ 1536 /* dst = dst % src(imm) */ 1537 case BPF_ALU | BPF_DIV | BPF_K: 1538 case BPF_ALU | BPF_DIV | BPF_X: 1539 case BPF_ALU | BPF_MOD | BPF_K: 1540 case BPF_ALU | BPF_MOD | BPF_X: 1541 rd_lo = arm_bpf_get_reg32(dst_lo, tmp2[1], ctx); 1542 switch (BPF_SRC(code)) { 1543 case BPF_X: 1544 rt = arm_bpf_get_reg32(src_lo, tmp2[0], ctx); 1545 break; 1546 case BPF_K: 1547 rt = tmp2[0]; 1548 emit_a32_mov_i(rt, imm, ctx); 1549 break; 1550 default: 1551 rt = src_lo; 1552 break; 1553 } 1554 emit_udivmod(rd_lo, rd_lo, rt, ctx, BPF_OP(code)); 1555 arm_bpf_put_reg32(dst_lo, rd_lo, ctx); 1556 if (!ctx->prog->aux->verifier_zext) 1557 emit_a32_mov_i(dst_hi, 0, ctx); 1558 break; 1559 case BPF_ALU64 | BPF_DIV | BPF_K: 1560 case BPF_ALU64 | BPF_DIV | BPF_X: 1561 case BPF_ALU64 | BPF_MOD | BPF_K: 1562 case BPF_ALU64 | BPF_MOD | BPF_X: 1563 goto notyet; 1564 /* dst = dst << imm */ 1565 /* dst = dst >> imm */ 1566 /* dst = dst >> imm (signed) */ 1567 case BPF_ALU | BPF_LSH | BPF_K: 1568 case BPF_ALU | BPF_RSH | BPF_K: 1569 case BPF_ALU | BPF_ARSH | BPF_K: 1570 if (unlikely(imm > 31)) 1571 return -EINVAL; 1572 if (imm) 1573 emit_a32_alu_i(dst_lo, imm, ctx, BPF_OP(code)); 1574 if (!ctx->prog->aux->verifier_zext) 1575 emit_a32_mov_i(dst_hi, 0, ctx); 1576 break; 1577 /* dst = dst << imm */ 1578 case BPF_ALU64 | BPF_LSH | BPF_K: 1579 if (unlikely(imm > 63)) 1580 return -EINVAL; 1581 emit_a32_lsh_i64(dst, imm, ctx); 1582 break; 1583 /* dst = dst >> imm */ 1584 case BPF_ALU64 | BPF_RSH | BPF_K: 1585 if (unlikely(imm > 63)) 1586 return -EINVAL; 1587 emit_a32_rsh_i64(dst, imm, ctx); 1588 break; 1589 /* dst = dst << src */ 1590 case BPF_ALU64 | BPF_LSH | BPF_X: 1591 emit_a32_lsh_r64(dst, src, ctx); 1592 break; 1593 /* dst = dst >> src */ 1594 case BPF_ALU64 | BPF_RSH | BPF_X: 1595 emit_a32_rsh_r64(dst, src, ctx); 1596 break; 1597 /* dst = dst >> src (signed) */ 1598 case BPF_ALU64 | BPF_ARSH | BPF_X: 1599 emit_a32_arsh_r64(dst, src, ctx); 1600 break; 1601 /* dst = dst >> imm (signed) */ 1602 case BPF_ALU64 | BPF_ARSH | BPF_K: 1603 if (unlikely(imm > 63)) 1604 return -EINVAL; 1605 emit_a32_arsh_i64(dst, imm, ctx); 1606 break; 1607 /* dst = ~dst */ 1608 case BPF_ALU | BPF_NEG: 1609 emit_a32_alu_i(dst_lo, 0, ctx, BPF_OP(code)); 1610 if (!ctx->prog->aux->verifier_zext) 1611 emit_a32_mov_i(dst_hi, 0, ctx); 1612 break; 1613 /* dst = ~dst (64 bit) */ 1614 case BPF_ALU64 | BPF_NEG: 1615 emit_a32_neg64(dst, ctx); 1616 break; 1617 /* dst = dst * src/imm */ 1618 case BPF_ALU64 | BPF_MUL | BPF_X: 1619 case BPF_ALU64 | BPF_MUL | BPF_K: 1620 switch (BPF_SRC(code)) { 1621 case BPF_X: 1622 emit_a32_mul_r64(dst, src, ctx); 1623 break; 1624 case BPF_K: 1625 /* Move immediate value to the temporary register 1626 * and then do the multiplication on it as this 1627 * will sign-extend the immediate value into temp 1628 * reg then it would be safe to do the operation 1629 * on it. 1630 */ 1631 emit_a32_mov_se_i64(is64, tmp2, imm, ctx); 1632 emit_a32_mul_r64(dst, tmp2, ctx); 1633 break; 1634 } 1635 break; 1636 /* dst = htole(dst) */ 1637 /* dst = htobe(dst) */ 1638 case BPF_ALU | BPF_END | BPF_FROM_LE: /* also BPF_TO_LE */ 1639 case BPF_ALU | BPF_END | BPF_FROM_BE: /* also BPF_TO_BE */ 1640 /* dst = bswap(dst) */ 1641 case BPF_ALU64 | BPF_END | BPF_FROM_LE: /* also BPF_TO_LE */ 1642 rd = arm_bpf_get_reg64(dst, tmp, ctx); 1643 if (BPF_SRC(code) == BPF_FROM_LE && BPF_CLASS(code) != BPF_ALU64) 1644 goto emit_bswap_uxt; 1645 switch (imm) { 1646 case 16: 1647 emit_rev16(rd[1], rd[1], ctx); 1648 goto emit_bswap_uxt; 1649 case 32: 1650 emit_rev32(rd[1], rd[1], ctx); 1651 goto emit_bswap_uxt; 1652 case 64: 1653 emit_rev32(ARM_LR, rd[1], ctx); 1654 emit_rev32(rd[1], rd[0], ctx); 1655 emit(ARM_MOV_R(rd[0], ARM_LR), ctx); 1656 break; 1657 } 1658 goto exit; 1659 emit_bswap_uxt: 1660 switch (imm) { 1661 case 16: 1662 /* zero-extend 16 bits into 64 bits */ 1663 #if __LINUX_ARM_ARCH__ < 6 1664 emit_a32_mov_i(tmp2[1], 0xffff, ctx); 1665 emit(ARM_AND_R(rd[1], rd[1], tmp2[1]), ctx); 1666 #else /* ARMv6+ */ 1667 emit(ARM_UXTH(rd[1], rd[1]), ctx); 1668 #endif 1669 if (!ctx->prog->aux->verifier_zext) 1670 emit(ARM_EOR_R(rd[0], rd[0], rd[0]), ctx); 1671 break; 1672 case 32: 1673 /* zero-extend 32 bits into 64 bits */ 1674 if (!ctx->prog->aux->verifier_zext) 1675 emit(ARM_EOR_R(rd[0], rd[0], rd[0]), ctx); 1676 break; 1677 case 64: 1678 /* nop */ 1679 break; 1680 } 1681 exit: 1682 arm_bpf_put_reg64(dst, rd, ctx); 1683 break; 1684 /* dst = imm64 */ 1685 case BPF_LD | BPF_IMM | BPF_DW: 1686 { 1687 u64 val = (u32)imm | (u64)insn[1].imm << 32; 1688 1689 emit_a32_mov_i64(dst, val, ctx); 1690 1691 return 1; 1692 } 1693 /* LDX: dst = *(size *)(src + off) */ 1694 case BPF_LDX | BPF_MEM | BPF_W: 1695 case BPF_LDX | BPF_MEM | BPF_H: 1696 case BPF_LDX | BPF_MEM | BPF_B: 1697 case BPF_LDX | BPF_MEM | BPF_DW: 1698 /* LDSX: dst = *(signed size *)(src + off) */ 1699 case BPF_LDX | BPF_MEMSX | BPF_B: 1700 case BPF_LDX | BPF_MEMSX | BPF_H: 1701 case BPF_LDX | BPF_MEMSX | BPF_W: 1702 rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx); 1703 if (BPF_MODE(insn->code) == BPF_MEMSX) 1704 emit_ldsx_r(dst, rn, off, ctx, BPF_SIZE(code)); 1705 else 1706 emit_ldx_r(dst, rn, off, ctx, BPF_SIZE(code)); 1707 break; 1708 /* speculation barrier */ 1709 case BPF_ST | BPF_NOSPEC: 1710 break; 1711 /* ST: *(size *)(dst + off) = imm */ 1712 case BPF_ST | BPF_MEM | BPF_W: 1713 case BPF_ST | BPF_MEM | BPF_H: 1714 case BPF_ST | BPF_MEM | BPF_B: 1715 case BPF_ST | BPF_MEM | BPF_DW: 1716 switch (BPF_SIZE(code)) { 1717 case BPF_DW: 1718 /* Sign-extend immediate value into temp reg */ 1719 emit_a32_mov_se_i64(true, tmp2, imm, ctx); 1720 break; 1721 case BPF_W: 1722 case BPF_H: 1723 case BPF_B: 1724 emit_a32_mov_i(tmp2[1], imm, ctx); 1725 break; 1726 } 1727 emit_str_r(dst_lo, tmp2, off, ctx, BPF_SIZE(code)); 1728 break; 1729 /* Atomic ops */ 1730 case BPF_STX | BPF_ATOMIC | BPF_W: 1731 case BPF_STX | BPF_ATOMIC | BPF_DW: 1732 goto notyet; 1733 /* STX: *(size *)(dst + off) = src */ 1734 case BPF_STX | BPF_MEM | BPF_W: 1735 case BPF_STX | BPF_MEM | BPF_H: 1736 case BPF_STX | BPF_MEM | BPF_B: 1737 case BPF_STX | BPF_MEM | BPF_DW: 1738 rs = arm_bpf_get_reg64(src, tmp2, ctx); 1739 emit_str_r(dst_lo, rs, off, ctx, BPF_SIZE(code)); 1740 break; 1741 /* PC += off if dst == src */ 1742 /* PC += off if dst > src */ 1743 /* PC += off if dst >= src */ 1744 /* PC += off if dst < src */ 1745 /* PC += off if dst <= src */ 1746 /* PC += off if dst != src */ 1747 /* PC += off if dst > src (signed) */ 1748 /* PC += off if dst >= src (signed) */ 1749 /* PC += off if dst < src (signed) */ 1750 /* PC += off if dst <= src (signed) */ 1751 /* PC += off if dst & src */ 1752 case BPF_JMP | BPF_JEQ | BPF_X: 1753 case BPF_JMP | BPF_JGT | BPF_X: 1754 case BPF_JMP | BPF_JGE | BPF_X: 1755 case BPF_JMP | BPF_JNE | BPF_X: 1756 case BPF_JMP | BPF_JSGT | BPF_X: 1757 case BPF_JMP | BPF_JSGE | BPF_X: 1758 case BPF_JMP | BPF_JSET | BPF_X: 1759 case BPF_JMP | BPF_JLE | BPF_X: 1760 case BPF_JMP | BPF_JLT | BPF_X: 1761 case BPF_JMP | BPF_JSLT | BPF_X: 1762 case BPF_JMP | BPF_JSLE | BPF_X: 1763 case BPF_JMP32 | BPF_JEQ | BPF_X: 1764 case BPF_JMP32 | BPF_JGT | BPF_X: 1765 case BPF_JMP32 | BPF_JGE | BPF_X: 1766 case BPF_JMP32 | BPF_JNE | BPF_X: 1767 case BPF_JMP32 | BPF_JSGT | BPF_X: 1768 case BPF_JMP32 | BPF_JSGE | BPF_X: 1769 case BPF_JMP32 | BPF_JSET | BPF_X: 1770 case BPF_JMP32 | BPF_JLE | BPF_X: 1771 case BPF_JMP32 | BPF_JLT | BPF_X: 1772 case BPF_JMP32 | BPF_JSLT | BPF_X: 1773 case BPF_JMP32 | BPF_JSLE | BPF_X: 1774 /* Setup source registers */ 1775 rm = arm_bpf_get_reg32(src_hi, tmp2[0], ctx); 1776 rn = arm_bpf_get_reg32(src_lo, tmp2[1], ctx); 1777 goto go_jmp; 1778 /* PC += off if dst == imm */ 1779 /* PC += off if dst > imm */ 1780 /* PC += off if dst >= imm */ 1781 /* PC += off if dst < imm */ 1782 /* PC += off if dst <= imm */ 1783 /* PC += off if dst != imm */ 1784 /* PC += off if dst > imm (signed) */ 1785 /* PC += off if dst >= imm (signed) */ 1786 /* PC += off if dst < imm (signed) */ 1787 /* PC += off if dst <= imm (signed) */ 1788 /* PC += off if dst & imm */ 1789 case BPF_JMP | BPF_JEQ | BPF_K: 1790 case BPF_JMP | BPF_JGT | BPF_K: 1791 case BPF_JMP | BPF_JGE | BPF_K: 1792 case BPF_JMP | BPF_JNE | BPF_K: 1793 case BPF_JMP | BPF_JSGT | BPF_K: 1794 case BPF_JMP | BPF_JSGE | BPF_K: 1795 case BPF_JMP | BPF_JSET | BPF_K: 1796 case BPF_JMP | BPF_JLT | BPF_K: 1797 case BPF_JMP | BPF_JLE | BPF_K: 1798 case BPF_JMP | BPF_JSLT | BPF_K: 1799 case BPF_JMP | BPF_JSLE | BPF_K: 1800 case BPF_JMP32 | BPF_JEQ | BPF_K: 1801 case BPF_JMP32 | BPF_JGT | BPF_K: 1802 case BPF_JMP32 | BPF_JGE | BPF_K: 1803 case BPF_JMP32 | BPF_JNE | BPF_K: 1804 case BPF_JMP32 | BPF_JSGT | BPF_K: 1805 case BPF_JMP32 | BPF_JSGE | BPF_K: 1806 case BPF_JMP32 | BPF_JSET | BPF_K: 1807 case BPF_JMP32 | BPF_JLT | BPF_K: 1808 case BPF_JMP32 | BPF_JLE | BPF_K: 1809 case BPF_JMP32 | BPF_JSLT | BPF_K: 1810 case BPF_JMP32 | BPF_JSLE | BPF_K: 1811 if (off == 0) 1812 break; 1813 rm = tmp2[0]; 1814 rn = tmp2[1]; 1815 /* Sign-extend immediate value */ 1816 emit_a32_mov_se_i64(true, tmp2, imm, ctx); 1817 go_jmp: 1818 /* Setup destination register */ 1819 rd = arm_bpf_get_reg64(dst, tmp, ctx); 1820 1821 /* Check for the condition */ 1822 emit_ar_r(rd[0], rd[1], rm, rn, ctx, BPF_OP(code), 1823 BPF_CLASS(code) == BPF_JMP); 1824 1825 /* Setup JUMP instruction */ 1826 jmp_offset = bpf2a32_offset(i+off, i, ctx); 1827 switch (BPF_OP(code)) { 1828 case BPF_JNE: 1829 case BPF_JSET: 1830 _emit(ARM_COND_NE, ARM_B(jmp_offset), ctx); 1831 break; 1832 case BPF_JEQ: 1833 _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx); 1834 break; 1835 case BPF_JGT: 1836 _emit(ARM_COND_HI, ARM_B(jmp_offset), ctx); 1837 break; 1838 case BPF_JGE: 1839 _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx); 1840 break; 1841 case BPF_JSGT: 1842 _emit(ARM_COND_LT, ARM_B(jmp_offset), ctx); 1843 break; 1844 case BPF_JSGE: 1845 _emit(ARM_COND_GE, ARM_B(jmp_offset), ctx); 1846 break; 1847 case BPF_JLE: 1848 _emit(ARM_COND_LS, ARM_B(jmp_offset), ctx); 1849 break; 1850 case BPF_JLT: 1851 _emit(ARM_COND_CC, ARM_B(jmp_offset), ctx); 1852 break; 1853 case BPF_JSLT: 1854 _emit(ARM_COND_LT, ARM_B(jmp_offset), ctx); 1855 break; 1856 case BPF_JSLE: 1857 _emit(ARM_COND_GE, ARM_B(jmp_offset), ctx); 1858 break; 1859 } 1860 break; 1861 /* JMP OFF */ 1862 case BPF_JMP | BPF_JA: 1863 case BPF_JMP32 | BPF_JA: 1864 { 1865 if (BPF_CLASS(code) == BPF_JMP32 && imm != 0) 1866 jmp_offset = bpf2a32_offset(i + imm, i, ctx); 1867 else if (BPF_CLASS(code) == BPF_JMP && off != 0) 1868 jmp_offset = bpf2a32_offset(i + off, i, ctx); 1869 else 1870 break; 1871 1872 check_imm24(jmp_offset); 1873 emit(ARM_B(jmp_offset), ctx); 1874 break; 1875 } 1876 /* tail call */ 1877 case BPF_JMP | BPF_TAIL_CALL: 1878 if (emit_bpf_tail_call(ctx)) 1879 return -EFAULT; 1880 break; 1881 /* function call */ 1882 case BPF_JMP | BPF_CALL: 1883 { 1884 const s8 *r0 = bpf2a32[BPF_REG_0]; 1885 const s8 *r1 = bpf2a32[BPF_REG_1]; 1886 const s8 *r2 = bpf2a32[BPF_REG_2]; 1887 const s8 *r3 = bpf2a32[BPF_REG_3]; 1888 const s8 *r4 = bpf2a32[BPF_REG_4]; 1889 const s8 *r5 = bpf2a32[BPF_REG_5]; 1890 const u32 func = (u32)__bpf_call_base + (u32)imm; 1891 1892 emit_a32_mov_r64(true, r0, r1, ctx); 1893 emit_a32_mov_r64(true, r1, r2, ctx); 1894 emit_push_r64(r5, ctx); 1895 emit_push_r64(r4, ctx); 1896 emit_push_r64(r3, ctx); 1897 1898 emit_a32_mov_i(tmp[1], func, ctx); 1899 emit_blx_r(tmp[1], ctx); 1900 1901 emit(ARM_ADD_I(ARM_SP, ARM_SP, imm8m(24)), ctx); // callee clean 1902 break; 1903 } 1904 /* function return */ 1905 case BPF_JMP | BPF_EXIT: 1906 /* Optimization: when last instruction is EXIT 1907 * simply fallthrough to epilogue. 1908 */ 1909 if (i == ctx->prog->len - 1) 1910 break; 1911 jmp_offset = epilogue_offset(ctx); 1912 check_imm24(jmp_offset); 1913 emit(ARM_B(jmp_offset), ctx); 1914 break; 1915 notyet: 1916 pr_info_once("*** NOT YET: opcode %02x ***\n", code); 1917 return -EFAULT; 1918 default: 1919 pr_err_once("unknown opcode %02x\n", code); 1920 return -EINVAL; 1921 } 1922 1923 if (ctx->flags & FLAG_IMM_OVERFLOW) 1924 /* 1925 * this instruction generated an overflow when 1926 * trying to access the literal pool, so 1927 * delegate this filter to the kernel interpreter. 1928 */ 1929 return -1; 1930 return 0; 1931 } 1932 1933 static int build_body(struct jit_ctx *ctx) 1934 { 1935 const struct bpf_prog *prog = ctx->prog; 1936 unsigned int i; 1937 1938 for (i = 0; i < prog->len; i++) { 1939 const struct bpf_insn *insn = &(prog->insnsi[i]); 1940 int ret; 1941 1942 ret = build_insn(insn, ctx); 1943 1944 /* It's used with loading the 64 bit immediate value. */ 1945 if (ret > 0) { 1946 i++; 1947 if (ctx->target == NULL) 1948 ctx->offsets[i] = ctx->idx; 1949 continue; 1950 } 1951 1952 if (ctx->target == NULL) 1953 ctx->offsets[i] = ctx->idx; 1954 1955 /* If unsuccesful, return with error code */ 1956 if (ret) 1957 return ret; 1958 } 1959 return 0; 1960 } 1961 1962 static int validate_code(struct jit_ctx *ctx) 1963 { 1964 int i; 1965 1966 for (i = 0; i < ctx->idx; i++) { 1967 if (ctx->target[i] == __opcode_to_mem_arm(ARM_INST_UDF)) 1968 return -1; 1969 } 1970 1971 return 0; 1972 } 1973 1974 bool bpf_jit_needs_zext(void) 1975 { 1976 return true; 1977 } 1978 1979 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) 1980 { 1981 struct bpf_prog *tmp, *orig_prog = prog; 1982 struct bpf_binary_header *header; 1983 bool tmp_blinded = false; 1984 struct jit_ctx ctx; 1985 unsigned int tmp_idx; 1986 unsigned int image_size; 1987 u8 *image_ptr; 1988 1989 /* If BPF JIT was not enabled then we must fall back to 1990 * the interpreter. 1991 */ 1992 if (!prog->jit_requested) 1993 return orig_prog; 1994 1995 /* If constant blinding was enabled and we failed during blinding 1996 * then we must fall back to the interpreter. Otherwise, we save 1997 * the new JITed code. 1998 */ 1999 tmp = bpf_jit_blind_constants(prog); 2000 2001 if (IS_ERR(tmp)) 2002 return orig_prog; 2003 if (tmp != prog) { 2004 tmp_blinded = true; 2005 prog = tmp; 2006 } 2007 2008 memset(&ctx, 0, sizeof(ctx)); 2009 ctx.prog = prog; 2010 ctx.cpu_architecture = cpu_architecture(); 2011 2012 /* Not able to allocate memory for offsets[] , then 2013 * we must fall back to the interpreter 2014 */ 2015 ctx.offsets = kcalloc(prog->len, sizeof(int), GFP_KERNEL); 2016 if (ctx.offsets == NULL) { 2017 prog = orig_prog; 2018 goto out; 2019 } 2020 2021 /* 1) fake pass to find in the length of the JITed code, 2022 * to compute ctx->offsets and other context variables 2023 * needed to compute final JITed code. 2024 * Also, calculate random starting pointer/start of JITed code 2025 * which is prefixed by random number of fault instructions. 2026 * 2027 * If the first pass fails then there is no chance of it 2028 * being successful in the second pass, so just fall back 2029 * to the interpreter. 2030 */ 2031 if (build_body(&ctx)) { 2032 prog = orig_prog; 2033 goto out_off; 2034 } 2035 2036 tmp_idx = ctx.idx; 2037 build_prologue(&ctx); 2038 ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4; 2039 2040 ctx.epilogue_offset = ctx.idx; 2041 2042 #if __LINUX_ARM_ARCH__ < 7 2043 tmp_idx = ctx.idx; 2044 build_epilogue(&ctx); 2045 ctx.epilogue_bytes = (ctx.idx - tmp_idx) * 4; 2046 2047 ctx.idx += ctx.imm_count; 2048 if (ctx.imm_count) { 2049 ctx.imms = kcalloc(ctx.imm_count, sizeof(u32), GFP_KERNEL); 2050 if (ctx.imms == NULL) { 2051 prog = orig_prog; 2052 goto out_off; 2053 } 2054 } 2055 #else 2056 /* there's nothing about the epilogue on ARMv7 */ 2057 build_epilogue(&ctx); 2058 #endif 2059 /* Now we can get the actual image size of the JITed arm code. 2060 * Currently, we are not considering the THUMB-2 instructions 2061 * for jit, although it can decrease the size of the image. 2062 * 2063 * As each arm instruction is of length 32bit, we are translating 2064 * number of JITed instructions into the size required to store these 2065 * JITed code. 2066 */ 2067 image_size = sizeof(u32) * ctx.idx; 2068 2069 /* Now we know the size of the structure to make */ 2070 header = bpf_jit_binary_alloc(image_size, &image_ptr, 2071 sizeof(u32), jit_fill_hole); 2072 /* Not able to allocate memory for the structure then 2073 * we must fall back to the interpretation 2074 */ 2075 if (header == NULL) { 2076 prog = orig_prog; 2077 goto out_imms; 2078 } 2079 2080 /* 2.) Actual pass to generate final JIT code */ 2081 ctx.target = (u32 *) image_ptr; 2082 ctx.idx = 0; 2083 2084 build_prologue(&ctx); 2085 2086 /* If building the body of the JITed code fails somehow, 2087 * we fall back to the interpretation. 2088 */ 2089 if (build_body(&ctx) < 0) { 2090 image_ptr = NULL; 2091 bpf_jit_binary_free(header); 2092 prog = orig_prog; 2093 goto out_imms; 2094 } 2095 build_epilogue(&ctx); 2096 2097 /* 3.) Extra pass to validate JITed Code */ 2098 if (validate_code(&ctx)) { 2099 image_ptr = NULL; 2100 bpf_jit_binary_free(header); 2101 prog = orig_prog; 2102 goto out_imms; 2103 } 2104 flush_icache_range((u32)header, (u32)(ctx.target + ctx.idx)); 2105 2106 if (bpf_jit_enable > 1) 2107 /* there are 2 passes here */ 2108 bpf_jit_dump(prog->len, image_size, 2, ctx.target); 2109 2110 bpf_jit_binary_lock_ro(header); 2111 prog->bpf_func = (void *)ctx.target; 2112 prog->jited = 1; 2113 prog->jited_len = image_size; 2114 2115 out_imms: 2116 #if __LINUX_ARM_ARCH__ < 7 2117 if (ctx.imm_count) 2118 kfree(ctx.imms); 2119 #endif 2120 out_off: 2121 kfree(ctx.offsets); 2122 out: 2123 if (tmp_blinded) 2124 bpf_jit_prog_release_other(prog, prog == orig_prog ? 2125 tmp : orig_prog); 2126 return prog; 2127 } 2128 2129