1 /* 2 * Just-In-Time compiler for eBPF filters on 32bit ARM 3 * 4 * Copyright (c) 2017 Shubham Bansal <illusionist.neo@gmail.com> 5 * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; version 2 of the License. 10 */ 11 12 #include <linux/bpf.h> 13 #include <linux/bitops.h> 14 #include <linux/compiler.h> 15 #include <linux/errno.h> 16 #include <linux/filter.h> 17 #include <linux/netdevice.h> 18 #include <linux/string.h> 19 #include <linux/slab.h> 20 #include <linux/if_vlan.h> 21 22 #include <asm/cacheflush.h> 23 #include <asm/hwcap.h> 24 #include <asm/opcodes.h> 25 26 #include "bpf_jit_32.h" 27 28 int bpf_jit_enable __read_mostly; 29 30 /* 31 * eBPF prog stack layout: 32 * 33 * high 34 * original ARM_SP => +-----+ 35 * | | callee saved registers 36 * +-----+ <= (BPF_FP + SCRATCH_SIZE) 37 * | ... | eBPF JIT scratch space 38 * eBPF fp register => +-----+ 39 * (BPF_FP) | ... | eBPF prog stack 40 * +-----+ 41 * |RSVD | JIT scratchpad 42 * current ARM_SP => +-----+ <= (BPF_FP - STACK_SIZE + SCRATCH_SIZE) 43 * | | 44 * | ... | Function call stack 45 * | | 46 * +-----+ 47 * low 48 * 49 * The callee saved registers depends on whether frame pointers are enabled. 50 * With frame pointers (to be compliant with the ABI): 51 * 52 * high 53 * original ARM_SP => +------------------+ \ 54 * | pc | | 55 * current ARM_FP => +------------------+ } callee saved registers 56 * |r4-r8,r10,fp,ip,lr| | 57 * +------------------+ / 58 * low 59 * 60 * Without frame pointers: 61 * 62 * high 63 * original ARM_SP => +------------------+ 64 * | r4-r8,r10,fp,lr | callee saved registers 65 * current ARM_FP => +------------------+ 66 * low 67 * 68 * When popping registers off the stack at the end of a BPF function, we 69 * reference them via the current ARM_FP register. 70 */ 71 #define CALLEE_MASK (1 << ARM_R4 | 1 << ARM_R5 | 1 << ARM_R6 | \ 72 1 << ARM_R7 | 1 << ARM_R8 | 1 << ARM_R10 | \ 73 1 << ARM_FP) 74 #define CALLEE_PUSH_MASK (CALLEE_MASK | 1 << ARM_LR) 75 #define CALLEE_POP_MASK (CALLEE_MASK | 1 << ARM_PC) 76 77 #define STACK_OFFSET(k) (k) 78 #define TMP_REG_1 (MAX_BPF_JIT_REG + 0) /* TEMP Register 1 */ 79 #define TMP_REG_2 (MAX_BPF_JIT_REG + 1) /* TEMP Register 2 */ 80 #define TCALL_CNT (MAX_BPF_JIT_REG + 2) /* Tail Call Count */ 81 82 #define FLAG_IMM_OVERFLOW (1 << 0) 83 84 /* 85 * Map eBPF registers to ARM 32bit registers or stack scratch space. 86 * 87 * 1. First argument is passed using the arm 32bit registers and rest of the 88 * arguments are passed on stack scratch space. 89 * 2. First callee-saved arugument is mapped to arm 32 bit registers and rest 90 * arguments are mapped to scratch space on stack. 91 * 3. We need two 64 bit temp registers to do complex operations on eBPF 92 * registers. 93 * 94 * As the eBPF registers are all 64 bit registers and arm has only 32 bit 95 * registers, we have to map each eBPF registers with two arm 32 bit regs or 96 * scratch memory space and we have to build eBPF 64 bit register from those. 97 * 98 */ 99 static const u8 bpf2a32[][2] = { 100 /* return value from in-kernel function, and exit value from eBPF */ 101 [BPF_REG_0] = {ARM_R1, ARM_R0}, 102 /* arguments from eBPF program to in-kernel function */ 103 [BPF_REG_1] = {ARM_R3, ARM_R2}, 104 /* Stored on stack scratch space */ 105 [BPF_REG_2] = {STACK_OFFSET(0), STACK_OFFSET(4)}, 106 [BPF_REG_3] = {STACK_OFFSET(8), STACK_OFFSET(12)}, 107 [BPF_REG_4] = {STACK_OFFSET(16), STACK_OFFSET(20)}, 108 [BPF_REG_5] = {STACK_OFFSET(24), STACK_OFFSET(28)}, 109 /* callee saved registers that in-kernel function will preserve */ 110 [BPF_REG_6] = {ARM_R5, ARM_R4}, 111 /* Stored on stack scratch space */ 112 [BPF_REG_7] = {STACK_OFFSET(32), STACK_OFFSET(36)}, 113 [BPF_REG_8] = {STACK_OFFSET(40), STACK_OFFSET(44)}, 114 [BPF_REG_9] = {STACK_OFFSET(48), STACK_OFFSET(52)}, 115 /* Read only Frame Pointer to access Stack */ 116 [BPF_REG_FP] = {STACK_OFFSET(56), STACK_OFFSET(60)}, 117 /* Temporary Register for internal BPF JIT, can be used 118 * for constant blindings and others. 119 */ 120 [TMP_REG_1] = {ARM_R7, ARM_R6}, 121 [TMP_REG_2] = {ARM_R10, ARM_R8}, 122 /* Tail call count. Stored on stack scratch space. */ 123 [TCALL_CNT] = {STACK_OFFSET(64), STACK_OFFSET(68)}, 124 /* temporary register for blinding constants. 125 * Stored on stack scratch space. 126 */ 127 [BPF_REG_AX] = {STACK_OFFSET(72), STACK_OFFSET(76)}, 128 }; 129 130 #define dst_lo dst[1] 131 #define dst_hi dst[0] 132 #define src_lo src[1] 133 #define src_hi src[0] 134 135 /* 136 * JIT Context: 137 * 138 * prog : bpf_prog 139 * idx : index of current last JITed instruction. 140 * prologue_bytes : bytes used in prologue. 141 * epilogue_offset : offset of epilogue starting. 142 * offsets : array of eBPF instruction offsets in 143 * JITed code. 144 * target : final JITed code. 145 * epilogue_bytes : no of bytes used in epilogue. 146 * imm_count : no of immediate counts used for global 147 * variables. 148 * imms : array of global variable addresses. 149 */ 150 151 struct jit_ctx { 152 const struct bpf_prog *prog; 153 unsigned int idx; 154 unsigned int prologue_bytes; 155 unsigned int epilogue_offset; 156 u32 flags; 157 u32 *offsets; 158 u32 *target; 159 u32 stack_size; 160 #if __LINUX_ARM_ARCH__ < 7 161 u16 epilogue_bytes; 162 u16 imm_count; 163 u32 *imms; 164 #endif 165 }; 166 167 /* 168 * Wrappers which handle both OABI and EABI and assures Thumb2 interworking 169 * (where the assembly routines like __aeabi_uidiv could cause problems). 170 */ 171 static u32 jit_udiv32(u32 dividend, u32 divisor) 172 { 173 return dividend / divisor; 174 } 175 176 static u32 jit_mod32(u32 dividend, u32 divisor) 177 { 178 return dividend % divisor; 179 } 180 181 static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx) 182 { 183 inst |= (cond << 28); 184 inst = __opcode_to_mem_arm(inst); 185 186 if (ctx->target != NULL) 187 ctx->target[ctx->idx] = inst; 188 189 ctx->idx++; 190 } 191 192 /* 193 * Emit an instruction that will be executed unconditionally. 194 */ 195 static inline void emit(u32 inst, struct jit_ctx *ctx) 196 { 197 _emit(ARM_COND_AL, inst, ctx); 198 } 199 200 /* 201 * Checks if immediate value can be converted to imm12(12 bits) value. 202 */ 203 static int16_t imm8m(u32 x) 204 { 205 u32 rot; 206 207 for (rot = 0; rot < 16; rot++) 208 if ((x & ~ror32(0xff, 2 * rot)) == 0) 209 return rol32(x, 2 * rot) | (rot << 8); 210 return -1; 211 } 212 213 /* 214 * Initializes the JIT space with undefined instructions. 215 */ 216 static void jit_fill_hole(void *area, unsigned int size) 217 { 218 u32 *ptr; 219 /* We are guaranteed to have aligned memory. */ 220 for (ptr = area; size >= sizeof(u32); size -= sizeof(u32)) 221 *ptr++ = __opcode_to_mem_arm(ARM_INST_UDF); 222 } 223 224 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) 225 /* EABI requires the stack to be aligned to 64-bit boundaries */ 226 #define STACK_ALIGNMENT 8 227 #else 228 /* Stack must be aligned to 32-bit boundaries */ 229 #define STACK_ALIGNMENT 4 230 #endif 231 232 /* Stack space for BPF_REG_2, BPF_REG_3, BPF_REG_4, 233 * BPF_REG_5, BPF_REG_7, BPF_REG_8, BPF_REG_9, 234 * BPF_REG_FP and Tail call counts. 235 */ 236 #define SCRATCH_SIZE 80 237 238 /* total stack size used in JITed code */ 239 #define _STACK_SIZE \ 240 (ctx->prog->aux->stack_depth + \ 241 + SCRATCH_SIZE + \ 242 + 4 /* extra for skb_copy_bits buffer */) 243 244 #define STACK_SIZE ALIGN(_STACK_SIZE, STACK_ALIGNMENT) 245 246 /* Get the offset of eBPF REGISTERs stored on scratch space. */ 247 #define STACK_VAR(off) (STACK_SIZE-off-4) 248 249 /* Offset of skb_copy_bits buffer */ 250 #define SKB_BUFFER STACK_VAR(SCRATCH_SIZE) 251 252 #if __LINUX_ARM_ARCH__ < 7 253 254 static u16 imm_offset(u32 k, struct jit_ctx *ctx) 255 { 256 unsigned int i = 0, offset; 257 u16 imm; 258 259 /* on the "fake" run we just count them (duplicates included) */ 260 if (ctx->target == NULL) { 261 ctx->imm_count++; 262 return 0; 263 } 264 265 while ((i < ctx->imm_count) && ctx->imms[i]) { 266 if (ctx->imms[i] == k) 267 break; 268 i++; 269 } 270 271 if (ctx->imms[i] == 0) 272 ctx->imms[i] = k; 273 274 /* constants go just after the epilogue */ 275 offset = ctx->offsets[ctx->prog->len - 1] * 4; 276 offset += ctx->prologue_bytes; 277 offset += ctx->epilogue_bytes; 278 offset += i * 4; 279 280 ctx->target[offset / 4] = k; 281 282 /* PC in ARM mode == address of the instruction + 8 */ 283 imm = offset - (8 + ctx->idx * 4); 284 285 if (imm & ~0xfff) { 286 /* 287 * literal pool is too far, signal it into flags. we 288 * can only detect it on the second pass unfortunately. 289 */ 290 ctx->flags |= FLAG_IMM_OVERFLOW; 291 return 0; 292 } 293 294 return imm; 295 } 296 297 #endif /* __LINUX_ARM_ARCH__ */ 298 299 static inline int bpf2a32_offset(int bpf_to, int bpf_from, 300 const struct jit_ctx *ctx) { 301 int to, from; 302 303 if (ctx->target == NULL) 304 return 0; 305 to = ctx->offsets[bpf_to]; 306 from = ctx->offsets[bpf_from]; 307 308 return to - from - 1; 309 } 310 311 /* 312 * Move an immediate that's not an imm8m to a core register. 313 */ 314 static inline void emit_mov_i_no8m(const u8 rd, u32 val, struct jit_ctx *ctx) 315 { 316 #if __LINUX_ARM_ARCH__ < 7 317 emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx); 318 #else 319 emit(ARM_MOVW(rd, val & 0xffff), ctx); 320 if (val > 0xffff) 321 emit(ARM_MOVT(rd, val >> 16), ctx); 322 #endif 323 } 324 325 static inline void emit_mov_i(const u8 rd, u32 val, struct jit_ctx *ctx) 326 { 327 int imm12 = imm8m(val); 328 329 if (imm12 >= 0) 330 emit(ARM_MOV_I(rd, imm12), ctx); 331 else 332 emit_mov_i_no8m(rd, val, ctx); 333 } 334 335 static void emit_bx_r(u8 tgt_reg, struct jit_ctx *ctx) 336 { 337 if (elf_hwcap & HWCAP_THUMB) 338 emit(ARM_BX(tgt_reg), ctx); 339 else 340 emit(ARM_MOV_R(ARM_PC, tgt_reg), ctx); 341 } 342 343 static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx) 344 { 345 #if __LINUX_ARM_ARCH__ < 5 346 emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx); 347 emit_bx_r(tgt_reg, ctx); 348 #else 349 emit(ARM_BLX_R(tgt_reg), ctx); 350 #endif 351 } 352 353 static inline int epilogue_offset(const struct jit_ctx *ctx) 354 { 355 int to, from; 356 /* No need for 1st dummy run */ 357 if (ctx->target == NULL) 358 return 0; 359 to = ctx->epilogue_offset; 360 from = ctx->idx; 361 362 return to - from - 2; 363 } 364 365 static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op) 366 { 367 const u8 *tmp = bpf2a32[TMP_REG_1]; 368 s32 jmp_offset; 369 370 /* checks if divisor is zero or not. If it is, then 371 * exit directly. 372 */ 373 emit(ARM_CMP_I(rn, 0), ctx); 374 _emit(ARM_COND_EQ, ARM_MOV_I(ARM_R0, 0), ctx); 375 jmp_offset = epilogue_offset(ctx); 376 _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx); 377 #if __LINUX_ARM_ARCH__ == 7 378 if (elf_hwcap & HWCAP_IDIVA) { 379 if (op == BPF_DIV) 380 emit(ARM_UDIV(rd, rm, rn), ctx); 381 else { 382 emit(ARM_UDIV(ARM_IP, rm, rn), ctx); 383 emit(ARM_MLS(rd, rn, ARM_IP, rm), ctx); 384 } 385 return; 386 } 387 #endif 388 389 /* 390 * For BPF_ALU | BPF_DIV | BPF_K instructions 391 * As ARM_R1 and ARM_R0 contains 1st argument of bpf 392 * function, we need to save it on caller side to save 393 * it from getting destroyed within callee. 394 * After the return from the callee, we restore ARM_R0 395 * ARM_R1. 396 */ 397 if (rn != ARM_R1) { 398 emit(ARM_MOV_R(tmp[0], ARM_R1), ctx); 399 emit(ARM_MOV_R(ARM_R1, rn), ctx); 400 } 401 if (rm != ARM_R0) { 402 emit(ARM_MOV_R(tmp[1], ARM_R0), ctx); 403 emit(ARM_MOV_R(ARM_R0, rm), ctx); 404 } 405 406 /* Call appropriate function */ 407 emit_mov_i(ARM_IP, op == BPF_DIV ? 408 (u32)jit_udiv32 : (u32)jit_mod32, ctx); 409 emit_blx_r(ARM_IP, ctx); 410 411 /* Save return value */ 412 if (rd != ARM_R0) 413 emit(ARM_MOV_R(rd, ARM_R0), ctx); 414 415 /* Restore ARM_R0 and ARM_R1 */ 416 if (rn != ARM_R1) 417 emit(ARM_MOV_R(ARM_R1, tmp[0]), ctx); 418 if (rm != ARM_R0) 419 emit(ARM_MOV_R(ARM_R0, tmp[1]), ctx); 420 } 421 422 /* Checks whether BPF register is on scratch stack space or not. */ 423 static inline bool is_on_stack(u8 bpf_reg) 424 { 425 static u8 stack_regs[] = {BPF_REG_AX, BPF_REG_3, BPF_REG_4, BPF_REG_5, 426 BPF_REG_7, BPF_REG_8, BPF_REG_9, TCALL_CNT, 427 BPF_REG_2, BPF_REG_FP}; 428 int i, reg_len = sizeof(stack_regs); 429 430 for (i = 0 ; i < reg_len ; i++) { 431 if (bpf_reg == stack_regs[i]) 432 return true; 433 } 434 return false; 435 } 436 437 static inline void emit_a32_mov_i(const u8 dst, const u32 val, 438 bool dstk, struct jit_ctx *ctx) 439 { 440 const u8 *tmp = bpf2a32[TMP_REG_1]; 441 442 if (dstk) { 443 emit_mov_i(tmp[1], val, ctx); 444 emit(ARM_STR_I(tmp[1], ARM_SP, STACK_VAR(dst)), ctx); 445 } else { 446 emit_mov_i(dst, val, ctx); 447 } 448 } 449 450 /* Sign extended move */ 451 static inline void emit_a32_mov_i64(const bool is64, const u8 dst[], 452 const u32 val, bool dstk, 453 struct jit_ctx *ctx) { 454 u32 hi = 0; 455 456 if (is64 && (val & (1<<31))) 457 hi = (u32)~0; 458 emit_a32_mov_i(dst_lo, val, dstk, ctx); 459 emit_a32_mov_i(dst_hi, hi, dstk, ctx); 460 } 461 462 static inline void emit_a32_add_r(const u8 dst, const u8 src, 463 const bool is64, const bool hi, 464 struct jit_ctx *ctx) { 465 /* 64 bit : 466 * adds dst_lo, dst_lo, src_lo 467 * adc dst_hi, dst_hi, src_hi 468 * 32 bit : 469 * add dst_lo, dst_lo, src_lo 470 */ 471 if (!hi && is64) 472 emit(ARM_ADDS_R(dst, dst, src), ctx); 473 else if (hi && is64) 474 emit(ARM_ADC_R(dst, dst, src), ctx); 475 else 476 emit(ARM_ADD_R(dst, dst, src), ctx); 477 } 478 479 static inline void emit_a32_sub_r(const u8 dst, const u8 src, 480 const bool is64, const bool hi, 481 struct jit_ctx *ctx) { 482 /* 64 bit : 483 * subs dst_lo, dst_lo, src_lo 484 * sbc dst_hi, dst_hi, src_hi 485 * 32 bit : 486 * sub dst_lo, dst_lo, src_lo 487 */ 488 if (!hi && is64) 489 emit(ARM_SUBS_R(dst, dst, src), ctx); 490 else if (hi && is64) 491 emit(ARM_SBC_R(dst, dst, src), ctx); 492 else 493 emit(ARM_SUB_R(dst, dst, src), ctx); 494 } 495 496 static inline void emit_alu_r(const u8 dst, const u8 src, const bool is64, 497 const bool hi, const u8 op, struct jit_ctx *ctx){ 498 switch (BPF_OP(op)) { 499 /* dst = dst + src */ 500 case BPF_ADD: 501 emit_a32_add_r(dst, src, is64, hi, ctx); 502 break; 503 /* dst = dst - src */ 504 case BPF_SUB: 505 emit_a32_sub_r(dst, src, is64, hi, ctx); 506 break; 507 /* dst = dst | src */ 508 case BPF_OR: 509 emit(ARM_ORR_R(dst, dst, src), ctx); 510 break; 511 /* dst = dst & src */ 512 case BPF_AND: 513 emit(ARM_AND_R(dst, dst, src), ctx); 514 break; 515 /* dst = dst ^ src */ 516 case BPF_XOR: 517 emit(ARM_EOR_R(dst, dst, src), ctx); 518 break; 519 /* dst = dst * src */ 520 case BPF_MUL: 521 emit(ARM_MUL(dst, dst, src), ctx); 522 break; 523 /* dst = dst << src */ 524 case BPF_LSH: 525 emit(ARM_LSL_R(dst, dst, src), ctx); 526 break; 527 /* dst = dst >> src */ 528 case BPF_RSH: 529 emit(ARM_LSR_R(dst, dst, src), ctx); 530 break; 531 /* dst = dst >> src (signed)*/ 532 case BPF_ARSH: 533 emit(ARM_MOV_SR(dst, dst, SRTYPE_ASR, src), ctx); 534 break; 535 } 536 } 537 538 /* ALU operation (32 bit) 539 * dst = dst (op) src 540 */ 541 static inline void emit_a32_alu_r(const u8 dst, const u8 src, 542 bool dstk, bool sstk, 543 struct jit_ctx *ctx, const bool is64, 544 const bool hi, const u8 op) { 545 const u8 *tmp = bpf2a32[TMP_REG_1]; 546 u8 rn = sstk ? tmp[1] : src; 547 548 if (sstk) 549 emit(ARM_LDR_I(rn, ARM_SP, STACK_VAR(src)), ctx); 550 551 /* ALU operation */ 552 if (dstk) { 553 emit(ARM_LDR_I(tmp[0], ARM_SP, STACK_VAR(dst)), ctx); 554 emit_alu_r(tmp[0], rn, is64, hi, op, ctx); 555 emit(ARM_STR_I(tmp[0], ARM_SP, STACK_VAR(dst)), ctx); 556 } else { 557 emit_alu_r(dst, rn, is64, hi, op, ctx); 558 } 559 } 560 561 /* ALU operation (64 bit) */ 562 static inline void emit_a32_alu_r64(const bool is64, const u8 dst[], 563 const u8 src[], bool dstk, 564 bool sstk, struct jit_ctx *ctx, 565 const u8 op) { 566 emit_a32_alu_r(dst_lo, src_lo, dstk, sstk, ctx, is64, false, op); 567 if (is64) 568 emit_a32_alu_r(dst_hi, src_hi, dstk, sstk, ctx, is64, true, op); 569 else 570 emit_a32_mov_i(dst_hi, 0, dstk, ctx); 571 } 572 573 /* dst = imm (4 bytes)*/ 574 static inline void emit_a32_mov_r(const u8 dst, const u8 src, 575 bool dstk, bool sstk, 576 struct jit_ctx *ctx) { 577 const u8 *tmp = bpf2a32[TMP_REG_1]; 578 u8 rt = sstk ? tmp[0] : src; 579 580 if (sstk) 581 emit(ARM_LDR_I(tmp[0], ARM_SP, STACK_VAR(src)), ctx); 582 if (dstk) 583 emit(ARM_STR_I(rt, ARM_SP, STACK_VAR(dst)), ctx); 584 else 585 emit(ARM_MOV_R(dst, rt), ctx); 586 } 587 588 /* dst = src */ 589 static inline void emit_a32_mov_r64(const bool is64, const u8 dst[], 590 const u8 src[], bool dstk, 591 bool sstk, struct jit_ctx *ctx) { 592 emit_a32_mov_r(dst_lo, src_lo, dstk, sstk, ctx); 593 if (is64) { 594 /* complete 8 byte move */ 595 emit_a32_mov_r(dst_hi, src_hi, dstk, sstk, ctx); 596 } else { 597 /* Zero out high 4 bytes */ 598 emit_a32_mov_i(dst_hi, 0, dstk, ctx); 599 } 600 } 601 602 /* Shift operations */ 603 static inline void emit_a32_alu_i(const u8 dst, const u32 val, bool dstk, 604 struct jit_ctx *ctx, const u8 op) { 605 const u8 *tmp = bpf2a32[TMP_REG_1]; 606 u8 rd = dstk ? tmp[0] : dst; 607 608 if (dstk) 609 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst)), ctx); 610 611 /* Do shift operation */ 612 switch (op) { 613 case BPF_LSH: 614 emit(ARM_LSL_I(rd, rd, val), ctx); 615 break; 616 case BPF_RSH: 617 emit(ARM_LSR_I(rd, rd, val), ctx); 618 break; 619 case BPF_NEG: 620 emit(ARM_RSB_I(rd, rd, val), ctx); 621 break; 622 } 623 624 if (dstk) 625 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst)), ctx); 626 } 627 628 /* dst = ~dst (64 bit) */ 629 static inline void emit_a32_neg64(const u8 dst[], bool dstk, 630 struct jit_ctx *ctx){ 631 const u8 *tmp = bpf2a32[TMP_REG_1]; 632 u8 rd = dstk ? tmp[1] : dst[1]; 633 u8 rm = dstk ? tmp[0] : dst[0]; 634 635 /* Setup Operand */ 636 if (dstk) { 637 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 638 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx); 639 } 640 641 /* Do Negate Operation */ 642 emit(ARM_RSBS_I(rd, rd, 0), ctx); 643 emit(ARM_RSC_I(rm, rm, 0), ctx); 644 645 if (dstk) { 646 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 647 emit(ARM_STR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx); 648 } 649 } 650 651 /* dst = dst << src */ 652 static inline void emit_a32_lsh_r64(const u8 dst[], const u8 src[], bool dstk, 653 bool sstk, struct jit_ctx *ctx) { 654 const u8 *tmp = bpf2a32[TMP_REG_1]; 655 const u8 *tmp2 = bpf2a32[TMP_REG_2]; 656 657 /* Setup Operands */ 658 u8 rt = sstk ? tmp2[1] : src_lo; 659 u8 rd = dstk ? tmp[1] : dst_lo; 660 u8 rm = dstk ? tmp[0] : dst_hi; 661 662 if (sstk) 663 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(src_lo)), ctx); 664 if (dstk) { 665 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 666 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx); 667 } 668 669 /* Do LSH operation */ 670 emit(ARM_SUB_I(ARM_IP, rt, 32), ctx); 671 emit(ARM_RSB_I(tmp2[0], rt, 32), ctx); 672 emit(ARM_MOV_SR(ARM_LR, rm, SRTYPE_ASL, rt), ctx); 673 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rd, SRTYPE_ASL, ARM_IP), ctx); 674 emit(ARM_ORR_SR(ARM_IP, ARM_LR, rd, SRTYPE_LSR, tmp2[0]), ctx); 675 emit(ARM_MOV_SR(ARM_LR, rd, SRTYPE_ASL, rt), ctx); 676 677 if (dstk) { 678 emit(ARM_STR_I(ARM_LR, ARM_SP, STACK_VAR(dst_lo)), ctx); 679 emit(ARM_STR_I(ARM_IP, ARM_SP, STACK_VAR(dst_hi)), ctx); 680 } else { 681 emit(ARM_MOV_R(rd, ARM_LR), ctx); 682 emit(ARM_MOV_R(rm, ARM_IP), ctx); 683 } 684 } 685 686 /* dst = dst >> src (signed)*/ 687 static inline void emit_a32_arsh_r64(const u8 dst[], const u8 src[], bool dstk, 688 bool sstk, struct jit_ctx *ctx) { 689 const u8 *tmp = bpf2a32[TMP_REG_1]; 690 const u8 *tmp2 = bpf2a32[TMP_REG_2]; 691 /* Setup Operands */ 692 u8 rt = sstk ? tmp2[1] : src_lo; 693 u8 rd = dstk ? tmp[1] : dst_lo; 694 u8 rm = dstk ? tmp[0] : dst_hi; 695 696 if (sstk) 697 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(src_lo)), ctx); 698 if (dstk) { 699 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 700 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx); 701 } 702 703 /* Do the ARSH operation */ 704 emit(ARM_RSB_I(ARM_IP, rt, 32), ctx); 705 emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx); 706 emit(ARM_MOV_SR(ARM_LR, rd, SRTYPE_LSR, rt), ctx); 707 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rm, SRTYPE_ASL, ARM_IP), ctx); 708 _emit(ARM_COND_MI, ARM_B(0), ctx); 709 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rm, SRTYPE_ASR, tmp2[0]), ctx); 710 emit(ARM_MOV_SR(ARM_IP, rm, SRTYPE_ASR, rt), ctx); 711 if (dstk) { 712 emit(ARM_STR_I(ARM_LR, ARM_SP, STACK_VAR(dst_lo)), ctx); 713 emit(ARM_STR_I(ARM_IP, ARM_SP, STACK_VAR(dst_hi)), ctx); 714 } else { 715 emit(ARM_MOV_R(rd, ARM_LR), ctx); 716 emit(ARM_MOV_R(rm, ARM_IP), ctx); 717 } 718 } 719 720 /* dst = dst >> src */ 721 static inline void emit_a32_lsr_r64(const u8 dst[], const u8 src[], bool dstk, 722 bool sstk, struct jit_ctx *ctx) { 723 const u8 *tmp = bpf2a32[TMP_REG_1]; 724 const u8 *tmp2 = bpf2a32[TMP_REG_2]; 725 /* Setup Operands */ 726 u8 rt = sstk ? tmp2[1] : src_lo; 727 u8 rd = dstk ? tmp[1] : dst_lo; 728 u8 rm = dstk ? tmp[0] : dst_hi; 729 730 if (sstk) 731 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(src_lo)), ctx); 732 if (dstk) { 733 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 734 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx); 735 } 736 737 /* Do LSH operation */ 738 emit(ARM_RSB_I(ARM_IP, rt, 32), ctx); 739 emit(ARM_SUBS_I(tmp2[0], rt, 32), ctx); 740 emit(ARM_MOV_SR(ARM_LR, rd, SRTYPE_LSR, rt), ctx); 741 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rm, SRTYPE_ASL, ARM_IP), ctx); 742 emit(ARM_ORR_SR(ARM_LR, ARM_LR, rm, SRTYPE_LSR, tmp2[0]), ctx); 743 emit(ARM_MOV_SR(ARM_IP, rm, SRTYPE_LSR, rt), ctx); 744 if (dstk) { 745 emit(ARM_STR_I(ARM_LR, ARM_SP, STACK_VAR(dst_lo)), ctx); 746 emit(ARM_STR_I(ARM_IP, ARM_SP, STACK_VAR(dst_hi)), ctx); 747 } else { 748 emit(ARM_MOV_R(rd, ARM_LR), ctx); 749 emit(ARM_MOV_R(rm, ARM_IP), ctx); 750 } 751 } 752 753 /* dst = dst << val */ 754 static inline void emit_a32_lsh_i64(const u8 dst[], bool dstk, 755 const u32 val, struct jit_ctx *ctx){ 756 const u8 *tmp = bpf2a32[TMP_REG_1]; 757 const u8 *tmp2 = bpf2a32[TMP_REG_2]; 758 /* Setup operands */ 759 u8 rd = dstk ? tmp[1] : dst_lo; 760 u8 rm = dstk ? tmp[0] : dst_hi; 761 762 if (dstk) { 763 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 764 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx); 765 } 766 767 /* Do LSH operation */ 768 if (val < 32) { 769 emit(ARM_MOV_SI(tmp2[0], rm, SRTYPE_ASL, val), ctx); 770 emit(ARM_ORR_SI(rm, tmp2[0], rd, SRTYPE_LSR, 32 - val), ctx); 771 emit(ARM_MOV_SI(rd, rd, SRTYPE_ASL, val), ctx); 772 } else { 773 if (val == 32) 774 emit(ARM_MOV_R(rm, rd), ctx); 775 else 776 emit(ARM_MOV_SI(rm, rd, SRTYPE_ASL, val - 32), ctx); 777 emit(ARM_EOR_R(rd, rd, rd), ctx); 778 } 779 780 if (dstk) { 781 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 782 emit(ARM_STR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx); 783 } 784 } 785 786 /* dst = dst >> val */ 787 static inline void emit_a32_lsr_i64(const u8 dst[], bool dstk, 788 const u32 val, struct jit_ctx *ctx) { 789 const u8 *tmp = bpf2a32[TMP_REG_1]; 790 const u8 *tmp2 = bpf2a32[TMP_REG_2]; 791 /* Setup operands */ 792 u8 rd = dstk ? tmp[1] : dst_lo; 793 u8 rm = dstk ? tmp[0] : dst_hi; 794 795 if (dstk) { 796 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 797 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx); 798 } 799 800 /* Do LSR operation */ 801 if (val < 32) { 802 emit(ARM_MOV_SI(tmp2[1], rd, SRTYPE_LSR, val), ctx); 803 emit(ARM_ORR_SI(rd, tmp2[1], rm, SRTYPE_ASL, 32 - val), ctx); 804 emit(ARM_MOV_SI(rm, rm, SRTYPE_LSR, val), ctx); 805 } else if (val == 32) { 806 emit(ARM_MOV_R(rd, rm), ctx); 807 emit(ARM_MOV_I(rm, 0), ctx); 808 } else { 809 emit(ARM_MOV_SI(rd, rm, SRTYPE_LSR, val - 32), ctx); 810 emit(ARM_MOV_I(rm, 0), ctx); 811 } 812 813 if (dstk) { 814 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 815 emit(ARM_STR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx); 816 } 817 } 818 819 /* dst = dst >> val (signed) */ 820 static inline void emit_a32_arsh_i64(const u8 dst[], bool dstk, 821 const u32 val, struct jit_ctx *ctx){ 822 const u8 *tmp = bpf2a32[TMP_REG_1]; 823 const u8 *tmp2 = bpf2a32[TMP_REG_2]; 824 /* Setup operands */ 825 u8 rd = dstk ? tmp[1] : dst_lo; 826 u8 rm = dstk ? tmp[0] : dst_hi; 827 828 if (dstk) { 829 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 830 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx); 831 } 832 833 /* Do ARSH operation */ 834 if (val < 32) { 835 emit(ARM_MOV_SI(tmp2[1], rd, SRTYPE_LSR, val), ctx); 836 emit(ARM_ORR_SI(rd, tmp2[1], rm, SRTYPE_ASL, 32 - val), ctx); 837 emit(ARM_MOV_SI(rm, rm, SRTYPE_ASR, val), ctx); 838 } else if (val == 32) { 839 emit(ARM_MOV_R(rd, rm), ctx); 840 emit(ARM_MOV_SI(rm, rm, SRTYPE_ASR, 31), ctx); 841 } else { 842 emit(ARM_MOV_SI(rd, rm, SRTYPE_ASR, val - 32), ctx); 843 emit(ARM_MOV_SI(rm, rm, SRTYPE_ASR, 31), ctx); 844 } 845 846 if (dstk) { 847 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 848 emit(ARM_STR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx); 849 } 850 } 851 852 static inline void emit_a32_mul_r64(const u8 dst[], const u8 src[], bool dstk, 853 bool sstk, struct jit_ctx *ctx) { 854 const u8 *tmp = bpf2a32[TMP_REG_1]; 855 const u8 *tmp2 = bpf2a32[TMP_REG_2]; 856 /* Setup operands for multiplication */ 857 u8 rd = dstk ? tmp[1] : dst_lo; 858 u8 rm = dstk ? tmp[0] : dst_hi; 859 u8 rt = sstk ? tmp2[1] : src_lo; 860 u8 rn = sstk ? tmp2[0] : src_hi; 861 862 if (dstk) { 863 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 864 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx); 865 } 866 if (sstk) { 867 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(src_lo)), ctx); 868 emit(ARM_LDR_I(rn, ARM_SP, STACK_VAR(src_hi)), ctx); 869 } 870 871 /* Do Multiplication */ 872 emit(ARM_MUL(ARM_IP, rd, rn), ctx); 873 emit(ARM_MUL(ARM_LR, rm, rt), ctx); 874 emit(ARM_ADD_R(ARM_LR, ARM_IP, ARM_LR), ctx); 875 876 emit(ARM_UMULL(ARM_IP, rm, rd, rt), ctx); 877 emit(ARM_ADD_R(rm, ARM_LR, rm), ctx); 878 if (dstk) { 879 emit(ARM_STR_I(ARM_IP, ARM_SP, STACK_VAR(dst_lo)), ctx); 880 emit(ARM_STR_I(rm, ARM_SP, STACK_VAR(dst_hi)), ctx); 881 } else { 882 emit(ARM_MOV_R(rd, ARM_IP), ctx); 883 } 884 } 885 886 /* *(size *)(dst + off) = src */ 887 static inline void emit_str_r(const u8 dst, const u8 src, bool dstk, 888 const s32 off, struct jit_ctx *ctx, const u8 sz){ 889 const u8 *tmp = bpf2a32[TMP_REG_1]; 890 u8 rd = dstk ? tmp[1] : dst; 891 892 if (dstk) 893 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst)), ctx); 894 if (off) { 895 emit_a32_mov_i(tmp[0], off, false, ctx); 896 emit(ARM_ADD_R(tmp[0], rd, tmp[0]), ctx); 897 rd = tmp[0]; 898 } 899 switch (sz) { 900 case BPF_W: 901 /* Store a Word */ 902 emit(ARM_STR_I(src, rd, 0), ctx); 903 break; 904 case BPF_H: 905 /* Store a HalfWord */ 906 emit(ARM_STRH_I(src, rd, 0), ctx); 907 break; 908 case BPF_B: 909 /* Store a Byte */ 910 emit(ARM_STRB_I(src, rd, 0), ctx); 911 break; 912 } 913 } 914 915 /* dst = *(size*)(src + off) */ 916 static inline void emit_ldx_r(const u8 dst[], const u8 src, bool dstk, 917 s32 off, struct jit_ctx *ctx, const u8 sz){ 918 const u8 *tmp = bpf2a32[TMP_REG_1]; 919 const u8 *rd = dstk ? tmp : dst; 920 u8 rm = src; 921 s32 off_max; 922 923 if (sz == BPF_H) 924 off_max = 0xff; 925 else 926 off_max = 0xfff; 927 928 if (off < 0 || off > off_max) { 929 emit_a32_mov_i(tmp[0], off, false, ctx); 930 emit(ARM_ADD_R(tmp[0], tmp[0], src), ctx); 931 rm = tmp[0]; 932 off = 0; 933 } else if (rd[1] == rm) { 934 emit(ARM_MOV_R(tmp[0], rm), ctx); 935 rm = tmp[0]; 936 } 937 switch (sz) { 938 case BPF_B: 939 /* Load a Byte */ 940 emit(ARM_LDRB_I(rd[1], rm, off), ctx); 941 emit_a32_mov_i(dst[0], 0, dstk, ctx); 942 break; 943 case BPF_H: 944 /* Load a HalfWord */ 945 emit(ARM_LDRH_I(rd[1], rm, off), ctx); 946 emit_a32_mov_i(dst[0], 0, dstk, ctx); 947 break; 948 case BPF_W: 949 /* Load a Word */ 950 emit(ARM_LDR_I(rd[1], rm, off), ctx); 951 emit_a32_mov_i(dst[0], 0, dstk, ctx); 952 break; 953 case BPF_DW: 954 /* Load a Double Word */ 955 emit(ARM_LDR_I(rd[1], rm, off), ctx); 956 emit(ARM_LDR_I(rd[0], rm, off + 4), ctx); 957 break; 958 } 959 if (dstk) 960 emit(ARM_STR_I(rd[1], ARM_SP, STACK_VAR(dst[1])), ctx); 961 if (dstk && sz == BPF_DW) 962 emit(ARM_STR_I(rd[0], ARM_SP, STACK_VAR(dst[0])), ctx); 963 } 964 965 /* Arithmatic Operation */ 966 static inline void emit_ar_r(const u8 rd, const u8 rt, const u8 rm, 967 const u8 rn, struct jit_ctx *ctx, u8 op) { 968 switch (op) { 969 case BPF_JSET: 970 emit(ARM_AND_R(ARM_IP, rt, rn), ctx); 971 emit(ARM_AND_R(ARM_LR, rd, rm), ctx); 972 emit(ARM_ORRS_R(ARM_IP, ARM_LR, ARM_IP), ctx); 973 break; 974 case BPF_JEQ: 975 case BPF_JNE: 976 case BPF_JGT: 977 case BPF_JGE: 978 case BPF_JLE: 979 case BPF_JLT: 980 emit(ARM_CMP_R(rd, rm), ctx); 981 _emit(ARM_COND_EQ, ARM_CMP_R(rt, rn), ctx); 982 break; 983 case BPF_JSLE: 984 case BPF_JSGT: 985 emit(ARM_CMP_R(rn, rt), ctx); 986 emit(ARM_SBCS_R(ARM_IP, rm, rd), ctx); 987 break; 988 case BPF_JSLT: 989 case BPF_JSGE: 990 emit(ARM_CMP_R(rt, rn), ctx); 991 emit(ARM_SBCS_R(ARM_IP, rd, rm), ctx); 992 break; 993 } 994 } 995 996 static int out_offset = -1; /* initialized on the first pass of build_body() */ 997 static int emit_bpf_tail_call(struct jit_ctx *ctx) 998 { 999 1000 /* bpf_tail_call(void *prog_ctx, struct bpf_array *array, u64 index) */ 1001 const u8 *r2 = bpf2a32[BPF_REG_2]; 1002 const u8 *r3 = bpf2a32[BPF_REG_3]; 1003 const u8 *tmp = bpf2a32[TMP_REG_1]; 1004 const u8 *tmp2 = bpf2a32[TMP_REG_2]; 1005 const u8 *tcc = bpf2a32[TCALL_CNT]; 1006 const int idx0 = ctx->idx; 1007 #define cur_offset (ctx->idx - idx0) 1008 #define jmp_offset (out_offset - (cur_offset) - 2) 1009 u32 off, lo, hi; 1010 1011 /* if (index >= array->map.max_entries) 1012 * goto out; 1013 */ 1014 off = offsetof(struct bpf_array, map.max_entries); 1015 /* array->map.max_entries */ 1016 emit_a32_mov_i(tmp[1], off, false, ctx); 1017 emit(ARM_LDR_I(tmp2[1], ARM_SP, STACK_VAR(r2[1])), ctx); 1018 emit(ARM_LDR_R(tmp[1], tmp2[1], tmp[1]), ctx); 1019 /* index is 32-bit for arrays */ 1020 emit(ARM_LDR_I(tmp2[1], ARM_SP, STACK_VAR(r3[1])), ctx); 1021 /* index >= array->map.max_entries */ 1022 emit(ARM_CMP_R(tmp2[1], tmp[1]), ctx); 1023 _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx); 1024 1025 /* if (tail_call_cnt > MAX_TAIL_CALL_CNT) 1026 * goto out; 1027 * tail_call_cnt++; 1028 */ 1029 lo = (u32)MAX_TAIL_CALL_CNT; 1030 hi = (u32)((u64)MAX_TAIL_CALL_CNT >> 32); 1031 emit(ARM_LDR_I(tmp[1], ARM_SP, STACK_VAR(tcc[1])), ctx); 1032 emit(ARM_LDR_I(tmp[0], ARM_SP, STACK_VAR(tcc[0])), ctx); 1033 emit(ARM_CMP_I(tmp[0], hi), ctx); 1034 _emit(ARM_COND_EQ, ARM_CMP_I(tmp[1], lo), ctx); 1035 _emit(ARM_COND_HI, ARM_B(jmp_offset), ctx); 1036 emit(ARM_ADDS_I(tmp[1], tmp[1], 1), ctx); 1037 emit(ARM_ADC_I(tmp[0], tmp[0], 0), ctx); 1038 emit(ARM_STR_I(tmp[1], ARM_SP, STACK_VAR(tcc[1])), ctx); 1039 emit(ARM_STR_I(tmp[0], ARM_SP, STACK_VAR(tcc[0])), ctx); 1040 1041 /* prog = array->ptrs[index] 1042 * if (prog == NULL) 1043 * goto out; 1044 */ 1045 off = offsetof(struct bpf_array, ptrs); 1046 emit_a32_mov_i(tmp[1], off, false, ctx); 1047 emit(ARM_LDR_I(tmp2[1], ARM_SP, STACK_VAR(r2[1])), ctx); 1048 emit(ARM_ADD_R(tmp[1], tmp2[1], tmp[1]), ctx); 1049 emit(ARM_LDR_I(tmp2[1], ARM_SP, STACK_VAR(r3[1])), ctx); 1050 emit(ARM_MOV_SI(tmp[0], tmp2[1], SRTYPE_ASL, 2), ctx); 1051 emit(ARM_LDR_R(tmp[1], tmp[1], tmp[0]), ctx); 1052 emit(ARM_CMP_I(tmp[1], 0), ctx); 1053 _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx); 1054 1055 /* goto *(prog->bpf_func + prologue_size); */ 1056 off = offsetof(struct bpf_prog, bpf_func); 1057 emit_a32_mov_i(tmp2[1], off, false, ctx); 1058 emit(ARM_LDR_R(tmp[1], tmp[1], tmp2[1]), ctx); 1059 emit(ARM_ADD_I(tmp[1], tmp[1], ctx->prologue_bytes), ctx); 1060 emit_bx_r(tmp[1], ctx); 1061 1062 /* out: */ 1063 if (out_offset == -1) 1064 out_offset = cur_offset; 1065 if (cur_offset != out_offset) { 1066 pr_err_once("tail_call out_offset = %d, expected %d!\n", 1067 cur_offset, out_offset); 1068 return -1; 1069 } 1070 return 0; 1071 #undef cur_offset 1072 #undef jmp_offset 1073 } 1074 1075 /* 0xabcd => 0xcdab */ 1076 static inline void emit_rev16(const u8 rd, const u8 rn, struct jit_ctx *ctx) 1077 { 1078 #if __LINUX_ARM_ARCH__ < 6 1079 const u8 *tmp2 = bpf2a32[TMP_REG_2]; 1080 1081 emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx); 1082 emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 8), ctx); 1083 emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx); 1084 emit(ARM_ORR_SI(rd, tmp2[0], tmp2[1], SRTYPE_LSL, 8), ctx); 1085 #else /* ARMv6+ */ 1086 emit(ARM_REV16(rd, rn), ctx); 1087 #endif 1088 } 1089 1090 /* 0xabcdefgh => 0xghefcdab */ 1091 static inline void emit_rev32(const u8 rd, const u8 rn, struct jit_ctx *ctx) 1092 { 1093 #if __LINUX_ARM_ARCH__ < 6 1094 const u8 *tmp2 = bpf2a32[TMP_REG_2]; 1095 1096 emit(ARM_AND_I(tmp2[1], rn, 0xff), ctx); 1097 emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 24), ctx); 1098 emit(ARM_ORR_SI(ARM_IP, tmp2[0], tmp2[1], SRTYPE_LSL, 24), ctx); 1099 1100 emit(ARM_MOV_SI(tmp2[1], rn, SRTYPE_LSR, 8), ctx); 1101 emit(ARM_AND_I(tmp2[1], tmp2[1], 0xff), ctx); 1102 emit(ARM_MOV_SI(tmp2[0], rn, SRTYPE_LSR, 16), ctx); 1103 emit(ARM_AND_I(tmp2[0], tmp2[0], 0xff), ctx); 1104 emit(ARM_MOV_SI(tmp2[0], tmp2[0], SRTYPE_LSL, 8), ctx); 1105 emit(ARM_ORR_SI(tmp2[0], tmp2[0], tmp2[1], SRTYPE_LSL, 16), ctx); 1106 emit(ARM_ORR_R(rd, ARM_IP, tmp2[0]), ctx); 1107 1108 #else /* ARMv6+ */ 1109 emit(ARM_REV(rd, rn), ctx); 1110 #endif 1111 } 1112 1113 // push the scratch stack register on top of the stack 1114 static inline void emit_push_r64(const u8 src[], const u8 shift, 1115 struct jit_ctx *ctx) 1116 { 1117 const u8 *tmp2 = bpf2a32[TMP_REG_2]; 1118 u16 reg_set = 0; 1119 1120 emit(ARM_LDR_I(tmp2[1], ARM_SP, STACK_VAR(src[1]+shift)), ctx); 1121 emit(ARM_LDR_I(tmp2[0], ARM_SP, STACK_VAR(src[0]+shift)), ctx); 1122 1123 reg_set = (1 << tmp2[1]) | (1 << tmp2[0]); 1124 emit(ARM_PUSH(reg_set), ctx); 1125 } 1126 1127 static void build_prologue(struct jit_ctx *ctx) 1128 { 1129 const u8 r0 = bpf2a32[BPF_REG_0][1]; 1130 const u8 r2 = bpf2a32[BPF_REG_1][1]; 1131 const u8 r3 = bpf2a32[BPF_REG_1][0]; 1132 const u8 r4 = bpf2a32[BPF_REG_6][1]; 1133 const u8 fplo = bpf2a32[BPF_REG_FP][1]; 1134 const u8 fphi = bpf2a32[BPF_REG_FP][0]; 1135 const u8 *tcc = bpf2a32[TCALL_CNT]; 1136 1137 /* Save callee saved registers. */ 1138 #ifdef CONFIG_FRAME_POINTER 1139 u16 reg_set = CALLEE_PUSH_MASK | 1 << ARM_IP | 1 << ARM_PC; 1140 emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx); 1141 emit(ARM_PUSH(reg_set), ctx); 1142 emit(ARM_SUB_I(ARM_FP, ARM_IP, 4), ctx); 1143 #else 1144 emit(ARM_PUSH(CALLEE_PUSH_MASK), ctx); 1145 emit(ARM_MOV_R(ARM_FP, ARM_SP), ctx); 1146 #endif 1147 /* Save frame pointer for later */ 1148 emit(ARM_SUB_I(ARM_IP, ARM_SP, SCRATCH_SIZE), ctx); 1149 1150 ctx->stack_size = imm8m(STACK_SIZE); 1151 1152 /* Set up function call stack */ 1153 emit(ARM_SUB_I(ARM_SP, ARM_SP, ctx->stack_size), ctx); 1154 1155 /* Set up BPF prog stack base register */ 1156 emit_a32_mov_r(fplo, ARM_IP, true, false, ctx); 1157 emit_a32_mov_i(fphi, 0, true, ctx); 1158 1159 /* mov r4, 0 */ 1160 emit(ARM_MOV_I(r4, 0), ctx); 1161 1162 /* Move BPF_CTX to BPF_R1 */ 1163 emit(ARM_MOV_R(r3, r4), ctx); 1164 emit(ARM_MOV_R(r2, r0), ctx); 1165 /* Initialize Tail Count */ 1166 emit(ARM_STR_I(r4, ARM_SP, STACK_VAR(tcc[0])), ctx); 1167 emit(ARM_STR_I(r4, ARM_SP, STACK_VAR(tcc[1])), ctx); 1168 /* end of prologue */ 1169 } 1170 1171 /* restore callee saved registers. */ 1172 static void build_epilogue(struct jit_ctx *ctx) 1173 { 1174 #ifdef CONFIG_FRAME_POINTER 1175 /* When using frame pointers, some additional registers need to 1176 * be loaded. */ 1177 u16 reg_set = CALLEE_POP_MASK | 1 << ARM_SP; 1178 emit(ARM_SUB_I(ARM_SP, ARM_FP, hweight16(reg_set) * 4), ctx); 1179 emit(ARM_LDM(ARM_SP, reg_set), ctx); 1180 #else 1181 /* Restore callee saved registers. */ 1182 emit(ARM_MOV_R(ARM_SP, ARM_FP), ctx); 1183 emit(ARM_POP(CALLEE_POP_MASK), ctx); 1184 #endif 1185 } 1186 1187 /* 1188 * Convert an eBPF instruction to native instruction, i.e 1189 * JITs an eBPF instruction. 1190 * Returns : 1191 * 0 - Successfully JITed an 8-byte eBPF instruction 1192 * >0 - Successfully JITed a 16-byte eBPF instruction 1193 * <0 - Failed to JIT. 1194 */ 1195 static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx) 1196 { 1197 const u8 code = insn->code; 1198 const u8 *dst = bpf2a32[insn->dst_reg]; 1199 const u8 *src = bpf2a32[insn->src_reg]; 1200 const u8 *tmp = bpf2a32[TMP_REG_1]; 1201 const u8 *tmp2 = bpf2a32[TMP_REG_2]; 1202 const s16 off = insn->off; 1203 const s32 imm = insn->imm; 1204 const int i = insn - ctx->prog->insnsi; 1205 const bool is64 = BPF_CLASS(code) == BPF_ALU64; 1206 const bool dstk = is_on_stack(insn->dst_reg); 1207 const bool sstk = is_on_stack(insn->src_reg); 1208 u8 rd, rt, rm, rn; 1209 s32 jmp_offset; 1210 1211 #define check_imm(bits, imm) do { \ 1212 if ((((imm) > 0) && ((imm) >> (bits))) || \ 1213 (((imm) < 0) && (~(imm) >> (bits)))) { \ 1214 pr_info("[%2d] imm=%d(0x%x) out of range\n", \ 1215 i, imm, imm); \ 1216 return -EINVAL; \ 1217 } \ 1218 } while (0) 1219 #define check_imm24(imm) check_imm(24, imm) 1220 1221 switch (code) { 1222 /* ALU operations */ 1223 1224 /* dst = src */ 1225 case BPF_ALU | BPF_MOV | BPF_K: 1226 case BPF_ALU | BPF_MOV | BPF_X: 1227 case BPF_ALU64 | BPF_MOV | BPF_K: 1228 case BPF_ALU64 | BPF_MOV | BPF_X: 1229 switch (BPF_SRC(code)) { 1230 case BPF_X: 1231 emit_a32_mov_r64(is64, dst, src, dstk, sstk, ctx); 1232 break; 1233 case BPF_K: 1234 /* Sign-extend immediate value to destination reg */ 1235 emit_a32_mov_i64(is64, dst, imm, dstk, ctx); 1236 break; 1237 } 1238 break; 1239 /* dst = dst + src/imm */ 1240 /* dst = dst - src/imm */ 1241 /* dst = dst | src/imm */ 1242 /* dst = dst & src/imm */ 1243 /* dst = dst ^ src/imm */ 1244 /* dst = dst * src/imm */ 1245 /* dst = dst << src */ 1246 /* dst = dst >> src */ 1247 case BPF_ALU | BPF_ADD | BPF_K: 1248 case BPF_ALU | BPF_ADD | BPF_X: 1249 case BPF_ALU | BPF_SUB | BPF_K: 1250 case BPF_ALU | BPF_SUB | BPF_X: 1251 case BPF_ALU | BPF_OR | BPF_K: 1252 case BPF_ALU | BPF_OR | BPF_X: 1253 case BPF_ALU | BPF_AND | BPF_K: 1254 case BPF_ALU | BPF_AND | BPF_X: 1255 case BPF_ALU | BPF_XOR | BPF_K: 1256 case BPF_ALU | BPF_XOR | BPF_X: 1257 case BPF_ALU | BPF_MUL | BPF_K: 1258 case BPF_ALU | BPF_MUL | BPF_X: 1259 case BPF_ALU | BPF_LSH | BPF_X: 1260 case BPF_ALU | BPF_RSH | BPF_X: 1261 case BPF_ALU | BPF_ARSH | BPF_K: 1262 case BPF_ALU | BPF_ARSH | BPF_X: 1263 case BPF_ALU64 | BPF_ADD | BPF_K: 1264 case BPF_ALU64 | BPF_ADD | BPF_X: 1265 case BPF_ALU64 | BPF_SUB | BPF_K: 1266 case BPF_ALU64 | BPF_SUB | BPF_X: 1267 case BPF_ALU64 | BPF_OR | BPF_K: 1268 case BPF_ALU64 | BPF_OR | BPF_X: 1269 case BPF_ALU64 | BPF_AND | BPF_K: 1270 case BPF_ALU64 | BPF_AND | BPF_X: 1271 case BPF_ALU64 | BPF_XOR | BPF_K: 1272 case BPF_ALU64 | BPF_XOR | BPF_X: 1273 switch (BPF_SRC(code)) { 1274 case BPF_X: 1275 emit_a32_alu_r64(is64, dst, src, dstk, sstk, 1276 ctx, BPF_OP(code)); 1277 break; 1278 case BPF_K: 1279 /* Move immediate value to the temporary register 1280 * and then do the ALU operation on the temporary 1281 * register as this will sign-extend the immediate 1282 * value into temporary reg and then it would be 1283 * safe to do the operation on it. 1284 */ 1285 emit_a32_mov_i64(is64, tmp2, imm, false, ctx); 1286 emit_a32_alu_r64(is64, dst, tmp2, dstk, false, 1287 ctx, BPF_OP(code)); 1288 break; 1289 } 1290 break; 1291 /* dst = dst / src(imm) */ 1292 /* dst = dst % src(imm) */ 1293 case BPF_ALU | BPF_DIV | BPF_K: 1294 case BPF_ALU | BPF_DIV | BPF_X: 1295 case BPF_ALU | BPF_MOD | BPF_K: 1296 case BPF_ALU | BPF_MOD | BPF_X: 1297 rt = src_lo; 1298 rd = dstk ? tmp2[1] : dst_lo; 1299 if (dstk) 1300 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 1301 switch (BPF_SRC(code)) { 1302 case BPF_X: 1303 rt = sstk ? tmp2[0] : rt; 1304 if (sstk) 1305 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(src_lo)), 1306 ctx); 1307 break; 1308 case BPF_K: 1309 rt = tmp2[0]; 1310 emit_a32_mov_i(rt, imm, false, ctx); 1311 break; 1312 } 1313 emit_udivmod(rd, rd, rt, ctx, BPF_OP(code)); 1314 if (dstk) 1315 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst_lo)), ctx); 1316 emit_a32_mov_i(dst_hi, 0, dstk, ctx); 1317 break; 1318 case BPF_ALU64 | BPF_DIV | BPF_K: 1319 case BPF_ALU64 | BPF_DIV | BPF_X: 1320 case BPF_ALU64 | BPF_MOD | BPF_K: 1321 case BPF_ALU64 | BPF_MOD | BPF_X: 1322 goto notyet; 1323 /* dst = dst >> imm */ 1324 /* dst = dst << imm */ 1325 case BPF_ALU | BPF_RSH | BPF_K: 1326 case BPF_ALU | BPF_LSH | BPF_K: 1327 if (unlikely(imm > 31)) 1328 return -EINVAL; 1329 if (imm) 1330 emit_a32_alu_i(dst_lo, imm, dstk, ctx, BPF_OP(code)); 1331 emit_a32_mov_i(dst_hi, 0, dstk, ctx); 1332 break; 1333 /* dst = dst << imm */ 1334 case BPF_ALU64 | BPF_LSH | BPF_K: 1335 if (unlikely(imm > 63)) 1336 return -EINVAL; 1337 emit_a32_lsh_i64(dst, dstk, imm, ctx); 1338 break; 1339 /* dst = dst >> imm */ 1340 case BPF_ALU64 | BPF_RSH | BPF_K: 1341 if (unlikely(imm > 63)) 1342 return -EINVAL; 1343 emit_a32_lsr_i64(dst, dstk, imm, ctx); 1344 break; 1345 /* dst = dst << src */ 1346 case BPF_ALU64 | BPF_LSH | BPF_X: 1347 emit_a32_lsh_r64(dst, src, dstk, sstk, ctx); 1348 break; 1349 /* dst = dst >> src */ 1350 case BPF_ALU64 | BPF_RSH | BPF_X: 1351 emit_a32_lsr_r64(dst, src, dstk, sstk, ctx); 1352 break; 1353 /* dst = dst >> src (signed) */ 1354 case BPF_ALU64 | BPF_ARSH | BPF_X: 1355 emit_a32_arsh_r64(dst, src, dstk, sstk, ctx); 1356 break; 1357 /* dst = dst >> imm (signed) */ 1358 case BPF_ALU64 | BPF_ARSH | BPF_K: 1359 if (unlikely(imm > 63)) 1360 return -EINVAL; 1361 emit_a32_arsh_i64(dst, dstk, imm, ctx); 1362 break; 1363 /* dst = ~dst */ 1364 case BPF_ALU | BPF_NEG: 1365 emit_a32_alu_i(dst_lo, 0, dstk, ctx, BPF_OP(code)); 1366 emit_a32_mov_i(dst_hi, 0, dstk, ctx); 1367 break; 1368 /* dst = ~dst (64 bit) */ 1369 case BPF_ALU64 | BPF_NEG: 1370 emit_a32_neg64(dst, dstk, ctx); 1371 break; 1372 /* dst = dst * src/imm */ 1373 case BPF_ALU64 | BPF_MUL | BPF_X: 1374 case BPF_ALU64 | BPF_MUL | BPF_K: 1375 switch (BPF_SRC(code)) { 1376 case BPF_X: 1377 emit_a32_mul_r64(dst, src, dstk, sstk, ctx); 1378 break; 1379 case BPF_K: 1380 /* Move immediate value to the temporary register 1381 * and then do the multiplication on it as this 1382 * will sign-extend the immediate value into temp 1383 * reg then it would be safe to do the operation 1384 * on it. 1385 */ 1386 emit_a32_mov_i64(is64, tmp2, imm, false, ctx); 1387 emit_a32_mul_r64(dst, tmp2, dstk, false, ctx); 1388 break; 1389 } 1390 break; 1391 /* dst = htole(dst) */ 1392 /* dst = htobe(dst) */ 1393 case BPF_ALU | BPF_END | BPF_FROM_LE: 1394 case BPF_ALU | BPF_END | BPF_FROM_BE: 1395 rd = dstk ? tmp[0] : dst_hi; 1396 rt = dstk ? tmp[1] : dst_lo; 1397 if (dstk) { 1398 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(dst_lo)), ctx); 1399 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_hi)), ctx); 1400 } 1401 if (BPF_SRC(code) == BPF_FROM_LE) 1402 goto emit_bswap_uxt; 1403 switch (imm) { 1404 case 16: 1405 emit_rev16(rt, rt, ctx); 1406 goto emit_bswap_uxt; 1407 case 32: 1408 emit_rev32(rt, rt, ctx); 1409 goto emit_bswap_uxt; 1410 case 64: 1411 emit_rev32(ARM_LR, rt, ctx); 1412 emit_rev32(rt, rd, ctx); 1413 emit(ARM_MOV_R(rd, ARM_LR), ctx); 1414 break; 1415 } 1416 goto exit; 1417 emit_bswap_uxt: 1418 switch (imm) { 1419 case 16: 1420 /* zero-extend 16 bits into 64 bits */ 1421 #if __LINUX_ARM_ARCH__ < 6 1422 emit_a32_mov_i(tmp2[1], 0xffff, false, ctx); 1423 emit(ARM_AND_R(rt, rt, tmp2[1]), ctx); 1424 #else /* ARMv6+ */ 1425 emit(ARM_UXTH(rt, rt), ctx); 1426 #endif 1427 emit(ARM_EOR_R(rd, rd, rd), ctx); 1428 break; 1429 case 32: 1430 /* zero-extend 32 bits into 64 bits */ 1431 emit(ARM_EOR_R(rd, rd, rd), ctx); 1432 break; 1433 case 64: 1434 /* nop */ 1435 break; 1436 } 1437 exit: 1438 if (dstk) { 1439 emit(ARM_STR_I(rt, ARM_SP, STACK_VAR(dst_lo)), ctx); 1440 emit(ARM_STR_I(rd, ARM_SP, STACK_VAR(dst_hi)), ctx); 1441 } 1442 break; 1443 /* dst = imm64 */ 1444 case BPF_LD | BPF_IMM | BPF_DW: 1445 { 1446 const struct bpf_insn insn1 = insn[1]; 1447 u32 hi, lo = imm; 1448 1449 hi = insn1.imm; 1450 emit_a32_mov_i(dst_lo, lo, dstk, ctx); 1451 emit_a32_mov_i(dst_hi, hi, dstk, ctx); 1452 1453 return 1; 1454 } 1455 /* LDX: dst = *(size *)(src + off) */ 1456 case BPF_LDX | BPF_MEM | BPF_W: 1457 case BPF_LDX | BPF_MEM | BPF_H: 1458 case BPF_LDX | BPF_MEM | BPF_B: 1459 case BPF_LDX | BPF_MEM | BPF_DW: 1460 rn = sstk ? tmp2[1] : src_lo; 1461 if (sstk) 1462 emit(ARM_LDR_I(rn, ARM_SP, STACK_VAR(src_lo)), ctx); 1463 emit_ldx_r(dst, rn, dstk, off, ctx, BPF_SIZE(code)); 1464 break; 1465 /* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + imm)) */ 1466 case BPF_LD | BPF_ABS | BPF_W: 1467 case BPF_LD | BPF_ABS | BPF_H: 1468 case BPF_LD | BPF_ABS | BPF_B: 1469 /* R0 = ntohx(*(size *)(((struct sk_buff *)R6)->data + src + imm)) */ 1470 case BPF_LD | BPF_IND | BPF_W: 1471 case BPF_LD | BPF_IND | BPF_H: 1472 case BPF_LD | BPF_IND | BPF_B: 1473 { 1474 const u8 r4 = bpf2a32[BPF_REG_6][1]; /* r4 = ptr to sk_buff */ 1475 const u8 r0 = bpf2a32[BPF_REG_0][1]; /*r0: struct sk_buff *skb*/ 1476 /* rtn value */ 1477 const u8 r1 = bpf2a32[BPF_REG_0][0]; /* r1: int k */ 1478 const u8 r2 = bpf2a32[BPF_REG_1][1]; /* r2: unsigned int size */ 1479 const u8 r3 = bpf2a32[BPF_REG_1][0]; /* r3: void *buffer */ 1480 const u8 r6 = bpf2a32[TMP_REG_1][1]; /* r6: void *(*func)(..) */ 1481 int size; 1482 1483 /* Setting up first argument */ 1484 emit(ARM_MOV_R(r0, r4), ctx); 1485 1486 /* Setting up second argument */ 1487 emit_a32_mov_i(r1, imm, false, ctx); 1488 if (BPF_MODE(code) == BPF_IND) 1489 emit_a32_alu_r(r1, src_lo, false, sstk, ctx, 1490 false, false, BPF_ADD); 1491 1492 /* Setting up third argument */ 1493 switch (BPF_SIZE(code)) { 1494 case BPF_W: 1495 size = 4; 1496 break; 1497 case BPF_H: 1498 size = 2; 1499 break; 1500 case BPF_B: 1501 size = 1; 1502 break; 1503 default: 1504 return -EINVAL; 1505 } 1506 emit_a32_mov_i(r2, size, false, ctx); 1507 1508 /* Setting up fourth argument */ 1509 emit(ARM_ADD_I(r3, ARM_SP, imm8m(SKB_BUFFER)), ctx); 1510 1511 /* Setting up function pointer to call */ 1512 emit_a32_mov_i(r6, (unsigned int)bpf_load_pointer, false, ctx); 1513 emit_blx_r(r6, ctx); 1514 1515 emit(ARM_EOR_R(r1, r1, r1), ctx); 1516 /* Check if return address is NULL or not. 1517 * if NULL then jump to epilogue 1518 * else continue to load the value from retn address 1519 */ 1520 emit(ARM_CMP_I(r0, 0), ctx); 1521 jmp_offset = epilogue_offset(ctx); 1522 check_imm24(jmp_offset); 1523 _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx); 1524 1525 /* Load value from the address */ 1526 switch (BPF_SIZE(code)) { 1527 case BPF_W: 1528 emit(ARM_LDR_I(r0, r0, 0), ctx); 1529 emit_rev32(r0, r0, ctx); 1530 break; 1531 case BPF_H: 1532 emit(ARM_LDRH_I(r0, r0, 0), ctx); 1533 emit_rev16(r0, r0, ctx); 1534 break; 1535 case BPF_B: 1536 emit(ARM_LDRB_I(r0, r0, 0), ctx); 1537 /* No need to reverse */ 1538 break; 1539 } 1540 break; 1541 } 1542 /* ST: *(size *)(dst + off) = imm */ 1543 case BPF_ST | BPF_MEM | BPF_W: 1544 case BPF_ST | BPF_MEM | BPF_H: 1545 case BPF_ST | BPF_MEM | BPF_B: 1546 case BPF_ST | BPF_MEM | BPF_DW: 1547 switch (BPF_SIZE(code)) { 1548 case BPF_DW: 1549 /* Sign-extend immediate value into temp reg */ 1550 emit_a32_mov_i64(true, tmp2, imm, false, ctx); 1551 emit_str_r(dst_lo, tmp2[1], dstk, off, ctx, BPF_W); 1552 emit_str_r(dst_lo, tmp2[0], dstk, off+4, ctx, BPF_W); 1553 break; 1554 case BPF_W: 1555 case BPF_H: 1556 case BPF_B: 1557 emit_a32_mov_i(tmp2[1], imm, false, ctx); 1558 emit_str_r(dst_lo, tmp2[1], dstk, off, ctx, 1559 BPF_SIZE(code)); 1560 break; 1561 } 1562 break; 1563 /* STX XADD: lock *(u32 *)(dst + off) += src */ 1564 case BPF_STX | BPF_XADD | BPF_W: 1565 /* STX XADD: lock *(u64 *)(dst + off) += src */ 1566 case BPF_STX | BPF_XADD | BPF_DW: 1567 goto notyet; 1568 /* STX: *(size *)(dst + off) = src */ 1569 case BPF_STX | BPF_MEM | BPF_W: 1570 case BPF_STX | BPF_MEM | BPF_H: 1571 case BPF_STX | BPF_MEM | BPF_B: 1572 case BPF_STX | BPF_MEM | BPF_DW: 1573 { 1574 u8 sz = BPF_SIZE(code); 1575 1576 rn = sstk ? tmp2[1] : src_lo; 1577 rm = sstk ? tmp2[0] : src_hi; 1578 if (sstk) { 1579 emit(ARM_LDR_I(rn, ARM_SP, STACK_VAR(src_lo)), ctx); 1580 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(src_hi)), ctx); 1581 } 1582 1583 /* Store the value */ 1584 if (BPF_SIZE(code) == BPF_DW) { 1585 emit_str_r(dst_lo, rn, dstk, off, ctx, BPF_W); 1586 emit_str_r(dst_lo, rm, dstk, off+4, ctx, BPF_W); 1587 } else { 1588 emit_str_r(dst_lo, rn, dstk, off, ctx, sz); 1589 } 1590 break; 1591 } 1592 /* PC += off if dst == src */ 1593 /* PC += off if dst > src */ 1594 /* PC += off if dst >= src */ 1595 /* PC += off if dst < src */ 1596 /* PC += off if dst <= src */ 1597 /* PC += off if dst != src */ 1598 /* PC += off if dst > src (signed) */ 1599 /* PC += off if dst >= src (signed) */ 1600 /* PC += off if dst < src (signed) */ 1601 /* PC += off if dst <= src (signed) */ 1602 /* PC += off if dst & src */ 1603 case BPF_JMP | BPF_JEQ | BPF_X: 1604 case BPF_JMP | BPF_JGT | BPF_X: 1605 case BPF_JMP | BPF_JGE | BPF_X: 1606 case BPF_JMP | BPF_JNE | BPF_X: 1607 case BPF_JMP | BPF_JSGT | BPF_X: 1608 case BPF_JMP | BPF_JSGE | BPF_X: 1609 case BPF_JMP | BPF_JSET | BPF_X: 1610 case BPF_JMP | BPF_JLE | BPF_X: 1611 case BPF_JMP | BPF_JLT | BPF_X: 1612 case BPF_JMP | BPF_JSLT | BPF_X: 1613 case BPF_JMP | BPF_JSLE | BPF_X: 1614 /* Setup source registers */ 1615 rm = sstk ? tmp2[0] : src_hi; 1616 rn = sstk ? tmp2[1] : src_lo; 1617 if (sstk) { 1618 emit(ARM_LDR_I(rn, ARM_SP, STACK_VAR(src_lo)), ctx); 1619 emit(ARM_LDR_I(rm, ARM_SP, STACK_VAR(src_hi)), ctx); 1620 } 1621 goto go_jmp; 1622 /* PC += off if dst == imm */ 1623 /* PC += off if dst > imm */ 1624 /* PC += off if dst >= imm */ 1625 /* PC += off if dst < imm */ 1626 /* PC += off if dst <= imm */ 1627 /* PC += off if dst != imm */ 1628 /* PC += off if dst > imm (signed) */ 1629 /* PC += off if dst >= imm (signed) */ 1630 /* PC += off if dst < imm (signed) */ 1631 /* PC += off if dst <= imm (signed) */ 1632 /* PC += off if dst & imm */ 1633 case BPF_JMP | BPF_JEQ | BPF_K: 1634 case BPF_JMP | BPF_JGT | BPF_K: 1635 case BPF_JMP | BPF_JGE | BPF_K: 1636 case BPF_JMP | BPF_JNE | BPF_K: 1637 case BPF_JMP | BPF_JSGT | BPF_K: 1638 case BPF_JMP | BPF_JSGE | BPF_K: 1639 case BPF_JMP | BPF_JSET | BPF_K: 1640 case BPF_JMP | BPF_JLT | BPF_K: 1641 case BPF_JMP | BPF_JLE | BPF_K: 1642 case BPF_JMP | BPF_JSLT | BPF_K: 1643 case BPF_JMP | BPF_JSLE | BPF_K: 1644 if (off == 0) 1645 break; 1646 rm = tmp2[0]; 1647 rn = tmp2[1]; 1648 /* Sign-extend immediate value */ 1649 emit_a32_mov_i64(true, tmp2, imm, false, ctx); 1650 go_jmp: 1651 /* Setup destination register */ 1652 rd = dstk ? tmp[0] : dst_hi; 1653 rt = dstk ? tmp[1] : dst_lo; 1654 if (dstk) { 1655 emit(ARM_LDR_I(rt, ARM_SP, STACK_VAR(dst_lo)), ctx); 1656 emit(ARM_LDR_I(rd, ARM_SP, STACK_VAR(dst_hi)), ctx); 1657 } 1658 1659 /* Check for the condition */ 1660 emit_ar_r(rd, rt, rm, rn, ctx, BPF_OP(code)); 1661 1662 /* Setup JUMP instruction */ 1663 jmp_offset = bpf2a32_offset(i+off, i, ctx); 1664 switch (BPF_OP(code)) { 1665 case BPF_JNE: 1666 case BPF_JSET: 1667 _emit(ARM_COND_NE, ARM_B(jmp_offset), ctx); 1668 break; 1669 case BPF_JEQ: 1670 _emit(ARM_COND_EQ, ARM_B(jmp_offset), ctx); 1671 break; 1672 case BPF_JGT: 1673 _emit(ARM_COND_HI, ARM_B(jmp_offset), ctx); 1674 break; 1675 case BPF_JGE: 1676 _emit(ARM_COND_CS, ARM_B(jmp_offset), ctx); 1677 break; 1678 case BPF_JSGT: 1679 _emit(ARM_COND_LT, ARM_B(jmp_offset), ctx); 1680 break; 1681 case BPF_JSGE: 1682 _emit(ARM_COND_GE, ARM_B(jmp_offset), ctx); 1683 break; 1684 case BPF_JLE: 1685 _emit(ARM_COND_LS, ARM_B(jmp_offset), ctx); 1686 break; 1687 case BPF_JLT: 1688 _emit(ARM_COND_CC, ARM_B(jmp_offset), ctx); 1689 break; 1690 case BPF_JSLT: 1691 _emit(ARM_COND_LT, ARM_B(jmp_offset), ctx); 1692 break; 1693 case BPF_JSLE: 1694 _emit(ARM_COND_GE, ARM_B(jmp_offset), ctx); 1695 break; 1696 } 1697 break; 1698 /* JMP OFF */ 1699 case BPF_JMP | BPF_JA: 1700 { 1701 if (off == 0) 1702 break; 1703 jmp_offset = bpf2a32_offset(i+off, i, ctx); 1704 check_imm24(jmp_offset); 1705 emit(ARM_B(jmp_offset), ctx); 1706 break; 1707 } 1708 /* tail call */ 1709 case BPF_JMP | BPF_TAIL_CALL: 1710 if (emit_bpf_tail_call(ctx)) 1711 return -EFAULT; 1712 break; 1713 /* function call */ 1714 case BPF_JMP | BPF_CALL: 1715 { 1716 const u8 *r0 = bpf2a32[BPF_REG_0]; 1717 const u8 *r1 = bpf2a32[BPF_REG_1]; 1718 const u8 *r2 = bpf2a32[BPF_REG_2]; 1719 const u8 *r3 = bpf2a32[BPF_REG_3]; 1720 const u8 *r4 = bpf2a32[BPF_REG_4]; 1721 const u8 *r5 = bpf2a32[BPF_REG_5]; 1722 const u32 func = (u32)__bpf_call_base + (u32)imm; 1723 1724 emit_a32_mov_r64(true, r0, r1, false, false, ctx); 1725 emit_a32_mov_r64(true, r1, r2, false, true, ctx); 1726 emit_push_r64(r5, 0, ctx); 1727 emit_push_r64(r4, 8, ctx); 1728 emit_push_r64(r3, 16, ctx); 1729 1730 emit_a32_mov_i(tmp[1], func, false, ctx); 1731 emit_blx_r(tmp[1], ctx); 1732 1733 emit(ARM_ADD_I(ARM_SP, ARM_SP, imm8m(24)), ctx); // callee clean 1734 break; 1735 } 1736 /* function return */ 1737 case BPF_JMP | BPF_EXIT: 1738 /* Optimization: when last instruction is EXIT 1739 * simply fallthrough to epilogue. 1740 */ 1741 if (i == ctx->prog->len - 1) 1742 break; 1743 jmp_offset = epilogue_offset(ctx); 1744 check_imm24(jmp_offset); 1745 emit(ARM_B(jmp_offset), ctx); 1746 break; 1747 notyet: 1748 pr_info_once("*** NOT YET: opcode %02x ***\n", code); 1749 return -EFAULT; 1750 default: 1751 pr_err_once("unknown opcode %02x\n", code); 1752 return -EINVAL; 1753 } 1754 1755 if (ctx->flags & FLAG_IMM_OVERFLOW) 1756 /* 1757 * this instruction generated an overflow when 1758 * trying to access the literal pool, so 1759 * delegate this filter to the kernel interpreter. 1760 */ 1761 return -1; 1762 return 0; 1763 } 1764 1765 static int build_body(struct jit_ctx *ctx) 1766 { 1767 const struct bpf_prog *prog = ctx->prog; 1768 unsigned int i; 1769 1770 for (i = 0; i < prog->len; i++) { 1771 const struct bpf_insn *insn = &(prog->insnsi[i]); 1772 int ret; 1773 1774 ret = build_insn(insn, ctx); 1775 1776 /* It's used with loading the 64 bit immediate value. */ 1777 if (ret > 0) { 1778 i++; 1779 if (ctx->target == NULL) 1780 ctx->offsets[i] = ctx->idx; 1781 continue; 1782 } 1783 1784 if (ctx->target == NULL) 1785 ctx->offsets[i] = ctx->idx; 1786 1787 /* If unsuccesfull, return with error code */ 1788 if (ret) 1789 return ret; 1790 } 1791 return 0; 1792 } 1793 1794 static int validate_code(struct jit_ctx *ctx) 1795 { 1796 int i; 1797 1798 for (i = 0; i < ctx->idx; i++) { 1799 if (ctx->target[i] == __opcode_to_mem_arm(ARM_INST_UDF)) 1800 return -1; 1801 } 1802 1803 return 0; 1804 } 1805 1806 void bpf_jit_compile(struct bpf_prog *prog) 1807 { 1808 /* Nothing to do here. We support Internal BPF. */ 1809 } 1810 1811 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) 1812 { 1813 struct bpf_prog *tmp, *orig_prog = prog; 1814 struct bpf_binary_header *header; 1815 bool tmp_blinded = false; 1816 struct jit_ctx ctx; 1817 unsigned int tmp_idx; 1818 unsigned int image_size; 1819 u8 *image_ptr; 1820 1821 /* If BPF JIT was not enabled then we must fall back to 1822 * the interpreter. 1823 */ 1824 if (!bpf_jit_enable) 1825 return orig_prog; 1826 1827 /* If constant blinding was enabled and we failed during blinding 1828 * then we must fall back to the interpreter. Otherwise, we save 1829 * the new JITed code. 1830 */ 1831 tmp = bpf_jit_blind_constants(prog); 1832 1833 if (IS_ERR(tmp)) 1834 return orig_prog; 1835 if (tmp != prog) { 1836 tmp_blinded = true; 1837 prog = tmp; 1838 } 1839 1840 memset(&ctx, 0, sizeof(ctx)); 1841 ctx.prog = prog; 1842 1843 /* Not able to allocate memory for offsets[] , then 1844 * we must fall back to the interpreter 1845 */ 1846 ctx.offsets = kcalloc(prog->len, sizeof(int), GFP_KERNEL); 1847 if (ctx.offsets == NULL) { 1848 prog = orig_prog; 1849 goto out; 1850 } 1851 1852 /* 1) fake pass to find in the length of the JITed code, 1853 * to compute ctx->offsets and other context variables 1854 * needed to compute final JITed code. 1855 * Also, calculate random starting pointer/start of JITed code 1856 * which is prefixed by random number of fault instructions. 1857 * 1858 * If the first pass fails then there is no chance of it 1859 * being successful in the second pass, so just fall back 1860 * to the interpreter. 1861 */ 1862 if (build_body(&ctx)) { 1863 prog = orig_prog; 1864 goto out_off; 1865 } 1866 1867 tmp_idx = ctx.idx; 1868 build_prologue(&ctx); 1869 ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4; 1870 1871 ctx.epilogue_offset = ctx.idx; 1872 1873 #if __LINUX_ARM_ARCH__ < 7 1874 tmp_idx = ctx.idx; 1875 build_epilogue(&ctx); 1876 ctx.epilogue_bytes = (ctx.idx - tmp_idx) * 4; 1877 1878 ctx.idx += ctx.imm_count; 1879 if (ctx.imm_count) { 1880 ctx.imms = kcalloc(ctx.imm_count, sizeof(u32), GFP_KERNEL); 1881 if (ctx.imms == NULL) { 1882 prog = orig_prog; 1883 goto out_off; 1884 } 1885 } 1886 #else 1887 /* there's nothing about the epilogue on ARMv7 */ 1888 build_epilogue(&ctx); 1889 #endif 1890 /* Now we can get the actual image size of the JITed arm code. 1891 * Currently, we are not considering the THUMB-2 instructions 1892 * for jit, although it can decrease the size of the image. 1893 * 1894 * As each arm instruction is of length 32bit, we are translating 1895 * number of JITed intructions into the size required to store these 1896 * JITed code. 1897 */ 1898 image_size = sizeof(u32) * ctx.idx; 1899 1900 /* Now we know the size of the structure to make */ 1901 header = bpf_jit_binary_alloc(image_size, &image_ptr, 1902 sizeof(u32), jit_fill_hole); 1903 /* Not able to allocate memory for the structure then 1904 * we must fall back to the interpretation 1905 */ 1906 if (header == NULL) { 1907 prog = orig_prog; 1908 goto out_imms; 1909 } 1910 1911 /* 2.) Actual pass to generate final JIT code */ 1912 ctx.target = (u32 *) image_ptr; 1913 ctx.idx = 0; 1914 1915 build_prologue(&ctx); 1916 1917 /* If building the body of the JITed code fails somehow, 1918 * we fall back to the interpretation. 1919 */ 1920 if (build_body(&ctx) < 0) { 1921 image_ptr = NULL; 1922 bpf_jit_binary_free(header); 1923 prog = orig_prog; 1924 goto out_imms; 1925 } 1926 build_epilogue(&ctx); 1927 1928 /* 3.) Extra pass to validate JITed Code */ 1929 if (validate_code(&ctx)) { 1930 image_ptr = NULL; 1931 bpf_jit_binary_free(header); 1932 prog = orig_prog; 1933 goto out_imms; 1934 } 1935 flush_icache_range((u32)header, (u32)(ctx.target + ctx.idx)); 1936 1937 if (bpf_jit_enable > 1) 1938 /* there are 2 passes here */ 1939 bpf_jit_dump(prog->len, image_size, 2, ctx.target); 1940 1941 set_memory_ro((unsigned long)header, header->pages); 1942 prog->bpf_func = (void *)ctx.target; 1943 prog->jited = 1; 1944 prog->jited_len = image_size; 1945 1946 out_imms: 1947 #if __LINUX_ARM_ARCH__ < 7 1948 if (ctx.imm_count) 1949 kfree(ctx.imms); 1950 #endif 1951 out_off: 1952 kfree(ctx.offsets); 1953 out: 1954 if (tmp_blinded) 1955 bpf_jit_prog_release_other(prog, prog == orig_prog ? 1956 tmp : orig_prog); 1957 return prog; 1958 } 1959 1960