1/* 2 * linux/arch/arm/mm/proc-xscale.S 3 * 4 * Author: Nicolas Pitre 5 * Created: November 2000 6 * Copyright: (C) 2000, 2001 MontaVista Software Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * MMU functions for the Intel XScale CPUs 13 * 14 * 2001 Aug 21: 15 * some contributions by Brett Gaines <brett.w.gaines@intel.com> 16 * Copyright 2001 by Intel Corp. 17 * 18 * 2001 Sep 08: 19 * Completely revisited, many important fixes 20 * Nicolas Pitre <nico@cam.org> 21 */ 22 23#include <linux/linkage.h> 24#include <linux/init.h> 25#include <asm/assembler.h> 26#include <asm/procinfo.h> 27#include <asm/hardware.h> 28#include <asm/pgtable.h> 29#include <asm/page.h> 30#include <asm/ptrace.h> 31#include "proc-macros.S" 32 33/* 34 * This is the maximum size of an area which will be flushed. If the area 35 * is larger than this, then we flush the whole cache 36 */ 37#define MAX_AREA_SIZE 32768 38 39/* 40 * the cache line size of the I and D cache 41 */ 42#define CACHELINESIZE 32 43 44/* 45 * the size of the data cache 46 */ 47#define CACHESIZE 32768 48 49/* 50 * Virtual address used to allocate the cache when flushed 51 * 52 * This must be an address range which is _never_ used. It should 53 * apparently have a mapping in the corresponding page table for 54 * compatibility with future CPUs that _could_ require it. For instance we 55 * don't care. 56 * 57 * This must be aligned on a 2*CACHESIZE boundary. The code selects one of 58 * the 2 areas in alternance each time the clean_d_cache macro is used. 59 * Without this the XScale core exhibits cache eviction problems and no one 60 * knows why. 61 * 62 * Reminder: the vector table is located at 0xffff0000-0xffff0fff. 63 */ 64#define CLEAN_ADDR 0xfffe0000 65 66/* 67 * This macro is used to wait for a CP15 write and is needed 68 * when we have to ensure that the last operation to the co-pro 69 * was completed before continuing with operation. 70 */ 71 .macro cpwait, rd 72 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 73 mov \rd, \rd @ wait for completion 74 sub pc, pc, #4 @ flush instruction pipeline 75 .endm 76 77 .macro cpwait_ret, lr, rd 78 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 79 sub pc, \lr, \rd, LSR #32 @ wait for completion and 80 @ flush instruction pipeline 81 .endm 82 83/* 84 * This macro cleans the entire dcache using line allocate. 85 * The main loop has been unrolled to reduce loop overhead. 86 * rd and rs are two scratch registers. 87 */ 88 .macro clean_d_cache, rd, rs 89 ldr \rs, =clean_addr 90 ldr \rd, [\rs] 91 eor \rd, \rd, #CACHESIZE 92 str \rd, [\rs] 93 add \rs, \rd, #CACHESIZE 941: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 95 add \rd, \rd, #CACHELINESIZE 96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 97 add \rd, \rd, #CACHELINESIZE 98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 99 add \rd, \rd, #CACHELINESIZE 100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line 101 add \rd, \rd, #CACHELINESIZE 102 teq \rd, \rs 103 bne 1b 104 .endm 105 106 .data 107clean_addr: .word CLEAN_ADDR 108 109 .text 110 111/* 112 * cpu_xscale_proc_init() 113 * 114 * Nothing too exciting at the moment 115 */ 116ENTRY(cpu_xscale_proc_init) 117 mov pc, lr 118 119/* 120 * cpu_xscale_proc_fin() 121 */ 122ENTRY(cpu_xscale_proc_fin) 123 str lr, [sp, #-4]! 124 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 125 msr cpsr_c, r0 126 bl xscale_flush_kern_cache_all @ clean caches 127 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 128 bic r0, r0, #0x1800 @ ...IZ........... 129 bic r0, r0, #0x0006 @ .............CA. 130 mcr p15, 0, r0, c1, c0, 0 @ disable caches 131 ldr pc, [sp], #4 132 133/* 134 * cpu_xscale_reset(loc) 135 * 136 * Perform a soft reset of the system. Put the CPU into the 137 * same state as it would be if it had been reset, and branch 138 * to what would be the reset vector. 139 * 140 * loc: location to jump to for soft reset 141 */ 142 .align 5 143ENTRY(cpu_xscale_reset) 144 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE 145 msr cpsr_c, r1 @ reset CPSR 146 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 147 bic r1, r1, #0x0086 @ ........B....CA. 148 bic r1, r1, #0x3900 @ ..VIZ..S........ 149 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 150 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 151 bic r1, r1, #0x0001 @ ...............M 152 mcr p15, 0, r1, c1, c0, 0 @ ctrl register 153 @ CAUTION: MMU turned off from this point. We count on the pipeline 154 @ already containing those two last instructions to survive. 155 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 156 mov pc, r0 157 158/* 159 * cpu_xscale_do_idle() 160 * 161 * Cause the processor to idle 162 * 163 * For now we do nothing but go to idle mode for every case 164 * 165 * XScale supports clock switching, but using idle mode support 166 * allows external hardware to react to system state changes. 167 */ 168 .align 5 169 170ENTRY(cpu_xscale_do_idle) 171 mov r0, #1 172 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE 173 mov pc, lr 174 175/* ================================= CACHE ================================ */ 176 177/* 178 * flush_user_cache_all() 179 * 180 * Invalidate all cache entries in a particular address 181 * space. 182 */ 183ENTRY(xscale_flush_user_cache_all) 184 /* FALLTHROUGH */ 185 186/* 187 * flush_kern_cache_all() 188 * 189 * Clean and invalidate the entire cache. 190 */ 191ENTRY(xscale_flush_kern_cache_all) 192 mov r2, #VM_EXEC 193 mov ip, #0 194__flush_whole_cache: 195 clean_d_cache r0, r1 196 tst r2, #VM_EXEC 197 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 198 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 199 mov pc, lr 200 201/* 202 * flush_user_cache_range(start, end, vm_flags) 203 * 204 * Invalidate a range of cache entries in the specified 205 * address space. 206 * 207 * - start - start address (may not be aligned) 208 * - end - end address (exclusive, may not be aligned) 209 * - vma - vma_area_struct describing address space 210 */ 211 .align 5 212ENTRY(xscale_flush_user_cache_range) 213 mov ip, #0 214 sub r3, r1, r0 @ calculate total size 215 cmp r3, #MAX_AREA_SIZE 216 bhs __flush_whole_cache 217 2181: tst r2, #VM_EXEC 219 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line 220 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line 221 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line 222 add r0, r0, #CACHELINESIZE 223 cmp r0, r1 224 blo 1b 225 tst r2, #VM_EXEC 226 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB 227 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 228 mov pc, lr 229 230/* 231 * coherent_kern_range(start, end) 232 * 233 * Ensure coherency between the Icache and the Dcache in the 234 * region described by start. If you have non-snooping 235 * Harvard caches, you need to implement this function. 236 * 237 * - start - virtual start address 238 * - end - virtual end address 239 * 240 * Note: single I-cache line invalidation isn't used here since 241 * it also trashes the mini I-cache used by JTAG debuggers. 242 */ 243ENTRY(xscale_coherent_kern_range) 244 /* FALLTHROUGH */ 245 246/* 247 * coherent_user_range(start, end) 248 * 249 * Ensure coherency between the Icache and the Dcache in the 250 * region described by start. If you have non-snooping 251 * Harvard caches, you need to implement this function. 252 * 253 * - start - virtual start address 254 * - end - virtual end address 255 * 256 * Note: single I-cache line invalidation isn't used here since 257 * it also trashes the mini I-cache used by JTAG debuggers. 258 */ 259ENTRY(xscale_coherent_user_range) 260 bic r0, r0, #CACHELINESIZE - 1 2611: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 262 add r0, r0, #CACHELINESIZE 263 cmp r0, r1 264 blo 1b 265 mov r0, #0 266 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 267 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 268 mov pc, lr 269 270/* 271 * flush_kern_dcache_page(void *page) 272 * 273 * Ensure no D cache aliasing occurs, either with itself or 274 * the I cache 275 * 276 * - addr - page aligned address 277 */ 278ENTRY(xscale_flush_kern_dcache_page) 279 add r1, r0, #PAGE_SZ 2801: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 281 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 282 add r0, r0, #CACHELINESIZE 283 cmp r0, r1 284 blo 1b 285 mov r0, #0 286 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB 287 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 288 mov pc, lr 289 290/* 291 * dma_inv_range(start, end) 292 * 293 * Invalidate (discard) the specified virtual address range. 294 * May not write back any entries. If 'start' or 'end' 295 * are not cache line aligned, those lines must be written 296 * back. 297 * 298 * - start - virtual start address 299 * - end - virtual end address 300 */ 301ENTRY(xscale_dma_inv_range) 302 mrc p15, 0, r2, c0, c0, 0 @ read ID 303 eor r2, r2, #0x69000000 304 eor r2, r2, #0x00052000 305 bics r2, r2, #1 306 beq xscale_dma_flush_range 307 308 tst r0, #CACHELINESIZE - 1 309 bic r0, r0, #CACHELINESIZE - 1 310 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 311 tst r1, #CACHELINESIZE - 1 312 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 3131: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 314 add r0, r0, #CACHELINESIZE 315 cmp r0, r1 316 blo 1b 317 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 318 mov pc, lr 319 320/* 321 * dma_clean_range(start, end) 322 * 323 * Clean the specified virtual address range. 324 * 325 * - start - virtual start address 326 * - end - virtual end address 327 */ 328ENTRY(xscale_dma_clean_range) 329 bic r0, r0, #CACHELINESIZE - 1 3301: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 331 add r0, r0, #CACHELINESIZE 332 cmp r0, r1 333 blo 1b 334 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 335 mov pc, lr 336 337/* 338 * dma_flush_range(start, end) 339 * 340 * Clean and invalidate the specified virtual address range. 341 * 342 * - start - virtual start address 343 * - end - virtual end address 344 */ 345ENTRY(xscale_dma_flush_range) 346 bic r0, r0, #CACHELINESIZE - 1 3471: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 348 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 349 add r0, r0, #CACHELINESIZE 350 cmp r0, r1 351 blo 1b 352 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer 353 mov pc, lr 354 355ENTRY(xscale_cache_fns) 356 .long xscale_flush_kern_cache_all 357 .long xscale_flush_user_cache_all 358 .long xscale_flush_user_cache_range 359 .long xscale_coherent_kern_range 360 .long xscale_coherent_user_range 361 .long xscale_flush_kern_dcache_page 362 .long xscale_dma_inv_range 363 .long xscale_dma_clean_range 364 .long xscale_dma_flush_range 365 366ENTRY(cpu_xscale_dcache_clean_area) 3671: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 368 add r0, r0, #CACHELINESIZE 369 subs r1, r1, #CACHELINESIZE 370 bhi 1b 371 mov pc, lr 372 373/* =============================== PageTable ============================== */ 374 375#define PTE_CACHE_WRITE_ALLOCATE 0 376 377/* 378 * cpu_xscale_switch_mm(pgd) 379 * 380 * Set the translation base pointer to be as described by pgd. 381 * 382 * pgd: new page tables 383 */ 384 .align 5 385ENTRY(cpu_xscale_switch_mm) 386 clean_d_cache r1, r2 387 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB 388 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 389 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 390 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 391 cpwait_ret lr, ip 392 393/* 394 * cpu_xscale_set_pte(ptep, pte) 395 * 396 * Set a PTE and flush it out 397 * 398 * Errata 40: must set memory to write-through for user read-only pages. 399 */ 400 .align 5 401ENTRY(cpu_xscale_set_pte) 402 str r1, [r0], #-2048 @ linux version 403 404 bic r2, r1, #0xff0 405 orr r2, r2, #PTE_TYPE_EXT @ extended page 406 407 eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY 408 409 tst r3, #L_PTE_USER @ User? 410 orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w 411 412 tst r3, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? 413 orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w 414 @ combined with user -> user r/w 415 416 @ 417 @ Handle the X bit. We want to set this bit for the minicache 418 @ (U = E = B = W = 0, C = 1) or when write allocate is enabled, 419 @ and we have a writeable, cacheable region. If we ignore the 420 @ U and E bits, we can allow user space to use the minicache as 421 @ well. 422 @ 423 @ X = (C & ~W & ~B) | (C & W & B & write_allocate) 424 @ 425 eor ip, r1, #L_PTE_CACHEABLE 426 tst ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE 427#if PTE_CACHE_WRITE_ALLOCATE 428 eorne ip, r1, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE 429 tstne ip, #L_PTE_CACHEABLE | L_PTE_WRITE | L_PTE_BUFFERABLE 430#endif 431 orreq r2, r2, #PTE_EXT_TEX(1) 432 433 @ 434 @ Erratum 40: The B bit must be cleared for a user read-only 435 @ cacheable page. 436 @ 437 @ B = B & ~(U & C & ~W) 438 @ 439 and ip, r1, #L_PTE_USER | L_PTE_WRITE | L_PTE_CACHEABLE 440 teq ip, #L_PTE_USER | L_PTE_CACHEABLE 441 biceq r2, r2, #PTE_BUFFERABLE 442 443 tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? 444 movne r2, #0 @ no -> fault 445 446 str r2, [r0] @ hardware version 447 mov ip, #0 448 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line 449 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 450 mov pc, lr 451 452 453 .ltorg 454 455 .align 456 457 __INIT 458 459 .type __xscale_setup, #function 460__xscale_setup: 461 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB 462 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer 463 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs 464#ifdef CONFIG_IWMMXT 465 mov r0, #0 @ initially disallow access to CP0/CP1 466#else 467 mov r0, #1 @ Allow access to CP0 468#endif 469 orr r0, r0, #1 << 6 @ cp6 for IOP3xx and Bulverde 470 orr r0, r0, #1 << 13 @ Its undefined whether this 471 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes 472 mrc p15, 0, r0, c1, c0, 0 @ get control register 473 ldr r5, xscale_cr1_clear 474 bic r0, r0, r5 475 ldr r5, xscale_cr1_set 476 orr r0, r0, r5 477 mov pc, lr 478 .size __xscale_setup, . - __xscale_setup 479 480 /* 481 * R 482 * .RVI ZFRS BLDP WCAM 483 * ..11 1.01 .... .101 484 * 485 */ 486 .type xscale_cr1_clear, #object 487 .type xscale_cr1_set, #object 488xscale_cr1_clear: 489 .word 0x3b07 490xscale_cr1_set: 491 .word 0x3905 492 493 __INITDATA 494 495/* 496 * Purpose : Function pointers used to access above functions - all calls 497 * come through these 498 */ 499 500 .type xscale_processor_functions, #object 501ENTRY(xscale_processor_functions) 502 .word v5t_early_abort 503 .word cpu_xscale_proc_init 504 .word cpu_xscale_proc_fin 505 .word cpu_xscale_reset 506 .word cpu_xscale_do_idle 507 .word cpu_xscale_dcache_clean_area 508 .word cpu_xscale_switch_mm 509 .word cpu_xscale_set_pte 510 .size xscale_processor_functions, . - xscale_processor_functions 511 512 .section ".rodata" 513 514 .type cpu_arch_name, #object 515cpu_arch_name: 516 .asciz "armv5te" 517 .size cpu_arch_name, . - cpu_arch_name 518 519 .type cpu_elf_name, #object 520cpu_elf_name: 521 .asciz "v5" 522 .size cpu_elf_name, . - cpu_elf_name 523 524 .type cpu_80200_name, #object 525cpu_80200_name: 526 .asciz "XScale-80200" 527 .size cpu_80200_name, . - cpu_80200_name 528 529 .type cpu_8032x_name, #object 530cpu_8032x_name: 531 .asciz "XScale-IOP8032x Family" 532 .size cpu_8032x_name, . - cpu_8032x_name 533 534 .type cpu_8033x_name, #object 535cpu_8033x_name: 536 .asciz "XScale-IOP8033x Family" 537 .size cpu_8033x_name, . - cpu_8033x_name 538 539 .type cpu_pxa250_name, #object 540cpu_pxa250_name: 541 .asciz "XScale-PXA250" 542 .size cpu_pxa250_name, . - cpu_pxa250_name 543 544 .type cpu_pxa210_name, #object 545cpu_pxa210_name: 546 .asciz "XScale-PXA210" 547 .size cpu_pxa210_name, . - cpu_pxa210_name 548 549 .type cpu_ixp42x_name, #object 550cpu_ixp42x_name: 551 .asciz "XScale-IXP42x Family" 552 .size cpu_ixp42x_name, . - cpu_ixp42x_name 553 554 .type cpu_ixp46x_name, #object 555cpu_ixp46x_name: 556 .asciz "XScale-IXP46x Family" 557 .size cpu_ixp46x_name, . - cpu_ixp46x_name 558 559 .type cpu_ixp2400_name, #object 560cpu_ixp2400_name: 561 .asciz "XScale-IXP2400" 562 .size cpu_ixp2400_name, . - cpu_ixp2400_name 563 564 .type cpu_ixp2800_name, #object 565cpu_ixp2800_name: 566 .asciz "XScale-IXP2800" 567 .size cpu_ixp2800_name, . - cpu_ixp2800_name 568 569 .type cpu_pxa255_name, #object 570cpu_pxa255_name: 571 .asciz "XScale-PXA255" 572 .size cpu_pxa255_name, . - cpu_pxa255_name 573 574 .type cpu_pxa270_name, #object 575cpu_pxa270_name: 576 .asciz "XScale-PXA270" 577 .size cpu_pxa270_name, . - cpu_pxa270_name 578 579 .align 580 581 .section ".proc.info", #alloc, #execinstr 582 583 .type __80200_proc_info,#object 584__80200_proc_info: 585 .long 0x69052000 586 .long 0xfffffff0 587 .long PMD_TYPE_SECT | \ 588 PMD_SECT_BUFFERABLE | \ 589 PMD_SECT_CACHEABLE | \ 590 PMD_SECT_AP_WRITE | \ 591 PMD_SECT_AP_READ 592 b __xscale_setup 593 .long cpu_arch_name 594 .long cpu_elf_name 595 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 596 .long cpu_80200_name 597 .long xscale_processor_functions 598 .long v4wbi_tlb_fns 599 .long xscale_mc_user_fns 600 .long xscale_cache_fns 601 .size __80200_proc_info, . - __80200_proc_info 602 603 .type __8032x_proc_info,#object 604__8032x_proc_info: 605 .long 0x69052420 606 .long 0xfffff5e0 @ mask should accomodate IOP80219 also 607 .long PMD_TYPE_SECT | \ 608 PMD_SECT_BUFFERABLE | \ 609 PMD_SECT_CACHEABLE | \ 610 PMD_SECT_AP_WRITE | \ 611 PMD_SECT_AP_READ 612 b __xscale_setup 613 .long cpu_arch_name 614 .long cpu_elf_name 615 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 616 .long cpu_8032x_name 617 .long xscale_processor_functions 618 .long v4wbi_tlb_fns 619 .long xscale_mc_user_fns 620 .long xscale_cache_fns 621 .size __8032x_proc_info, . - __8032x_proc_info 622 623 .type __8033x_proc_info,#object 624__8033x_proc_info: 625 .long 0x69054010 626 .long 0xffffff30 627 .long PMD_TYPE_SECT | \ 628 PMD_SECT_BUFFERABLE | \ 629 PMD_SECT_CACHEABLE | \ 630 PMD_SECT_AP_WRITE | \ 631 PMD_SECT_AP_READ 632 b __xscale_setup 633 .long cpu_arch_name 634 .long cpu_elf_name 635 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 636 .long cpu_8033x_name 637 .long xscale_processor_functions 638 .long v4wbi_tlb_fns 639 .long xscale_mc_user_fns 640 .long xscale_cache_fns 641 .size __8033x_proc_info, . - __8033x_proc_info 642 643 .type __pxa250_proc_info,#object 644__pxa250_proc_info: 645 .long 0x69052100 646 .long 0xfffff7f0 647 .long PMD_TYPE_SECT | \ 648 PMD_SECT_BUFFERABLE | \ 649 PMD_SECT_CACHEABLE | \ 650 PMD_SECT_AP_WRITE | \ 651 PMD_SECT_AP_READ 652 b __xscale_setup 653 .long cpu_arch_name 654 .long cpu_elf_name 655 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 656 .long cpu_pxa250_name 657 .long xscale_processor_functions 658 .long v4wbi_tlb_fns 659 .long xscale_mc_user_fns 660 .long xscale_cache_fns 661 .size __pxa250_proc_info, . - __pxa250_proc_info 662 663 .type __pxa210_proc_info,#object 664__pxa210_proc_info: 665 .long 0x69052120 666 .long 0xfffff3f0 667 .long PMD_TYPE_SECT | \ 668 PMD_SECT_BUFFERABLE | \ 669 PMD_SECT_CACHEABLE | \ 670 PMD_SECT_AP_WRITE | \ 671 PMD_SECT_AP_READ 672 b __xscale_setup 673 .long cpu_arch_name 674 .long cpu_elf_name 675 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 676 .long cpu_pxa210_name 677 .long xscale_processor_functions 678 .long v4wbi_tlb_fns 679 .long xscale_mc_user_fns 680 .long xscale_cache_fns 681 .size __pxa210_proc_info, . - __pxa210_proc_info 682 683 .type __ixp2400_proc_info, #object 684__ixp2400_proc_info: 685 .long 0x69054190 686 .long 0xfffffff0 687 .long PMD_TYPE_SECT | \ 688 PMD_SECT_BUFFERABLE | \ 689 PMD_SECT_CACHEABLE | \ 690 PMD_SECT_AP_WRITE | \ 691 PMD_SECT_AP_READ 692 b __xscale_setup 693 .long cpu_arch_name 694 .long cpu_elf_name 695 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 696 .long cpu_ixp2400_name 697 .long xscale_processor_functions 698 .long v4wbi_tlb_fns 699 .long xscale_mc_user_fns 700 .long xscale_cache_fns 701 .size __ixp2400_proc_info, . - __ixp2400_proc_info 702 703 .type __ixp2800_proc_info, #object 704__ixp2800_proc_info: 705 .long 0x690541a0 706 .long 0xfffffff0 707 .long PMD_TYPE_SECT | \ 708 PMD_SECT_BUFFERABLE | \ 709 PMD_SECT_CACHEABLE | \ 710 PMD_SECT_AP_WRITE | \ 711 PMD_SECT_AP_READ 712 b __xscale_setup 713 .long cpu_arch_name 714 .long cpu_elf_name 715 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 716 .long cpu_ixp2800_name 717 .long xscale_processor_functions 718 .long v4wbi_tlb_fns 719 .long xscale_mc_user_fns 720 .long xscale_cache_fns 721 .size __ixp2800_proc_info, . - __ixp2800_proc_info 722 723 .type __ixp42x_proc_info, #object 724__ixp42x_proc_info: 725 .long 0x690541c0 726 .long 0xffffffc0 727 .long PMD_TYPE_SECT | \ 728 PMD_SECT_BUFFERABLE | \ 729 PMD_SECT_CACHEABLE | \ 730 PMD_SECT_AP_WRITE | \ 731 PMD_SECT_AP_READ 732 b __xscale_setup 733 .long cpu_arch_name 734 .long cpu_elf_name 735 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 736 .long cpu_ixp42x_name 737 .long xscale_processor_functions 738 .long v4wbi_tlb_fns 739 .long xscale_mc_user_fns 740 .long xscale_cache_fns 741 .size __ixp42x_proc_info, . - __ixp42x_proc_info 742 743 .type __ixp46x_proc_info, #object 744__ixp46x_proc_info: 745 .long 0x69054200 746 .long 0xffffff00 747 .long 0x00000c0e 748 b __xscale_setup 749 .long cpu_arch_name 750 .long cpu_elf_name 751 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 752 .long cpu_ixp46x_name 753 .long xscale_processor_functions 754 .long v4wbi_tlb_fns 755 .long xscale_mc_user_fns 756 .long xscale_cache_fns 757 .size __ixp46x_proc_info, . - __ixp46x_proc_info 758 759 .type __pxa255_proc_info,#object 760__pxa255_proc_info: 761 .long 0x69052d00 762 .long 0xfffffff0 763 .long PMD_TYPE_SECT | \ 764 PMD_SECT_BUFFERABLE | \ 765 PMD_SECT_CACHEABLE | \ 766 PMD_SECT_AP_WRITE | \ 767 PMD_SECT_AP_READ 768 b __xscale_setup 769 .long cpu_arch_name 770 .long cpu_elf_name 771 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 772 .long cpu_pxa255_name 773 .long xscale_processor_functions 774 .long v4wbi_tlb_fns 775 .long xscale_mc_user_fns 776 .long xscale_cache_fns 777 .size __pxa255_proc_info, . - __pxa255_proc_info 778 779 .type __pxa270_proc_info,#object 780__pxa270_proc_info: 781 .long 0x69054110 782 .long 0xfffffff0 783 .long PMD_TYPE_SECT | \ 784 PMD_SECT_BUFFERABLE | \ 785 PMD_SECT_CACHEABLE | \ 786 PMD_SECT_AP_WRITE | \ 787 PMD_SECT_AP_READ 788 b __xscale_setup 789 .long cpu_arch_name 790 .long cpu_elf_name 791 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 792 .long cpu_pxa270_name 793 .long xscale_processor_functions 794 .long v4wbi_tlb_fns 795 .long xscale_mc_user_fns 796 .long xscale_cache_fns 797 .size __pxa270_proc_info, . - __pxa270_proc_info 798 799