xref: /linux/arch/arm/mm/proc-v7.S (revision d39d0ed196aa1685bb24771e92f78633c66ac9cb) 
1/*
2 *  linux/arch/arm/mm/proc-v7.S
3 *
4 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *  This is the "shell" of the ARMv7 processor support.
11 */
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15#include <asm/asm-offsets.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h>
19
20#include "proc-macros.S"
21
22#define TTB_S		(1 << 1)
23#define TTB_RGN_NC	(0 << 3)
24#define TTB_RGN_OC_WBWA	(1 << 3)
25#define TTB_RGN_OC_WT	(2 << 3)
26#define TTB_RGN_OC_WB	(3 << 3)
27#define TTB_NOS		(1 << 5)
28#define TTB_IRGN_NC	((0 << 0) | (0 << 6))
29#define TTB_IRGN_WBWA	((0 << 0) | (1 << 6))
30#define TTB_IRGN_WT	((1 << 0) | (0 << 6))
31#define TTB_IRGN_WB	((1 << 0) | (1 << 6))
32
33#ifndef CONFIG_SMP
34/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
35#define TTB_FLAGS	TTB_IRGN_WB|TTB_RGN_OC_WB
36#define PMD_FLAGS	PMD_SECT_WB
37#else
38/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
39#define TTB_FLAGS	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
40#define PMD_FLAGS	PMD_SECT_WBWA|PMD_SECT_S
41#endif
42
43ENTRY(cpu_v7_proc_init)
44	mov	pc, lr
45ENDPROC(cpu_v7_proc_init)
46
47ENTRY(cpu_v7_proc_fin)
48	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
49	bic	r0, r0, #0x1000			@ ...i............
50	bic	r0, r0, #0x0006			@ .............ca.
51	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
52	mov	pc, lr
53ENDPROC(cpu_v7_proc_fin)
54
55/*
56 *	cpu_v7_reset(loc)
57 *
58 *	Perform a soft reset of the system.  Put the CPU into the
59 *	same state as it would be if it had been reset, and branch
60 *	to what would be the reset vector.
61 *
62 *	- loc   - location to jump to for soft reset
63 */
64	.align	5
65ENTRY(cpu_v7_reset)
66	mov	pc, r0
67ENDPROC(cpu_v7_reset)
68
69/*
70 *	cpu_v7_do_idle()
71 *
72 *	Idle the processor (eg, wait for interrupt).
73 *
74 *	IRQs are already disabled.
75 */
76ENTRY(cpu_v7_do_idle)
77	dsb					@ WFI may enter a low-power mode
78	wfi
79	mov	pc, lr
80ENDPROC(cpu_v7_do_idle)
81
82ENTRY(cpu_v7_dcache_clean_area)
83#ifndef TLB_CAN_READ_FROM_L1_CACHE
84	dcache_line_size r2, r3
851:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
86	add	r0, r0, r2
87	subs	r1, r1, r2
88	bhi	1b
89	dsb
90#endif
91	mov	pc, lr
92ENDPROC(cpu_v7_dcache_clean_area)
93
94/*
95 *	cpu_v7_switch_mm(pgd_phys, tsk)
96 *
97 *	Set the translation table base pointer to be pgd_phys
98 *
99 *	- pgd_phys - physical address of new TTB
100 *
101 *	It is assumed that:
102 *	- we are not using split page tables
103 */
104ENTRY(cpu_v7_switch_mm)
105#ifdef CONFIG_MMU
106	mov	r2, #0
107	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
108	orr	r0, r0, #TTB_FLAGS
109#ifdef CONFIG_ARM_ERRATA_430973
110	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
111#endif
112	mcr	p15, 0, r2, c13, c0, 1		@ set reserved context ID
113	isb
1141:	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
115	isb
116	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
117	isb
118#endif
119	mov	pc, lr
120ENDPROC(cpu_v7_switch_mm)
121
122/*
123 *	cpu_v7_set_pte_ext(ptep, pte)
124 *
125 *	Set a level 2 translation table entry.
126 *
127 *	- ptep  - pointer to level 2 translation table entry
128 *		  (hardware version is stored at -1024 bytes)
129 *	- pte   - PTE value to store
130 *	- ext	- value for extended PTE bits
131 */
132ENTRY(cpu_v7_set_pte_ext)
133#ifdef CONFIG_MMU
134 ARM(	str	r1, [r0], #-2048	)	@ linux version
135 THUMB(	str	r1, [r0]		)	@ linux version
136 THUMB(	sub	r0, r0, #2048		)
137
138	bic	r3, r1, #0x000003f0
139	bic	r3, r3, #PTE_TYPE_MASK
140	orr	r3, r3, r2
141	orr	r3, r3, #PTE_EXT_AP0 | 2
142
143	tst	r1, #1 << 4
144	orrne	r3, r3, #PTE_EXT_TEX(1)
145
146	tst	r1, #L_PTE_WRITE
147	tstne	r1, #L_PTE_DIRTY
148	orreq	r3, r3, #PTE_EXT_APX
149
150	tst	r1, #L_PTE_USER
151	orrne	r3, r3, #PTE_EXT_AP1
152	tstne	r3, #PTE_EXT_APX
153	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
154
155	tst	r1, #L_PTE_EXEC
156	orreq	r3, r3, #PTE_EXT_XN
157
158	tst	r1, #L_PTE_YOUNG
159	tstne	r1, #L_PTE_PRESENT
160	moveq	r3, #0
161
162	str	r3, [r0]
163	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
164#endif
165	mov	pc, lr
166ENDPROC(cpu_v7_set_pte_ext)
167
168cpu_v7_name:
169	.ascii	"ARMv7 Processor"
170	.align
171
172	__INIT
173
174/*
175 *	__v7_setup
176 *
177 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
178 *	on.  Return in r0 the new CP15 C1 control register setting.
179 *
180 *	We automatically detect if we have a Harvard cache, and use the
181 *	Harvard cache control instructions insead of the unified cache
182 *	control instructions.
183 *
184 *	This should be able to cover all ARMv7 cores.
185 *
186 *	It is assumed that:
187 *	- cache type register is implemented
188 */
189__v7_setup:
190#ifdef CONFIG_SMP
191	mrc	p15, 0, r0, c1, c0, 1
192	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
193	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
194	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
195#endif
196	adr	r12, __v7_setup_stack		@ the local stack
197	stmia	r12, {r0-r5, r7, r9, r11, lr}
198	bl	v7_flush_dcache_all
199	ldmia	r12, {r0-r5, r7, r9, r11, lr}
200
201	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
202	and	r10, r0, #0xff000000		@ ARM?
203	teq	r10, #0x41000000
204	bne	2f
205	and	r5, r0, #0x00f00000		@ variant
206	and	r6, r0, #0x0000000f		@ revision
207	orr	r0, r6, r5, lsr #20-4		@ combine variant and revision
208
209#ifdef CONFIG_ARM_ERRATA_430973
210	teq	r5, #0x00100000			@ only present in r1p*
211	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
212	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
213	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
214#endif
215#ifdef CONFIG_ARM_ERRATA_458693
216	teq	r0, #0x20			@ only present in r2p0
217	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
218	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
219	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
220	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
221#endif
222#ifdef CONFIG_ARM_ERRATA_460075
223	teq	r0, #0x20			@ only present in r2p0
224	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
225	tsteq	r10, #1 << 22
226	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
227	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
228#endif
229
2302:	mov	r10, #0
231#ifdef HARVARD_CACHE
232	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
233#endif
234	dsb
235#ifdef CONFIG_MMU
236	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
237	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
238	orr	r4, r4, #TTB_FLAGS
239	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
240	mov	r10, #0x1f			@ domains 0, 1 = manager
241	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
242	/*
243	 * Memory region attributes with SCTLR.TRE=1
244	 *
245	 *   n = TEX[0],C,B
246	 *   TR = PRRR[2n+1:2n]		- memory type
247	 *   IR = NMRR[2n+1:2n]		- inner cacheable property
248	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property
249	 *
250	 *			n	TR	IR	OR
251	 *   UNCACHED		000	00
252	 *   BUFFERABLE		001	10	00	00
253	 *   WRITETHROUGH	010	10	10	10
254	 *   WRITEBACK		011	10	11	11
255	 *   reserved		110
256	 *   WRITEALLOC		111	10	01	01
257	 *   DEV_SHARED		100	01
258	 *   DEV_NONSHARED	100	01
259	 *   DEV_WC		001	10
260	 *   DEV_CACHED		011	10
261	 *
262	 * Other attributes:
263	 *
264	 *   DS0 = PRRR[16] = 0		- device shareable property
265	 *   DS1 = PRRR[17] = 1		- device shareable property
266	 *   NS0 = PRRR[18] = 0		- normal shareable property
267	 *   NS1 = PRRR[19] = 1		- normal shareable property
268	 *   NOS = PRRR[24+n] = 1	- not outer shareable
269	 */
270	ldr	r5, =0xff0a81a8			@ PRRR
271	ldr	r6, =0x40e040e0			@ NMRR
272	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
273	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
274#endif
275	adr	r5, v7_crval
276	ldmia	r5, {r5, r6}
277#ifdef CONFIG_CPU_ENDIAN_BE8
278	orr	r6, r6, #1 << 25		@ big-endian page tables
279#endif
280   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
281	bic	r0, r0, r5			@ clear bits them
282	orr	r0, r0, r6			@ set them
283 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
284	mov	pc, lr				@ return to head.S:__ret
285ENDPROC(__v7_setup)
286
287	/*   AT
288	 *  TFR   EV X F   I D LR    S
289	 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
290	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
291	 *    1    0 110       0011 1100 .111 1101 < we want
292	 */
293	.type	v7_crval, #object
294v7_crval:
295	crval	clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
296
297__v7_setup_stack:
298	.space	4 * 11				@ 11 registers
299
300	.type	v7_processor_functions, #object
301ENTRY(v7_processor_functions)
302	.word	v7_early_abort
303	.word	v7_pabort
304	.word	cpu_v7_proc_init
305	.word	cpu_v7_proc_fin
306	.word	cpu_v7_reset
307	.word	cpu_v7_do_idle
308	.word	cpu_v7_dcache_clean_area
309	.word	cpu_v7_switch_mm
310	.word	cpu_v7_set_pte_ext
311	.size	v7_processor_functions, . - v7_processor_functions
312
313	.type	cpu_arch_name, #object
314cpu_arch_name:
315	.asciz	"armv7"
316	.size	cpu_arch_name, . - cpu_arch_name
317
318	.type	cpu_elf_name, #object
319cpu_elf_name:
320	.asciz	"v7"
321	.size	cpu_elf_name, . - cpu_elf_name
322	.align
323
324	.section ".proc.info.init", #alloc, #execinstr
325
326	/*
327	 * Match any ARMv7 processor core.
328	 */
329	.type	__v7_proc_info, #object
330__v7_proc_info:
331	.long	0x000f0000		@ Required ID value
332	.long	0x000f0000		@ Mask for ID
333	.long   PMD_TYPE_SECT | \
334		PMD_SECT_AP_WRITE | \
335		PMD_SECT_AP_READ | \
336		PMD_FLAGS
337	.long   PMD_TYPE_SECT | \
338		PMD_SECT_XN | \
339		PMD_SECT_AP_WRITE | \
340		PMD_SECT_AP_READ
341	b	__v7_setup
342	.long	cpu_arch_name
343	.long	cpu_elf_name
344	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
345	.long	cpu_v7_name
346	.long	v7_processor_functions
347	.long	v7wbi_tlb_fns
348	.long	v6_user_fns
349	.long	v7_cache_fns
350	.size	__v7_proc_info, . - __v7_proc_info
351