1/* 2 * linux/arch/arm/mm/proc-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This is the "shell" of the ARMv7 processor support. 11 */ 12#include <linux/init.h> 13#include <linux/linkage.h> 14#include <asm/assembler.h> 15#include <asm/asm-offsets.h> 16#include <asm/hwcap.h> 17#include <asm/pgtable-hwdef.h> 18#include <asm/pgtable.h> 19 20#include "proc-macros.S" 21 22#ifdef CONFIG_ARM_LPAE 23#include "proc-v7-3level.S" 24#else 25#include "proc-v7-2level.S" 26#endif 27 28ENTRY(cpu_v7_proc_init) 29 mov pc, lr 30ENDPROC(cpu_v7_proc_init) 31 32ENTRY(cpu_v7_proc_fin) 33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 34 bic r0, r0, #0x1000 @ ...i............ 35 bic r0, r0, #0x0006 @ .............ca. 36 mcr p15, 0, r0, c1, c0, 0 @ disable caches 37 mov pc, lr 38ENDPROC(cpu_v7_proc_fin) 39 40/* 41 * cpu_v7_reset(loc) 42 * 43 * Perform a soft reset of the system. Put the CPU into the 44 * same state as it would be if it had been reset, and branch 45 * to what would be the reset vector. 46 * 47 * - loc - location to jump to for soft reset 48 * 49 * This code must be executed using a flat identity mapping with 50 * caches disabled. 51 */ 52 .align 5 53 .pushsection .idmap.text, "ax" 54ENTRY(cpu_v7_reset) 55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register 56 bic r1, r1, #0x1 @ ...............m 57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions) 58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU 59 isb 60 bx r0 61ENDPROC(cpu_v7_reset) 62 .popsection 63 64/* 65 * cpu_v7_do_idle() 66 * 67 * Idle the processor (eg, wait for interrupt). 68 * 69 * IRQs are already disabled. 70 */ 71ENTRY(cpu_v7_do_idle) 72 dsb @ WFI may enter a low-power mode 73 wfi 74 mov pc, lr 75ENDPROC(cpu_v7_do_idle) 76 77ENTRY(cpu_v7_dcache_clean_area) 78#ifndef TLB_CAN_READ_FROM_L1_CACHE 79 dcache_line_size r2, r3 801: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 81 add r0, r0, r2 82 subs r1, r1, r2 83 bhi 1b 84 dsb 85#endif 86 mov pc, lr 87ENDPROC(cpu_v7_dcache_clean_area) 88 89 string cpu_v7_name, "ARMv7 Processor" 90 .align 91 92/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ 93.globl cpu_v7_suspend_size 94.equ cpu_v7_suspend_size, 4 * 8 95#ifdef CONFIG_ARM_CPU_SUSPEND 96ENTRY(cpu_v7_do_suspend) 97 stmfd sp!, {r4 - r10, lr} 98 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 99 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID 100 stmia r0!, {r4 - r5} 101 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 102 mrc p15, 0, r7, c2, c0, 1 @ TTB 1 103 mrc p15, 0, r11, c2, c0, 2 @ TTB control register 104 mrc p15, 0, r8, c1, c0, 0 @ Control register 105 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register 106 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control 107 stmia r0, {r6 - r11} 108 ldmfd sp!, {r4 - r10, pc} 109ENDPROC(cpu_v7_do_suspend) 110 111ENTRY(cpu_v7_do_resume) 112 mov ip, #0 113 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs 114 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 115 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID 116 ldmia r0!, {r4 - r5} 117 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 118 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID 119 ldmia r0, {r6 - r11} 120 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 121#ifndef CONFIG_ARM_LPAE 122 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) 123 ALT_UP(orr r1, r1, #TTB_FLAGS_UP) 124#endif 125 mcr p15, 0, r1, c2, c0, 0 @ TTB 0 126 mcr p15, 0, r7, c2, c0, 1 @ TTB 1 127 mcr p15, 0, r11, c2, c0, 2 @ TTB control register 128 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register 129 teq r4, r9 @ Is it already set? 130 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it 131 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control 132 ldr r4, =PRRR @ PRRR 133 ldr r5, =NMRR @ NMRR 134 mcr p15, 0, r4, c10, c2, 0 @ write PRRR 135 mcr p15, 0, r5, c10, c2, 1 @ write NMRR 136 isb 137 dsb 138 mov r0, r8 @ control register 139 b cpu_resume_mmu 140ENDPROC(cpu_v7_do_resume) 141#endif 142 143 __CPUINIT 144 145/* 146 * __v7_setup 147 * 148 * Initialise TLB, Caches, and MMU state ready to switch the MMU 149 * on. Return in r0 the new CP15 C1 control register setting. 150 * 151 * This should be able to cover all ARMv7 cores. 152 * 153 * It is assumed that: 154 * - cache type register is implemented 155 */ 156__v7_ca5mp_setup: 157__v7_ca9mp_setup: 158 mov r10, #(1 << 0) @ TLB ops broadcasting 159 b 1f 160__v7_ca7mp_setup: 161__v7_ca15mp_setup: 162 mov r10, #0 1631: 164#ifdef CONFIG_SMP 165 ALT_SMP(mrc p15, 0, r0, c1, c0, 1) 166 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP 167 tst r0, #(1 << 6) @ SMP/nAMP mode enabled? 168 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode 169 orreq r0, r0, r10 @ Enable CPU-specific SMP bits 170 mcreq p15, 0, r0, c1, c0, 1 171#endif 172 173__v7_pj4b_setup: 174#ifdef CONFIG_CPU_PJ4B 175 176/* Auxiliary Debug Modes Control 1 Register */ 177#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */ 178#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */ 179#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */ 180#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */ 181 182/* Auxiliary Debug Modes Control 2 Register */ 183#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */ 184#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */ 185#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */ 186#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */ 187#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */ 188#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\ 189 PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR) 190 191/* Auxiliary Functional Modes Control Register 0 */ 192#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */ 193#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */ 194#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */ 195 196/* Auxiliary Debug Modes Control 0 Register */ 197#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */ 198 199 /* Auxiliary Debug Modes Control 1 Register */ 200 mrc p15, 1, r0, c15, c1, 1 201 orr r0, r0, #PJ4B_CLEAN_LINE 202 orr r0, r0, #PJ4B_BCK_OFF_STREX 203 orr r0, r0, #PJ4B_INTER_PARITY 204 bic r0, r0, #PJ4B_STATIC_BP 205 mcr p15, 1, r0, c15, c1, 1 206 207 /* Auxiliary Debug Modes Control 2 Register */ 208 mrc p15, 1, r0, c15, c1, 2 209 bic r0, r0, #PJ4B_FAST_LDR 210 orr r0, r0, #PJ4B_AUX_DBG_CTRL2 211 mcr p15, 1, r0, c15, c1, 2 212 213 /* Auxiliary Functional Modes Control Register 0 */ 214 mrc p15, 1, r0, c15, c2, 0 215#ifdef CONFIG_SMP 216 orr r0, r0, #PJ4B_SMP_CFB 217#endif 218 orr r0, r0, #PJ4B_L1_PAR_CHK 219 orr r0, r0, #PJ4B_BROADCAST_CACHE 220 mcr p15, 1, r0, c15, c2, 0 221 222 /* Auxiliary Debug Modes Control 0 Register */ 223 mrc p15, 1, r0, c15, c1, 0 224 orr r0, r0, #PJ4B_WFI_WFE 225 mcr p15, 1, r0, c15, c1, 0 226 227#endif /* CONFIG_CPU_PJ4B */ 228 229__v7_setup: 230 adr r12, __v7_setup_stack @ the local stack 231 stmia r12, {r0-r5, r7, r9, r11, lr} 232 bl v7_flush_dcache_louis 233 ldmia r12, {r0-r5, r7, r9, r11, lr} 234 235 mrc p15, 0, r0, c0, c0, 0 @ read main ID register 236 and r10, r0, #0xff000000 @ ARM? 237 teq r10, #0x41000000 238 bne 3f 239 and r5, r0, #0x00f00000 @ variant 240 and r6, r0, #0x0000000f @ revision 241 orr r6, r6, r5, lsr #20-4 @ combine variant and revision 242 ubfx r0, r0, #4, #12 @ primary part number 243 244 /* Cortex-A8 Errata */ 245 ldr r10, =0x00000c08 @ Cortex-A8 primary part number 246 teq r0, r10 247 bne 2f 248#ifdef CONFIG_ARM_ERRATA_430973 249 teq r5, #0x00100000 @ only present in r1p* 250 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 251 orreq r10, r10, #(1 << 6) @ set IBE to 1 252 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 253#endif 254#ifdef CONFIG_ARM_ERRATA_458693 255 teq r6, #0x20 @ only present in r2p0 256 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 257 orreq r10, r10, #(1 << 5) @ set L1NEON to 1 258 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 259 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 260#endif 261#ifdef CONFIG_ARM_ERRATA_460075 262 teq r6, #0x20 @ only present in r2p0 263 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register 264 tsteq r10, #1 << 22 265 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit 266 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register 267#endif 268 b 3f 269 270 /* Cortex-A9 Errata */ 2712: ldr r10, =0x00000c09 @ Cortex-A9 primary part number 272 teq r0, r10 273 bne 3f 274#ifdef CONFIG_ARM_ERRATA_742230 275 cmp r6, #0x22 @ only present up to r2p2 276 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register 277 orrle r10, r10, #1 << 4 @ set bit #4 278 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register 279#endif 280#ifdef CONFIG_ARM_ERRATA_742231 281 teq r6, #0x20 @ present in r2p0 282 teqne r6, #0x21 @ present in r2p1 283 teqne r6, #0x22 @ present in r2p2 284 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 285 orreq r10, r10, #1 << 12 @ set bit #12 286 orreq r10, r10, #1 << 22 @ set bit #22 287 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 288#endif 289#ifdef CONFIG_ARM_ERRATA_743622 290 teq r5, #0x00200000 @ only present in r2p* 291 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register 292 orreq r10, r10, #1 << 6 @ set bit #6 293 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register 294#endif 295#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP) 296 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0 297 ALT_UP_B(1f) 298 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register 299 orrlt r10, r10, #1 << 11 @ set bit #11 300 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register 3011: 302#endif 303 3043: mov r10, #0 305 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 306 dsb 307#ifdef CONFIG_MMU 308 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 309 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup 310 ldr r5, =PRRR @ PRRR 311 ldr r6, =NMRR @ NMRR 312 mcr p15, 0, r5, c10, c2, 0 @ write PRRR 313 mcr p15, 0, r6, c10, c2, 1 @ write NMRR 314#endif 315#ifndef CONFIG_ARM_THUMBEE 316 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE 317 and r0, r0, #(0xf << 12) @ ThumbEE enabled field 318 teq r0, #(1 << 12) @ check if ThumbEE is present 319 bne 1f 320 mov r5, #0 321 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0 322 mrc p14, 6, r0, c0, c0, 0 @ load TEECR 323 orr r0, r0, #1 @ set the 1st bit in order to 324 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access 3251: 326#endif 327 adr r5, v7_crval 328 ldmia r5, {r5, r6} 329#ifdef CONFIG_CPU_ENDIAN_BE8 330 orr r6, r6, #1 << 25 @ big-endian page tables 331#endif 332#ifdef CONFIG_SWP_EMULATE 333 orr r5, r5, #(1 << 10) @ set SW bit in "clear" 334 bic r6, r6, #(1 << 10) @ clear it in "mmuset" 335#endif 336 mrc p15, 0, r0, c1, c0, 0 @ read control register 337 bic r0, r0, r5 @ clear bits them 338 orr r0, r0, r6 @ set them 339 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions 340 mov pc, lr @ return to head.S:__ret 341ENDPROC(__v7_setup) 342 343 .align 2 344__v7_setup_stack: 345 .space 4 * 11 @ 11 registers 346 347 __INITDATA 348 349 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) 350 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 351 352 .section ".rodata" 353 354 string cpu_arch_name, "armv7" 355 string cpu_elf_name, "v7" 356 .align 357 358 .section ".proc.info.init", #alloc, #execinstr 359 360 /* 361 * Standard v7 proc info content 362 */ 363.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0 364 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ 365 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags) 366 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ 367 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags) 368 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \ 369 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags 370 W(b) \initfunc 371 .long cpu_arch_name 372 .long cpu_elf_name 373 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ 374 HWCAP_EDSP | HWCAP_TLS | \hwcaps 375 .long cpu_v7_name 376 .long v7_processor_functions 377 .long v7wbi_tlb_fns 378 .long v6_user_fns 379 .long v7_cache_fns 380.endm 381 382#ifndef CONFIG_ARM_LPAE 383 /* 384 * ARM Ltd. Cortex A5 processor. 385 */ 386 .type __v7_ca5mp_proc_info, #object 387__v7_ca5mp_proc_info: 388 .long 0x410fc050 389 .long 0xff0ffff0 390 __v7_proc __v7_ca5mp_setup 391 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info 392 393 /* 394 * ARM Ltd. Cortex A9 processor. 395 */ 396 .type __v7_ca9mp_proc_info, #object 397__v7_ca9mp_proc_info: 398 .long 0x410fc090 399 .long 0xff0ffff0 400 __v7_proc __v7_ca9mp_setup 401 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info 402 403 /* 404 * Marvell PJ4B processor. 405 */ 406 .type __v7_pj4b_proc_info, #object 407__v7_pj4b_proc_info: 408 .long 0x562f5840 409 .long 0xfffffff0 410 __v7_proc __v7_pj4b_setup 411 .size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info 412#endif /* CONFIG_ARM_LPAE */ 413 414 /* 415 * ARM Ltd. Cortex A7 processor. 416 */ 417 .type __v7_ca7mp_proc_info, #object 418__v7_ca7mp_proc_info: 419 .long 0x410fc070 420 .long 0xff0ffff0 421 __v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV 422 .size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info 423 424 /* 425 * ARM Ltd. Cortex A15 processor. 426 */ 427 .type __v7_ca15mp_proc_info, #object 428__v7_ca15mp_proc_info: 429 .long 0x410fc0f0 430 .long 0xff0ffff0 431 __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV 432 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info 433 434 /* 435 * Match any ARMv7 processor core. 436 */ 437 .type __v7_proc_info, #object 438__v7_proc_info: 439 .long 0x000f0000 @ Required ID value 440 .long 0x000f0000 @ Mask for ID 441 __v7_proc __v7_setup 442 .size __v7_proc_info, . - __v7_proc_info 443