xref: /linux/arch/arm/mm/proc-v7.S (revision b43ab901d671e3e3cad425ea5e9a3c74e266dcdd) 
1/*
2 *  linux/arch/arm/mm/proc-v7.S
3 *
4 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *  This is the "shell" of the ARMv7 processor support.
11 */
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15#include <asm/asm-offsets.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h>
19
20#include "proc-macros.S"
21
22#ifdef CONFIG_ARM_LPAE
23#include "proc-v7-3level.S"
24#else
25#include "proc-v7-2level.S"
26#endif
27
28ENTRY(cpu_v7_proc_init)
29	mov	pc, lr
30ENDPROC(cpu_v7_proc_init)
31
32ENTRY(cpu_v7_proc_fin)
33	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
34	bic	r0, r0, #0x1000			@ ...i............
35	bic	r0, r0, #0x0006			@ .............ca.
36	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
37	mov	pc, lr
38ENDPROC(cpu_v7_proc_fin)
39
40/*
41 *	cpu_v7_reset(loc)
42 *
43 *	Perform a soft reset of the system.  Put the CPU into the
44 *	same state as it would be if it had been reset, and branch
45 *	to what would be the reset vector.
46 *
47 *	- loc   - location to jump to for soft reset
48 *
49 *	This code must be executed using a flat identity mapping with
50 *      caches disabled.
51 */
52	.align	5
53	.pushsection	.idmap.text, "ax"
54ENTRY(cpu_v7_reset)
55	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
56	bic	r1, r1, #0x1			@ ...............m
57 THUMB(	bic	r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
58	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
59	isb
60	mov	pc, r0
61ENDPROC(cpu_v7_reset)
62	.popsection
63
64/*
65 *	cpu_v7_do_idle()
66 *
67 *	Idle the processor (eg, wait for interrupt).
68 *
69 *	IRQs are already disabled.
70 */
71ENTRY(cpu_v7_do_idle)
72	dsb					@ WFI may enter a low-power mode
73	wfi
74	mov	pc, lr
75ENDPROC(cpu_v7_do_idle)
76
77ENTRY(cpu_v7_dcache_clean_area)
78#ifndef TLB_CAN_READ_FROM_L1_CACHE
79	dcache_line_size r2, r3
801:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
81	add	r0, r0, r2
82	subs	r1, r1, r2
83	bhi	1b
84	dsb
85#endif
86	mov	pc, lr
87ENDPROC(cpu_v7_dcache_clean_area)
88
89	string	cpu_v7_name, "ARMv7 Processor"
90	.align
91
92/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
93.globl	cpu_v7_suspend_size
94.equ	cpu_v7_suspend_size, 4 * 8
95#ifdef CONFIG_ARM_CPU_SUSPEND
96ENTRY(cpu_v7_do_suspend)
97	stmfd	sp!, {r4 - r10, lr}
98	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
99	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
100	stmia	r0!, {r4 - r5}
101	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
102	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
103	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
104	mrc	p15, 0, r8, c1, c0, 0	@ Control register
105	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
106	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
107	stmia	r0, {r6 - r11}
108	ldmfd	sp!, {r4 - r10, pc}
109ENDPROC(cpu_v7_do_suspend)
110
111ENTRY(cpu_v7_do_resume)
112	mov	ip, #0
113	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
114	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
115	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
116	ldmia	r0!, {r4 - r5}
117	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
118	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
119	ldmia	r0, {r6 - r11}
120	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
121#ifndef CONFIG_ARM_LPAE
122	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
123	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
124#endif
125	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
126	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
127	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
128	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
129	teq	r4, r9			@ Is it already set?
130	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
131	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
132	ldr	r4, =PRRR		@ PRRR
133	ldr	r5, =NMRR		@ NMRR
134	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
135	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
136	isb
137	dsb
138	mov	r0, r8			@ control register
139	b	cpu_resume_mmu
140ENDPROC(cpu_v7_do_resume)
141#endif
142
143	__CPUINIT
144
145/*
146 *	__v7_setup
147 *
148 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
149 *	on.  Return in r0 the new CP15 C1 control register setting.
150 *
151 *	We automatically detect if we have a Harvard cache, and use the
152 *	Harvard cache control instructions insead of the unified cache
153 *	control instructions.
154 *
155 *	This should be able to cover all ARMv7 cores.
156 *
157 *	It is assumed that:
158 *	- cache type register is implemented
159 */
160__v7_ca5mp_setup:
161__v7_ca9mp_setup:
162	mov	r10, #(1 << 0)			@ TLB ops broadcasting
163	b	1f
164__v7_ca7mp_setup:
165__v7_ca15mp_setup:
166	mov	r10, #0
1671:
168#ifdef CONFIG_SMP
169	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
170	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
171	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
172	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
173	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
174	mcreq	p15, 0, r0, c1, c0, 1
175#endif
176__v7_setup:
177	adr	r12, __v7_setup_stack		@ the local stack
178	stmia	r12, {r0-r5, r7, r9, r11, lr}
179	bl	v7_flush_dcache_all
180	ldmia	r12, {r0-r5, r7, r9, r11, lr}
181
182	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
183	and	r10, r0, #0xff000000		@ ARM?
184	teq	r10, #0x41000000
185	bne	3f
186	and	r5, r0, #0x00f00000		@ variant
187	and	r6, r0, #0x0000000f		@ revision
188	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
189	ubfx	r0, r0, #4, #12			@ primary part number
190
191	/* Cortex-A8 Errata */
192	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
193	teq	r0, r10
194	bne	2f
195#ifdef CONFIG_ARM_ERRATA_430973
196	teq	r5, #0x00100000			@ only present in r1p*
197	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
198	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
199	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
200#endif
201#ifdef CONFIG_ARM_ERRATA_458693
202	teq	r6, #0x20			@ only present in r2p0
203	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
204	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
205	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
206	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
207#endif
208#ifdef CONFIG_ARM_ERRATA_460075
209	teq	r6, #0x20			@ only present in r2p0
210	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
211	tsteq	r10, #1 << 22
212	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
213	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
214#endif
215	b	3f
216
217	/* Cortex-A9 Errata */
2182:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
219	teq	r0, r10
220	bne	3f
221#ifdef CONFIG_ARM_ERRATA_742230
222	cmp	r6, #0x22			@ only present up to r2p2
223	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
224	orrle	r10, r10, #1 << 4		@ set bit #4
225	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
226#endif
227#ifdef CONFIG_ARM_ERRATA_742231
228	teq	r6, #0x20			@ present in r2p0
229	teqne	r6, #0x21			@ present in r2p1
230	teqne	r6, #0x22			@ present in r2p2
231	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
232	orreq	r10, r10, #1 << 12		@ set bit #12
233	orreq	r10, r10, #1 << 22		@ set bit #22
234	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
235#endif
236#ifdef CONFIG_ARM_ERRATA_743622
237	teq	r6, #0x20			@ present in r2p0
238	teqne	r6, #0x21			@ present in r2p1
239	teqne	r6, #0x22			@ present in r2p2
240	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
241	orreq	r10, r10, #1 << 6		@ set bit #6
242	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
243#endif
244#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
245	ALT_SMP(cmp r6, #0x30)			@ present prior to r3p0
246	ALT_UP_B(1f)
247	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
248	orrlt	r10, r10, #1 << 11		@ set bit #11
249	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
2501:
251#endif
252
2533:	mov	r10, #0
254#ifdef HARVARD_CACHE
255	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
256#endif
257	dsb
258#ifdef CONFIG_MMU
259	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
260	v7_ttb_setup r10, r4, r8, r5		@ TTBCR, TTBRx setup
261	ldr	r5, =PRRR			@ PRRR
262	ldr	r6, =NMRR			@ NMRR
263	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
264	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
265#endif
266	adr	r5, v7_crval
267	ldmia	r5, {r5, r6}
268#ifdef CONFIG_CPU_ENDIAN_BE8
269	orr	r6, r6, #1 << 25		@ big-endian page tables
270#endif
271#ifdef CONFIG_SWP_EMULATE
272	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
273	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
274#endif
275   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
276	bic	r0, r0, r5			@ clear bits them
277	orr	r0, r0, r6			@ set them
278 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
279	mov	pc, lr				@ return to head.S:__ret
280ENDPROC(__v7_setup)
281
282	.align	2
283__v7_setup_stack:
284	.space	4 * 11				@ 11 registers
285
286	__INITDATA
287
288	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
289	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
290
291	.section ".rodata"
292
293	string	cpu_arch_name, "armv7"
294	string	cpu_elf_name, "v7"
295	.align
296
297	.section ".proc.info.init", #alloc, #execinstr
298
299	/*
300	 * Standard v7 proc info content
301	 */
302.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
303	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
304			PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
305	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
306			PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
307	.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
308		PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
309	W(b)	\initfunc
310	.long	cpu_arch_name
311	.long	cpu_elf_name
312	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
313		HWCAP_EDSP | HWCAP_TLS | \hwcaps
314	.long	cpu_v7_name
315	.long	v7_processor_functions
316	.long	v7wbi_tlb_fns
317	.long	v6_user_fns
318	.long	v7_cache_fns
319.endm
320
321#ifndef CONFIG_ARM_LPAE
322	/*
323	 * ARM Ltd. Cortex A5 processor.
324	 */
325	.type   __v7_ca5mp_proc_info, #object
326__v7_ca5mp_proc_info:
327	.long	0x410fc050
328	.long	0xff0ffff0
329	__v7_proc __v7_ca5mp_setup
330	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
331
332	/*
333	 * ARM Ltd. Cortex A7 processor.
334	 */
335	.type	__v7_ca7mp_proc_info, #object
336__v7_ca7mp_proc_info:
337	.long	0x410fc070
338	.long	0xff0ffff0
339	__v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
340	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
341
342	/*
343	 * ARM Ltd. Cortex A9 processor.
344	 */
345	.type   __v7_ca9mp_proc_info, #object
346__v7_ca9mp_proc_info:
347	.long	0x410fc090
348	.long	0xff0ffff0
349	__v7_proc __v7_ca9mp_setup
350	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
351#endif	/* CONFIG_ARM_LPAE */
352
353	/*
354	 * ARM Ltd. Cortex A15 processor.
355	 */
356	.type	__v7_ca15mp_proc_info, #object
357__v7_ca15mp_proc_info:
358	.long	0x410fc0f0
359	.long	0xff0ffff0
360	__v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
361	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
362
363	/*
364	 * Match any ARMv7 processor core.
365	 */
366	.type	__v7_proc_info, #object
367__v7_proc_info:
368	.long	0x000f0000		@ Required ID value
369	.long	0x000f0000		@ Mask for ID
370	__v7_proc __v7_setup
371	.size	__v7_proc_info, . - __v7_proc_info
372