xref: /linux/arch/arm/mm/proc-v7.S (revision 60e13231561b3a4c5269bfa1ef6c0569ad6f28ec) 
1/*
2 *  linux/arch/arm/mm/proc-v7.S
3 *
4 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 *  This is the "shell" of the ARMv7 processor support.
11 */
12#include <linux/init.h>
13#include <linux/linkage.h>
14#include <asm/assembler.h>
15#include <asm/asm-offsets.h>
16#include <asm/hwcap.h>
17#include <asm/pgtable-hwdef.h>
18#include <asm/pgtable.h>
19
20#include "proc-macros.S"
21
22#define TTB_S		(1 << 1)
23#define TTB_RGN_NC	(0 << 3)
24#define TTB_RGN_OC_WBWA	(1 << 3)
25#define TTB_RGN_OC_WT	(2 << 3)
26#define TTB_RGN_OC_WB	(3 << 3)
27#define TTB_NOS		(1 << 5)
28#define TTB_IRGN_NC	((0 << 0) | (0 << 6))
29#define TTB_IRGN_WBWA	((0 << 0) | (1 << 6))
30#define TTB_IRGN_WT	((1 << 0) | (0 << 6))
31#define TTB_IRGN_WB	((1 << 0) | (1 << 6))
32
33/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
34#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
35#define PMD_FLAGS_UP	PMD_SECT_WB
36
37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
38#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
39#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S
40
41ENTRY(cpu_v7_proc_init)
42	mov	pc, lr
43ENDPROC(cpu_v7_proc_init)
44
45ENTRY(cpu_v7_proc_fin)
46	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
47	bic	r0, r0, #0x1000			@ ...i............
48	bic	r0, r0, #0x0006			@ .............ca.
49	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
50	mov	pc, lr
51ENDPROC(cpu_v7_proc_fin)
52
53/*
54 *	cpu_v7_reset(loc)
55 *
56 *	Perform a soft reset of the system.  Put the CPU into the
57 *	same state as it would be if it had been reset, and branch
58 *	to what would be the reset vector.
59 *
60 *	- loc   - location to jump to for soft reset
61 *
62 *	This code must be executed using a flat identity mapping with
63 *      caches disabled.
64 */
65	.align	5
66ENTRY(cpu_v7_reset)
67	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
68	bic	r1, r1, #0x1			@ ...............m
69 THUMB(	bic	r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
70	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
71	isb
72	mov	pc, r0
73ENDPROC(cpu_v7_reset)
74
75/*
76 *	cpu_v7_do_idle()
77 *
78 *	Idle the processor (eg, wait for interrupt).
79 *
80 *	IRQs are already disabled.
81 */
82ENTRY(cpu_v7_do_idle)
83	dsb					@ WFI may enter a low-power mode
84	wfi
85	mov	pc, lr
86ENDPROC(cpu_v7_do_idle)
87
88ENTRY(cpu_v7_dcache_clean_area)
89#ifndef TLB_CAN_READ_FROM_L1_CACHE
90	dcache_line_size r2, r3
911:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
92	add	r0, r0, r2
93	subs	r1, r1, r2
94	bhi	1b
95	dsb
96#endif
97	mov	pc, lr
98ENDPROC(cpu_v7_dcache_clean_area)
99
100/*
101 *	cpu_v7_switch_mm(pgd_phys, tsk)
102 *
103 *	Set the translation table base pointer to be pgd_phys
104 *
105 *	- pgd_phys - physical address of new TTB
106 *
107 *	It is assumed that:
108 *	- we are not using split page tables
109 */
110ENTRY(cpu_v7_switch_mm)
111#ifdef CONFIG_MMU
112	mov	r2, #0
113	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
114	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)
115	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)
116#ifdef CONFIG_ARM_ERRATA_430973
117	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
118#endif
119#ifdef CONFIG_ARM_ERRATA_754322
120	dsb
121#endif
122	mcr	p15, 0, r2, c13, c0, 1		@ set reserved context ID
123	isb
1241:	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
125	isb
126#ifdef CONFIG_ARM_ERRATA_754322
127	dsb
128#endif
129	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
130	isb
131#endif
132	mov	pc, lr
133ENDPROC(cpu_v7_switch_mm)
134
135/*
136 *	cpu_v7_set_pte_ext(ptep, pte)
137 *
138 *	Set a level 2 translation table entry.
139 *
140 *	- ptep  - pointer to level 2 translation table entry
141 *		  (hardware version is stored at +2048 bytes)
142 *	- pte   - PTE value to store
143 *	- ext	- value for extended PTE bits
144 */
145ENTRY(cpu_v7_set_pte_ext)
146#ifdef CONFIG_MMU
147	str	r1, [r0]			@ linux version
148
149	bic	r3, r1, #0x000003f0
150	bic	r3, r3, #PTE_TYPE_MASK
151	orr	r3, r3, r2
152	orr	r3, r3, #PTE_EXT_AP0 | 2
153
154	tst	r1, #1 << 4
155	orrne	r3, r3, #PTE_EXT_TEX(1)
156
157	eor	r1, r1, #L_PTE_DIRTY
158	tst	r1, #L_PTE_RDONLY | L_PTE_DIRTY
159	orrne	r3, r3, #PTE_EXT_APX
160
161	tst	r1, #L_PTE_USER
162	orrne	r3, r3, #PTE_EXT_AP1
163#ifdef CONFIG_CPU_USE_DOMAINS
164	@ allow kernel read/write access to read-only user pages
165	tstne	r3, #PTE_EXT_APX
166	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
167#endif
168
169	tst	r1, #L_PTE_XN
170	orrne	r3, r3, #PTE_EXT_XN
171
172	tst	r1, #L_PTE_YOUNG
173	tstne	r1, #L_PTE_PRESENT
174	moveq	r3, #0
175
176 ARM(	str	r3, [r0, #2048]! )
177 THUMB(	add	r0, r0, #2048 )
178 THUMB(	str	r3, [r0] )
179	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
180#endif
181	mov	pc, lr
182ENDPROC(cpu_v7_set_pte_ext)
183
184	string	cpu_v7_name, "ARMv7 Processor"
185	.align
186
187	/*
188	 * Memory region attributes with SCTLR.TRE=1
189	 *
190	 *   n = TEX[0],C,B
191	 *   TR = PRRR[2n+1:2n]		- memory type
192	 *   IR = NMRR[2n+1:2n]		- inner cacheable property
193	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property
194	 *
195	 *			n	TR	IR	OR
196	 *   UNCACHED		000	00
197	 *   BUFFERABLE		001	10	00	00
198	 *   WRITETHROUGH	010	10	10	10
199	 *   WRITEBACK		011	10	11	11
200	 *   reserved		110
201	 *   WRITEALLOC		111	10	01	01
202	 *   DEV_SHARED		100	01
203	 *   DEV_NONSHARED	100	01
204	 *   DEV_WC		001	10
205	 *   DEV_CACHED		011	10
206	 *
207	 * Other attributes:
208	 *
209	 *   DS0 = PRRR[16] = 0		- device shareable property
210	 *   DS1 = PRRR[17] = 1		- device shareable property
211	 *   NS0 = PRRR[18] = 0		- normal shareable property
212	 *   NS1 = PRRR[19] = 1		- normal shareable property
213	 *   NOS = PRRR[24+n] = 1	- not outer shareable
214	 */
215.equ	PRRR,	0xff0a81a8
216.equ	NMRR,	0x40e040e0
217
218/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
219.globl	cpu_v7_suspend_size
220.equ	cpu_v7_suspend_size, 4 * 9
221#ifdef CONFIG_PM_SLEEP
222ENTRY(cpu_v7_do_suspend)
223	stmfd	sp!, {r4 - r11, lr}
224	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
225	mrc	p15, 0, r5, c13, c0, 1	@ Context ID
226	mrc	p15, 0, r6, c13, c0, 3	@ User r/o thread ID
227	stmia	r0!, {r4 - r6}
228	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
229	mrc	p15, 0, r7, c2, c0, 0	@ TTB 0
230	mrc	p15, 0, r8, c2, c0, 1	@ TTB 1
231	mrc	p15, 0, r9, c1, c0, 0	@ Control register
232	mrc	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
233	mrc	p15, 0, r11, c1, c0, 2	@ Co-processor access control
234	stmia	r0, {r6 - r11}
235	ldmfd	sp!, {r4 - r11, pc}
236ENDPROC(cpu_v7_do_suspend)
237
238ENTRY(cpu_v7_do_resume)
239	mov	ip, #0
240	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
241	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
242	ldmia	r0!, {r4 - r6}
243	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
244	mcr	p15, 0, r5, c13, c0, 1	@ Context ID
245	mcr	p15, 0, r6, c13, c0, 3	@ User r/o thread ID
246	ldmia	r0, {r6 - r11}
247	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
248	mcr	p15, 0, r7, c2, c0, 0	@ TTB 0
249	mcr	p15, 0, r8, c2, c0, 1	@ TTB 1
250	mcr	p15, 0, ip, c2, c0, 2	@ TTB control register
251	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
252	teq	r4, r10			@ Is it already set?
253	mcrne	p15, 0, r10, c1, c0, 1	@ No, so write it
254	mcr	p15, 0, r11, c1, c0, 2	@ Co-processor access control
255	ldr	r4, =PRRR		@ PRRR
256	ldr	r5, =NMRR		@ NMRR
257	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
258	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
259	isb
260	dsb
261	mov	r0, r9			@ control register
262	mov	r2, r7, lsr #14		@ get TTB0 base
263	mov	r2, r2, lsl #14
264	ldr	r3, cpu_resume_l1_flags
265	b	cpu_resume_mmu
266ENDPROC(cpu_v7_do_resume)
267cpu_resume_l1_flags:
268	ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
269	ALT_UP(.long  PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
270#endif
271
272	__CPUINIT
273
274/*
275 *	__v7_setup
276 *
277 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
278 *	on.  Return in r0 the new CP15 C1 control register setting.
279 *
280 *	We automatically detect if we have a Harvard cache, and use the
281 *	Harvard cache control instructions insead of the unified cache
282 *	control instructions.
283 *
284 *	This should be able to cover all ARMv7 cores.
285 *
286 *	It is assumed that:
287 *	- cache type register is implemented
288 */
289__v7_ca5mp_setup:
290__v7_ca9mp_setup:
291	mov	r10, #(1 << 0)			@ TLB ops broadcasting
292	b	1f
293__v7_ca15mp_setup:
294	mov	r10, #0
2951:
296#ifdef CONFIG_SMP
297	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
298	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
299	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
300	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
301	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
302	mcreq	p15, 0, r0, c1, c0, 1
303#endif
304__v7_setup:
305	adr	r12, __v7_setup_stack		@ the local stack
306	stmia	r12, {r0-r5, r7, r9, r11, lr}
307	bl	v7_flush_dcache_all
308	ldmia	r12, {r0-r5, r7, r9, r11, lr}
309
310	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
311	and	r10, r0, #0xff000000		@ ARM?
312	teq	r10, #0x41000000
313	bne	3f
314	and	r5, r0, #0x00f00000		@ variant
315	and	r6, r0, #0x0000000f		@ revision
316	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
317	ubfx	r0, r0, #4, #12			@ primary part number
318
319	/* Cortex-A8 Errata */
320	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
321	teq	r0, r10
322	bne	2f
323#ifdef CONFIG_ARM_ERRATA_430973
324	teq	r5, #0x00100000			@ only present in r1p*
325	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
326	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
327	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
328#endif
329#ifdef CONFIG_ARM_ERRATA_458693
330	teq	r6, #0x20			@ only present in r2p0
331	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
332	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
333	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
334	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
335#endif
336#ifdef CONFIG_ARM_ERRATA_460075
337	teq	r6, #0x20			@ only present in r2p0
338	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
339	tsteq	r10, #1 << 22
340	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
341	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
342#endif
343	b	3f
344
345	/* Cortex-A9 Errata */
3462:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
347	teq	r0, r10
348	bne	3f
349#ifdef CONFIG_ARM_ERRATA_742230
350	cmp	r6, #0x22			@ only present up to r2p2
351	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
352	orrle	r10, r10, #1 << 4		@ set bit #4
353	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
354#endif
355#ifdef CONFIG_ARM_ERRATA_742231
356	teq	r6, #0x20			@ present in r2p0
357	teqne	r6, #0x21			@ present in r2p1
358	teqne	r6, #0x22			@ present in r2p2
359	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
360	orreq	r10, r10, #1 << 12		@ set bit #12
361	orreq	r10, r10, #1 << 22		@ set bit #22
362	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
363#endif
364#ifdef CONFIG_ARM_ERRATA_743622
365	teq	r6, #0x20			@ present in r2p0
366	teqne	r6, #0x21			@ present in r2p1
367	teqne	r6, #0x22			@ present in r2p2
368	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
369	orreq	r10, r10, #1 << 6		@ set bit #6
370	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
371#endif
372#ifdef CONFIG_ARM_ERRATA_751472
373	cmp	r6, #0x30			@ present prior to r3p0
374	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
375	orrlt	r10, r10, #1 << 11		@ set bit #11
376	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
377#endif
378
3793:	mov	r10, #0
380#ifdef HARVARD_CACHE
381	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
382#endif
383	dsb
384#ifdef CONFIG_MMU
385	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
386	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
387	ALT_SMP(orr	r4, r4, #TTB_FLAGS_SMP)
388	ALT_UP(orr	r4, r4, #TTB_FLAGS_UP)
389	ALT_SMP(orr	r8, r8, #TTB_FLAGS_SMP)
390	ALT_UP(orr	r8, r8, #TTB_FLAGS_UP)
391	mcr	p15, 0, r8, c2, c0, 1		@ load TTB1
392	ldr	r5, =PRRR			@ PRRR
393	ldr	r6, =NMRR			@ NMRR
394	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
395	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
396#endif
397	adr	r5, v7_crval
398	ldmia	r5, {r5, r6}
399#ifdef CONFIG_CPU_ENDIAN_BE8
400	orr	r6, r6, #1 << 25		@ big-endian page tables
401#endif
402#ifdef CONFIG_SWP_EMULATE
403	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
404	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
405#endif
406   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
407	bic	r0, r0, r5			@ clear bits them
408	orr	r0, r0, r6			@ set them
409 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
410	mov	pc, lr				@ return to head.S:__ret
411ENDPROC(__v7_setup)
412
413	/*   AT
414	 *  TFR   EV X F   I D LR    S
415	 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
416	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
417	 *    1    0 110       0011 1100 .111 1101 < we want
418	 */
419	.type	v7_crval, #object
420v7_crval:
421	crval	clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
422
423__v7_setup_stack:
424	.space	4 * 11				@ 11 registers
425
426	__INITDATA
427
428	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
429	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
430
431	.section ".rodata"
432
433	string	cpu_arch_name, "armv7"
434	string	cpu_elf_name, "v7"
435	.align
436
437	.section ".proc.info.init", #alloc, #execinstr
438
439	/*
440	 * Standard v7 proc info content
441	 */
442.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
443	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
444			PMD_FLAGS_SMP | \mm_mmuflags)
445	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
446			PMD_FLAGS_UP | \mm_mmuflags)
447	.long	PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \
448		PMD_SECT_AP_READ | \io_mmuflags
449	W(b)	\initfunc
450	.long	cpu_arch_name
451	.long	cpu_elf_name
452	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
453		HWCAP_EDSP | HWCAP_TLS | \hwcaps
454	.long	cpu_v7_name
455	.long	v7_processor_functions
456	.long	v7wbi_tlb_fns
457	.long	v6_user_fns
458	.long	v7_cache_fns
459.endm
460
461	/*
462	 * ARM Ltd. Cortex A5 processor.
463	 */
464	.type   __v7_ca5mp_proc_info, #object
465__v7_ca5mp_proc_info:
466	.long	0x410fc050
467	.long	0xff0ffff0
468	__v7_proc __v7_ca5mp_setup
469	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
470
471	/*
472	 * ARM Ltd. Cortex A9 processor.
473	 */
474	.type   __v7_ca9mp_proc_info, #object
475__v7_ca9mp_proc_info:
476	.long	0x410fc090
477	.long	0xff0ffff0
478	__v7_proc __v7_ca9mp_setup
479	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
480
481	/*
482	 * ARM Ltd. Cortex A15 processor.
483	 */
484	.type	__v7_ca15mp_proc_info, #object
485__v7_ca15mp_proc_info:
486	.long	0x410fc0f0
487	.long	0xff0ffff0
488	__v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
489	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
490
491	/*
492	 * Match any ARMv7 processor core.
493	 */
494	.type	__v7_proc_info, #object
495__v7_proc_info:
496	.long	0x000f0000		@ Required ID value
497	.long	0x000f0000		@ Mask for ID
498	__v7_proc __v7_setup
499	.size	__v7_proc_info, . - __v7_proc_info
500