1/* 2 * linux/arch/arm/mm/proc-v7.S 3 * 4 * Copyright (C) 2001 Deep Blue Solutions Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This is the "shell" of the ARMv7 processor support. 11 */ 12#include <linux/init.h> 13#include <linux/linkage.h> 14#include <asm/assembler.h> 15#include <asm/asm-offsets.h> 16#include <asm/hwcap.h> 17#include <asm/pgtable-hwdef.h> 18#include <asm/pgtable.h> 19 20#include "proc-macros.S" 21 22#define TTB_S (1 << 1) 23#define TTB_RGN_NC (0 << 3) 24#define TTB_RGN_OC_WBWA (1 << 3) 25#define TTB_RGN_OC_WT (2 << 3) 26#define TTB_RGN_OC_WB (3 << 3) 27#define TTB_NOS (1 << 5) 28#define TTB_IRGN_NC ((0 << 0) | (0 << 6)) 29#define TTB_IRGN_WBWA ((0 << 0) | (1 << 6)) 30#define TTB_IRGN_WT ((1 << 0) | (0 << 6)) 31#define TTB_IRGN_WB ((1 << 0) | (1 << 6)) 32 33#ifndef CONFIG_SMP 34/* PTWs cacheable, inner WB not shareable, outer WB not shareable */ 35#define TTB_FLAGS TTB_IRGN_WB|TTB_RGN_OC_WB 36#else 37/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ 38#define TTB_FLAGS TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA 39#endif 40 41ENTRY(cpu_v7_proc_init) 42 mov pc, lr 43ENDPROC(cpu_v7_proc_init) 44 45ENTRY(cpu_v7_proc_fin) 46 mov pc, lr 47ENDPROC(cpu_v7_proc_fin) 48 49/* 50 * cpu_v7_reset(loc) 51 * 52 * Perform a soft reset of the system. Put the CPU into the 53 * same state as it would be if it had been reset, and branch 54 * to what would be the reset vector. 55 * 56 * - loc - location to jump to for soft reset 57 * 58 * It is assumed that: 59 */ 60 .align 5 61ENTRY(cpu_v7_reset) 62 mov pc, r0 63ENDPROC(cpu_v7_reset) 64 65/* 66 * cpu_v7_do_idle() 67 * 68 * Idle the processor (eg, wait for interrupt). 69 * 70 * IRQs are already disabled. 71 */ 72ENTRY(cpu_v7_do_idle) 73 dsb @ WFI may enter a low-power mode 74 wfi 75 mov pc, lr 76ENDPROC(cpu_v7_do_idle) 77 78ENTRY(cpu_v7_dcache_clean_area) 79#ifndef TLB_CAN_READ_FROM_L1_CACHE 80 dcache_line_size r2, r3 811: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 82 add r0, r0, r2 83 subs r1, r1, r2 84 bhi 1b 85 dsb 86#endif 87 mov pc, lr 88ENDPROC(cpu_v7_dcache_clean_area) 89 90/* 91 * cpu_v7_switch_mm(pgd_phys, tsk) 92 * 93 * Set the translation table base pointer to be pgd_phys 94 * 95 * - pgd_phys - physical address of new TTB 96 * 97 * It is assumed that: 98 * - we are not using split page tables 99 */ 100ENTRY(cpu_v7_switch_mm) 101#ifdef CONFIG_MMU 102 mov r2, #0 103 ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id 104 orr r0, r0, #TTB_FLAGS 105#ifdef CONFIG_ARM_ERRATA_430973 106 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 107#endif 108 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID 109 isb 1101: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 111 isb 112 mcr p15, 0, r1, c13, c0, 1 @ set context ID 113 isb 114#endif 115 mov pc, lr 116ENDPROC(cpu_v7_switch_mm) 117 118/* 119 * cpu_v7_set_pte_ext(ptep, pte) 120 * 121 * Set a level 2 translation table entry. 122 * 123 * - ptep - pointer to level 2 translation table entry 124 * (hardware version is stored at -1024 bytes) 125 * - pte - PTE value to store 126 * - ext - value for extended PTE bits 127 */ 128ENTRY(cpu_v7_set_pte_ext) 129#ifdef CONFIG_MMU 130 str r1, [r0], #-2048 @ linux version 131 132 bic r3, r1, #0x000003f0 133 bic r3, r3, #PTE_TYPE_MASK 134 orr r3, r3, r2 135 orr r3, r3, #PTE_EXT_AP0 | 2 136 137 tst r1, #1 << 4 138 orrne r3, r3, #PTE_EXT_TEX(1) 139 140 tst r1, #L_PTE_WRITE 141 tstne r1, #L_PTE_DIRTY 142 orreq r3, r3, #PTE_EXT_APX 143 144 tst r1, #L_PTE_USER 145 orrne r3, r3, #PTE_EXT_AP1 146 tstne r3, #PTE_EXT_APX 147 bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 148 149 tst r1, #L_PTE_EXEC 150 orreq r3, r3, #PTE_EXT_XN 151 152 tst r1, #L_PTE_YOUNG 153 tstne r1, #L_PTE_PRESENT 154 moveq r3, #0 155 156 str r3, [r0] 157 mcr p15, 0, r0, c7, c10, 1 @ flush_pte 158#endif 159 mov pc, lr 160ENDPROC(cpu_v7_set_pte_ext) 161 162cpu_v7_name: 163 .ascii "ARMv7 Processor" 164 .align 165 166 __INIT 167 168/* 169 * __v7_setup 170 * 171 * Initialise TLB, Caches, and MMU state ready to switch the MMU 172 * on. Return in r0 the new CP15 C1 control register setting. 173 * 174 * We automatically detect if we have a Harvard cache, and use the 175 * Harvard cache control instructions insead of the unified cache 176 * control instructions. 177 * 178 * This should be able to cover all ARMv7 cores. 179 * 180 * It is assumed that: 181 * - cache type register is implemented 182 */ 183__v7_setup: 184#ifdef CONFIG_SMP 185 mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode and 186 orr r0, r0, #(1 << 6) | (1 << 0) @ TLB ops broadcasting 187 mcr p15, 0, r0, c1, c0, 1 188#endif 189 adr r12, __v7_setup_stack @ the local stack 190 stmia r12, {r0-r5, r7, r9, r11, lr} 191 bl v7_flush_dcache_all 192 ldmia r12, {r0-r5, r7, r9, r11, lr} 193 194 mrc p15, 0, r0, c0, c0, 0 @ read main ID register 195 and r10, r0, #0xff000000 @ ARM? 196 teq r10, #0x41000000 197 bne 2f 198 and r5, r0, #0x00f00000 @ variant 199 and r6, r0, #0x0000000f @ revision 200 orr r0, r6, r5, lsr #20-4 @ combine variant and revision 201 202#ifdef CONFIG_ARM_ERRATA_430973 203 teq r5, #0x00100000 @ only present in r1p* 204 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 205 orreq r10, r10, #(1 << 6) @ set IBE to 1 206 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 207#endif 208#ifdef CONFIG_ARM_ERRATA_458693 209 teq r0, #0x20 @ only present in r2p0 210 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 211 orreq r10, r10, #(1 << 5) @ set L1NEON to 1 212 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 213 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 214#endif 215#ifdef CONFIG_ARM_ERRATA_460075 216 teq r0, #0x20 @ only present in r2p0 217 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register 218 tsteq r10, #1 << 22 219 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit 220 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register 221#endif 222 2232: mov r10, #0 224#ifdef HARVARD_CACHE 225 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate 226#endif 227 dsb 228#ifdef CONFIG_MMU 229 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs 230 mcr p15, 0, r10, c2, c0, 2 @ TTB control register 231 orr r4, r4, #TTB_FLAGS 232 mcr p15, 0, r4, c2, c0, 1 @ load TTB1 233 mov r10, #0x1f @ domains 0, 1 = manager 234 mcr p15, 0, r10, c3, c0, 0 @ load domain access register 235#endif 236 /* 237 * Memory region attributes with SCTLR.TRE=1 238 * 239 * n = TEX[0],C,B 240 * TR = PRRR[2n+1:2n] - memory type 241 * IR = NMRR[2n+1:2n] - inner cacheable property 242 * OR = NMRR[2n+17:2n+16] - outer cacheable property 243 * 244 * n TR IR OR 245 * UNCACHED 000 00 246 * BUFFERABLE 001 10 00 00 247 * WRITETHROUGH 010 10 10 10 248 * WRITEBACK 011 10 11 11 249 * reserved 110 250 * WRITEALLOC 111 10 01 01 251 * DEV_SHARED 100 01 252 * DEV_NONSHARED 100 01 253 * DEV_WC 001 10 254 * DEV_CACHED 011 10 255 * 256 * Other attributes: 257 * 258 * DS0 = PRRR[16] = 0 - device shareable property 259 * DS1 = PRRR[17] = 1 - device shareable property 260 * NS0 = PRRR[18] = 0 - normal shareable property 261 * NS1 = PRRR[19] = 1 - normal shareable property 262 * NOS = PRRR[24+n] = 1 - not outer shareable 263 */ 264 ldr r5, =0xff0a81a8 @ PRRR 265 ldr r6, =0x40e040e0 @ NMRR 266 mcr p15, 0, r5, c10, c2, 0 @ write PRRR 267 mcr p15, 0, r6, c10, c2, 1 @ write NMRR 268 adr r5, v7_crval 269 ldmia r5, {r5, r6} 270#ifdef CONFIG_CPU_ENDIAN_BE8 271 orr r6, r6, #1 << 25 @ big-endian page tables 272#endif 273 mrc p15, 0, r0, c1, c0, 0 @ read control register 274 bic r0, r0, r5 @ clear bits them 275 orr r0, r0, r6 @ set them 276 mov pc, lr @ return to head.S:__ret 277ENDPROC(__v7_setup) 278 279 /* AT 280 * TFR EV X F I D LR S 281 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM 282 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced 283 * 1 0 110 0011 1100 .111 1101 < we want 284 */ 285 .type v7_crval, #object 286v7_crval: 287 crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c 288 289__v7_setup_stack: 290 .space 4 * 11 @ 11 registers 291 292 .type v7_processor_functions, #object 293ENTRY(v7_processor_functions) 294 .word v7_early_abort 295 .word pabort_ifar 296 .word cpu_v7_proc_init 297 .word cpu_v7_proc_fin 298 .word cpu_v7_reset 299 .word cpu_v7_do_idle 300 .word cpu_v7_dcache_clean_area 301 .word cpu_v7_switch_mm 302 .word cpu_v7_set_pte_ext 303 .size v7_processor_functions, . - v7_processor_functions 304 305 .type cpu_arch_name, #object 306cpu_arch_name: 307 .asciz "armv7" 308 .size cpu_arch_name, . - cpu_arch_name 309 310 .type cpu_elf_name, #object 311cpu_elf_name: 312 .asciz "v7" 313 .size cpu_elf_name, . - cpu_elf_name 314 .align 315 316 .section ".proc.info.init", #alloc, #execinstr 317 318 /* 319 * Match any ARMv7 processor core. 320 */ 321 .type __v7_proc_info, #object 322__v7_proc_info: 323 .long 0x000f0000 @ Required ID value 324 .long 0x000f0000 @ Mask for ID 325 .long PMD_TYPE_SECT | \ 326 PMD_SECT_BUFFERABLE | \ 327 PMD_SECT_CACHEABLE | \ 328 PMD_SECT_AP_WRITE | \ 329 PMD_SECT_AP_READ 330 .long PMD_TYPE_SECT | \ 331 PMD_SECT_XN | \ 332 PMD_SECT_AP_WRITE | \ 333 PMD_SECT_AP_READ 334 b __v7_setup 335 .long cpu_arch_name 336 .long cpu_elf_name 337 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 338 .long cpu_v7_name 339 .long v7_processor_functions 340 .long v7wbi_tlb_fns 341 .long v6_user_fns 342 .long v7_cache_fns 343 .size __v7_proc_info, . - __v7_proc_info 344