1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/arm-smccc.h> 3 #include <linux/kernel.h> 4 #include <linux/smp.h> 5 6 #include <asm/cp15.h> 7 #include <asm/cputype.h> 8 #include <asm/proc-fns.h> 9 #include <asm/system_misc.h> 10 11 #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR 12 DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn); 13 14 extern void cpu_v7_iciallu_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); 15 extern void cpu_v7_bpiall_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); 16 extern void cpu_v7_smc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); 17 extern void cpu_v7_hvc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); 18 19 static void harden_branch_predictor_bpiall(void) 20 { 21 write_sysreg(0, BPIALL); 22 } 23 24 static void harden_branch_predictor_iciallu(void) 25 { 26 write_sysreg(0, ICIALLU); 27 } 28 29 static void __maybe_unused call_smc_arch_workaround_1(void) 30 { 31 arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); 32 } 33 34 static void __maybe_unused call_hvc_arch_workaround_1(void) 35 { 36 arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); 37 } 38 39 static void cpu_v7_spectre_init(void) 40 { 41 const char *spectre_v2_method = NULL; 42 int cpu = smp_processor_id(); 43 44 if (per_cpu(harden_branch_predictor_fn, cpu)) 45 return; 46 47 switch (read_cpuid_part()) { 48 case ARM_CPU_PART_CORTEX_A8: 49 case ARM_CPU_PART_CORTEX_A9: 50 case ARM_CPU_PART_CORTEX_A12: 51 case ARM_CPU_PART_CORTEX_A17: 52 case ARM_CPU_PART_CORTEX_A73: 53 case ARM_CPU_PART_CORTEX_A75: 54 per_cpu(harden_branch_predictor_fn, cpu) = 55 harden_branch_predictor_bpiall; 56 spectre_v2_method = "BPIALL"; 57 break; 58 59 case ARM_CPU_PART_CORTEX_A15: 60 case ARM_CPU_PART_BRAHMA_B15: 61 per_cpu(harden_branch_predictor_fn, cpu) = 62 harden_branch_predictor_iciallu; 63 spectre_v2_method = "ICIALLU"; 64 break; 65 66 #ifdef CONFIG_ARM_PSCI 67 case ARM_CPU_PART_BRAHMA_B53: 68 /* Requires no workaround */ 69 break; 70 default: 71 /* Other ARM CPUs require no workaround */ 72 if (read_cpuid_implementor() == ARM_CPU_IMP_ARM) 73 break; 74 /* fallthrough */ 75 /* Cortex A57/A72 require firmware workaround */ 76 case ARM_CPU_PART_CORTEX_A57: 77 case ARM_CPU_PART_CORTEX_A72: { 78 struct arm_smccc_res res; 79 80 arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, 81 ARM_SMCCC_ARCH_WORKAROUND_1, &res); 82 if ((int)res.a0 != 0) 83 return; 84 85 switch (arm_smccc_1_1_get_conduit()) { 86 case SMCCC_CONDUIT_HVC: 87 per_cpu(harden_branch_predictor_fn, cpu) = 88 call_hvc_arch_workaround_1; 89 cpu_do_switch_mm = cpu_v7_hvc_switch_mm; 90 spectre_v2_method = "hypervisor"; 91 break; 92 93 case SMCCC_CONDUIT_SMC: 94 per_cpu(harden_branch_predictor_fn, cpu) = 95 call_smc_arch_workaround_1; 96 cpu_do_switch_mm = cpu_v7_smc_switch_mm; 97 spectre_v2_method = "firmware"; 98 break; 99 100 default: 101 break; 102 } 103 } 104 #endif 105 } 106 107 if (spectre_v2_method) 108 pr_info("CPU%u: Spectre v2: using %s workaround\n", 109 smp_processor_id(), spectre_v2_method); 110 } 111 #else 112 static void cpu_v7_spectre_init(void) 113 { 114 } 115 #endif 116 117 static __maybe_unused bool cpu_v7_check_auxcr_set(bool *warned, 118 u32 mask, const char *msg) 119 { 120 u32 aux_cr; 121 122 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (aux_cr)); 123 124 if ((aux_cr & mask) != mask) { 125 if (!*warned) 126 pr_err("CPU%u: %s", smp_processor_id(), msg); 127 *warned = true; 128 return false; 129 } 130 return true; 131 } 132 133 static DEFINE_PER_CPU(bool, spectre_warned); 134 135 static bool check_spectre_auxcr(bool *warned, u32 bit) 136 { 137 return IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR) && 138 cpu_v7_check_auxcr_set(warned, bit, 139 "Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable\n"); 140 } 141 142 void cpu_v7_ca8_ibe(void) 143 { 144 if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6))) 145 cpu_v7_spectre_init(); 146 } 147 148 void cpu_v7_ca15_ibe(void) 149 { 150 if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0))) 151 cpu_v7_spectre_init(); 152 } 153 154 void cpu_v7_bugs_init(void) 155 { 156 cpu_v7_spectre_init(); 157 } 158